Commit d01c6236 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher

drm/amdgpu: refine uvd pg code in kv_dpm.c

1. no need to set cg as use hw dynamic cg.
2. when uvd idle, stop uvd. encode, start uvd.
3. if pg feature enabled, power on/down uvd by smu.
4. drm/amdgpu: dpm do not set uvd pg status.
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3a786966
...@@ -1688,38 +1688,25 @@ static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate) ...@@ -1688,38 +1688,25 @@ static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
struct kv_power_info *pi = kv_get_pi(adev); struct kv_power_info *pi = kv_get_pi(adev);
int ret; int ret;
if (pi->uvd_power_gated == gate)
return;
pi->uvd_power_gated = gate; pi->uvd_power_gated = gate;
if (gate) { if (gate) {
if (pi->caps_uvd_pg) { /* stop the UVD block */
/* disable clockgating so we can properly shut down the block */ ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, AMD_PG_STATE_GATE);
AMD_CG_STATE_UNGATE);
/* shutdown the UVD block */
ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
AMD_PG_STATE_GATE);
/* XXX: check for errors */
}
kv_update_uvd_dpm(adev, gate); kv_update_uvd_dpm(adev, gate);
if (pi->caps_uvd_pg) if (pi->caps_uvd_pg)
/* power off the UVD block */ /* power off the UVD block */
amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerOFF); amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerOFF);
} else { } else {
if (pi->caps_uvd_pg) { if (pi->caps_uvd_pg)
/* power on the UVD block */ /* power on the UVD block */
amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON); amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON);
/* re-init the UVD block */ /* re-init the UVD block */
ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
AMD_PG_STATE_UNGATE);
/* enable clockgating. hw will dynamically gate/ungate clocks on the fly */
ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
AMD_CG_STATE_GATE);
/* XXX: check for errors */
}
kv_update_uvd_dpm(adev, gate); kv_update_uvd_dpm(adev, gate);
ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
AMD_PG_STATE_UNGATE);
} }
} }
...@@ -3010,7 +2997,7 @@ static int kv_dpm_late_init(void *handle) ...@@ -3010,7 +2997,7 @@ static int kv_dpm_late_init(void *handle)
kv_dpm_powergate_acp(adev, true); kv_dpm_powergate_acp(adev, true);
kv_dpm_powergate_samu(adev, true); kv_dpm_powergate_samu(adev, true);
kv_dpm_powergate_vce(adev, true); kv_dpm_powergate_vce(adev, true);
kv_dpm_powergate_uvd(adev, true);
return 0; return 0;
} }
......
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