Commit d092106d authored by James Morse's avatar James Morse Committed by Will Deacon

arm64/sysreg: Standardise naming for ID_DFR1_EL1

To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.

Ensure symbols for the ID_DFR1_EL1 register have an _EL1 suffix.

No functional change.
Signed-off-by: default avatarJames Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20221130171637.718182-13-james.morse@arm.comSigned-off-by: default avatarWill Deacon <will@kernel.org>
parent f4f5969e
...@@ -706,7 +706,7 @@ ...@@ -706,7 +706,7 @@
#define ID_ISAR4_EL1_WithShifts_SHIFT 4 #define ID_ISAR4_EL1_WithShifts_SHIFT 4
#define ID_ISAR4_EL1_Unpriv_SHIFT 0 #define ID_ISAR4_EL1_Unpriv_SHIFT 0
#define ID_DFR1_MTPMU_SHIFT 0 #define ID_DFR1_EL1_MTPMU_SHIFT 0
#define ID_ISAR0_EL1_Divide_SHIFT 24 #define ID_ISAR0_EL1_Divide_SHIFT 24
#define ID_ISAR0_EL1_Debug_SHIFT 20 #define ID_ISAR0_EL1_Debug_SHIFT 20
......
...@@ -578,7 +578,7 @@ static const struct arm64_ftr_bits ftr_id_dfr0[] = { ...@@ -578,7 +578,7 @@ static const struct arm64_ftr_bits ftr_id_dfr0[] = {
}; };
static const struct arm64_ftr_bits ftr_id_dfr1[] = { static const struct arm64_ftr_bits ftr_id_dfr1[] = {
S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0), S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0),
ARM64_FTR_END, ARM64_FTR_END,
}; };
......
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