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Commit d0c3b04a authored by Zhao Yakui's avatar Zhao Yakui Committed by Eric Anholt
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drm/i915: Replace DRM_DEBUG with DRM_DEBUG_KMS in DVO output code. 

Signed-off-by: default avatarZhao Yakui <yakui.zhao@intel.com>
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent 3e0f27ed
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Inline Side-by-side
Showing with 61 additions and 55 deletions
drivers/gpu/drm/i915/dvo_ch7017.c
View file @ d0c3b04a
...@@ -249,7 +249,8 @@ static bool ch7017_init(struct intel_dvo_device *dvo, ...@@ -249,7 +249,8 @@ static bool ch7017_init(struct intel_dvo_device *dvo,
if (val != CH7017_DEVICE_ID_VALUE && if (val != CH7017_DEVICE_ID_VALUE &&
val != CH7018_DEVICE_ID_VALUE && val != CH7018_DEVICE_ID_VALUE &&
val != CH7019_DEVICE_ID_VALUE) { val != CH7019_DEVICE_ID_VALUE) {
DRM_DEBUG("ch701x not detected, got %d: from %s Slave %d.\n", DRM_DEBUG_KMS("ch701x not detected, got %d: from %s "
"Slave %d.\n",
val, i2cbus->adapter.name,dvo->slave_addr); val, i2cbus->adapter.name,dvo->slave_addr);
goto fail; goto fail;
} }
...@@ -284,7 +285,7 @@ static void ch7017_mode_set(struct intel_dvo_device *dvo, ...@@ -284,7 +285,7 @@ static void ch7017_mode_set(struct intel_dvo_device *dvo,
uint8_t horizontal_active_pixel_output, vertical_active_line_output; uint8_t horizontal_active_pixel_output, vertical_active_line_output;
uint8_t active_input_line_output; uint8_t active_input_line_output;
DRM_DEBUG("Registers before mode setting\n"); DRM_DEBUG_KMS("Registers before mode setting\n");
ch7017_dump_regs(dvo); ch7017_dump_regs(dvo);
/* LVDS PLL settings from page 75 of 7017-7017ds.pdf*/ /* LVDS PLL settings from page 75 of 7017-7017ds.pdf*/
...@@ -346,7 +347,7 @@ static void ch7017_mode_set(struct intel_dvo_device *dvo, ...@@ -346,7 +347,7 @@ static void ch7017_mode_set(struct intel_dvo_device *dvo,
/* Turn the LVDS back on with new settings. */ /* Turn the LVDS back on with new settings. */
ch7017_write(dvo, CH7017_LVDS_POWER_DOWN, lvds_power_down); ch7017_write(dvo, CH7017_LVDS_POWER_DOWN, lvds_power_down);
DRM_DEBUG("Registers after mode setting\n"); DRM_DEBUG_KMS("Registers after mode setting\n");
ch7017_dump_regs(dvo); ch7017_dump_regs(dvo);
} }
...@@ -386,7 +387,7 @@ static void ch7017_dump_regs(struct intel_dvo_device *dvo) ...@@ -386,7 +387,7 @@ static void ch7017_dump_regs(struct intel_dvo_device *dvo)
#define DUMP(reg) \ #define DUMP(reg) \
do { \ do { \
ch7017_read(dvo, reg, &val); \ ch7017_read(dvo, reg, &val); \
DRM_DEBUG(#reg ": %02x\n", val); \ DRM_DEBUG_KMS(#reg ": %02x\n", val); \
} while (0) } while (0)
DUMP(CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT); DUMP(CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT);
......
drivers/gpu/drm/i915/dvo_ch7xxx.c
View file @ d0c3b04a
...@@ -152,7 +152,7 @@ static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch) ...@@ -152,7 +152,7 @@ static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
}; };
if (!ch7xxx->quiet) { if (!ch7xxx->quiet) {
DRM_DEBUG("Unable to read register 0x%02x from %s:%02x.\n", DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
addr, i2cbus->adapter.name, dvo->slave_addr); addr, i2cbus->adapter.name, dvo->slave_addr);
} }
return false; return false;
...@@ -179,7 +179,7 @@ static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch) ...@@ -179,7 +179,7 @@ static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
return true; return true;
if (!ch7xxx->quiet) { if (!ch7xxx->quiet) {
DRM_DEBUG("Unable to write register 0x%02x to %s:%d.\n", DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
addr, i2cbus->adapter.name, dvo->slave_addr); addr, i2cbus->adapter.name, dvo->slave_addr);
} }
...@@ -207,7 +207,8 @@ static bool ch7xxx_init(struct intel_dvo_device *dvo, ...@@ -207,7 +207,8 @@ static bool ch7xxx_init(struct intel_dvo_device *dvo,
name = ch7xxx_get_id(vendor); name = ch7xxx_get_id(vendor);
if (!name) { if (!name) {
DRM_DEBUG("ch7xxx not detected; got 0x%02x from %s slave %d.\n", DRM_DEBUG_KMS("ch7xxx not detected; got 0x%02x from %s "
"slave %d.\n",
vendor, adapter->name, dvo->slave_addr); vendor, adapter->name, dvo->slave_addr);
goto out; goto out;
} }
...@@ -217,13 +218,14 @@ static bool ch7xxx_init(struct intel_dvo_device *dvo, ...@@ -217,13 +218,14 @@ static bool ch7xxx_init(struct intel_dvo_device *dvo,
goto out; goto out;
if (device != CH7xxx_DID) { if (device != CH7xxx_DID) {
DRM_DEBUG("ch7xxx not detected; got 0x%02x from %s slave %d.\n", DRM_DEBUG_KMS("ch7xxx not detected; got 0x%02x from %s "
"slave %d.\n",
vendor, adapter->name, dvo->slave_addr); vendor, adapter->name, dvo->slave_addr);
goto out; goto out;
} }
ch7xxx->quiet = false; ch7xxx->quiet = false;
DRM_DEBUG("Detected %s chipset, vendor/device ID 0x%02x/0x%02x\n", DRM_DEBUG_KMS("Detected %s chipset, vendor/device ID 0x%02x/0x%02x\n",
name, vendor, device); name, vendor, device);
return true; return true;
out: out:
...@@ -315,8 +317,8 @@ static void ch7xxx_dump_regs(struct intel_dvo_device *dvo) ...@@ -315,8 +317,8 @@ static void ch7xxx_dump_regs(struct intel_dvo_device *dvo)
for (i = 0; i < CH7xxx_NUM_REGS; i++) { for (i = 0; i < CH7xxx_NUM_REGS; i++) {
if ((i % 8) == 0 ) if ((i % 8) == 0 )
DRM_DEBUG("\n %02X: ", i); DRM_LOG_KMS("\n %02X: ", i);
DRM_DEBUG("%02X ", ch7xxx->mode_reg.regs[i]); DRM_LOG_KMS("%02X ", ch7xxx->mode_reg.regs[i]);
} }
} }
......
drivers/gpu/drm/i915/dvo_ivch.c
View file @ d0c3b04a
...@@ -202,7 +202,8 @@ static bool ivch_read(struct intel_dvo_device *dvo, int addr, uint16_t *data) ...@@ -202,7 +202,8 @@ static bool ivch_read(struct intel_dvo_device *dvo, int addr, uint16_t *data)
}; };
if (!priv->quiet) { if (!priv->quiet) {
DRM_DEBUG("Unable to read register 0x%02x from %s:%02x.\n", DRM_DEBUG_KMS("Unable to read register 0x%02x from "
"%s:%02x.\n",
addr, i2cbus->adapter.name, dvo->slave_addr); addr, i2cbus->adapter.name, dvo->slave_addr);
} }
return false; return false;
...@@ -230,7 +231,7 @@ static bool ivch_write(struct intel_dvo_device *dvo, int addr, uint16_t data) ...@@ -230,7 +231,7 @@ static bool ivch_write(struct intel_dvo_device *dvo, int addr, uint16_t data)
return true; return true;
if (!priv->quiet) { if (!priv->quiet) {
DRM_DEBUG("Unable to write register 0x%02x to %s:%d.\n", DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
addr, i2cbus->adapter.name, dvo->slave_addr); addr, i2cbus->adapter.name, dvo->slave_addr);
} }
...@@ -261,7 +262,7 @@ static bool ivch_init(struct intel_dvo_device *dvo, ...@@ -261,7 +262,7 @@ static bool ivch_init(struct intel_dvo_device *dvo,
* the address it's responding on. * the address it's responding on.
*/ */
if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->slave_addr) { if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->slave_addr) {
DRM_DEBUG("ivch detect failed due to address mismatch " DRM_DEBUG_KMS("ivch detect failed due to address mismatch "
"(%d vs %d)\n", "(%d vs %d)\n",
(temp & VR00_BASE_ADDRESS_MASK), dvo->slave_addr); (temp & VR00_BASE_ADDRESS_MASK), dvo->slave_addr);
goto out; goto out;
...@@ -367,41 +368,41 @@ static void ivch_dump_regs(struct intel_dvo_device *dvo) ...@@ -367,41 +368,41 @@ static void ivch_dump_regs(struct intel_dvo_device *dvo)
uint16_t val; uint16_t val;
ivch_read(dvo, VR00, &val); ivch_read(dvo, VR00, &val);
DRM_DEBUG("VR00: 0x%04x\n", val); DRM_LOG_KMS("VR00: 0x%04x\n", val);
ivch_read(dvo, VR01, &val); ivch_read(dvo, VR01, &val);
DRM_DEBUG("VR01: 0x%04x\n", val); DRM_LOG_KMS("VR01: 0x%04x\n", val);
ivch_read(dvo, VR30, &val); ivch_read(dvo, VR30, &val);
DRM_DEBUG("VR30: 0x%04x\n", val); DRM_LOG_KMS("VR30: 0x%04x\n", val);
ivch_read(dvo, VR40, &val); ivch_read(dvo, VR40, &val);
DRM_DEBUG("VR40: 0x%04x\n", val); DRM_LOG_KMS("VR40: 0x%04x\n", val);
/* GPIO registers */ /* GPIO registers */
ivch_read(dvo, VR80, &val); ivch_read(dvo, VR80, &val);
DRM_DEBUG("VR80: 0x%04x\n", val); DRM_LOG_KMS("VR80: 0x%04x\n", val);
ivch_read(dvo, VR81, &val); ivch_read(dvo, VR81, &val);
DRM_DEBUG("VR81: 0x%04x\n", val); DRM_LOG_KMS("VR81: 0x%04x\n", val);
ivch_read(dvo, VR82, &val); ivch_read(dvo, VR82, &val);
DRM_DEBUG("VR82: 0x%04x\n", val); DRM_LOG_KMS("VR82: 0x%04x\n", val);
ivch_read(dvo, VR83, &val); ivch_read(dvo, VR83, &val);
DRM_DEBUG("VR83: 0x%04x\n", val); DRM_LOG_KMS("VR83: 0x%04x\n", val);
ivch_read(dvo, VR84, &val); ivch_read(dvo, VR84, &val);
DRM_DEBUG("VR84: 0x%04x\n", val); DRM_LOG_KMS("VR84: 0x%04x\n", val);
ivch_read(dvo, VR85, &val); ivch_read(dvo, VR85, &val);
DRM_DEBUG("VR85: 0x%04x\n", val); DRM_LOG_KMS("VR85: 0x%04x\n", val);
ivch_read(dvo, VR86, &val); ivch_read(dvo, VR86, &val);
DRM_DEBUG("VR86: 0x%04x\n", val); DRM_LOG_KMS("VR86: 0x%04x\n", val);
ivch_read(dvo, VR87, &val); ivch_read(dvo, VR87, &val);
DRM_DEBUG("VR87: 0x%04x\n", val); DRM_LOG_KMS("VR87: 0x%04x\n", val);
ivch_read(dvo, VR88, &val); ivch_read(dvo, VR88, &val);
DRM_DEBUG("VR88: 0x%04x\n", val); DRM_LOG_KMS("VR88: 0x%04x\n", val);
/* Scratch register 0 - AIM Panel type */ /* Scratch register 0 - AIM Panel type */
ivch_read(dvo, VR8E, &val); ivch_read(dvo, VR8E, &val);
DRM_DEBUG("VR8E: 0x%04x\n", val); DRM_LOG_KMS("VR8E: 0x%04x\n", val);
/* Scratch register 1 - Status register */ /* Scratch register 1 - Status register */
ivch_read(dvo, VR8F, &val); ivch_read(dvo, VR8F, &val);
DRM_DEBUG("VR8F: 0x%04x\n", val); DRM_LOG_KMS("VR8F: 0x%04x\n", val);
} }
static void ivch_save(struct intel_dvo_device *dvo) static void ivch_save(struct intel_dvo_device *dvo)
......
drivers/gpu/drm/i915/dvo_sil164.c
View file @ d0c3b04a
...@@ -105,7 +105,7 @@ static bool sil164_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch) ...@@ -105,7 +105,7 @@ static bool sil164_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
}; };
if (!sil->quiet) { if (!sil->quiet) {
DRM_DEBUG("Unable to read register 0x%02x from %s:%02x.\n", DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
addr, i2cbus->adapter.name, dvo->slave_addr); addr, i2cbus->adapter.name, dvo->slave_addr);
} }
return false; return false;
...@@ -131,7 +131,7 @@ static bool sil164_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch) ...@@ -131,7 +131,7 @@ static bool sil164_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
return true; return true;
if (!sil->quiet) { if (!sil->quiet) {
DRM_DEBUG("Unable to write register 0x%02x to %s:%d.\n", DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
addr, i2cbus->adapter.name, dvo->slave_addr); addr, i2cbus->adapter.name, dvo->slave_addr);
} }
...@@ -158,7 +158,7 @@ static bool sil164_init(struct intel_dvo_device *dvo, ...@@ -158,7 +158,7 @@ static bool sil164_init(struct intel_dvo_device *dvo,
goto out; goto out;
if (ch != (SIL164_VID & 0xff)) { if (ch != (SIL164_VID & 0xff)) {
DRM_DEBUG("sil164 not detected got %d: from %s Slave %d.\n", DRM_DEBUG_KMS("sil164 not detected got %d: from %s Slave %d.\n",
ch, adapter->name, dvo->slave_addr); ch, adapter->name, dvo->slave_addr);
goto out; goto out;
} }
...@@ -167,13 +167,13 @@ static bool sil164_init(struct intel_dvo_device *dvo, ...@@ -167,13 +167,13 @@ static bool sil164_init(struct intel_dvo_device *dvo,
goto out; goto out;
if (ch != (SIL164_DID & 0xff)) { if (ch != (SIL164_DID & 0xff)) {
DRM_DEBUG("sil164 not detected got %d: from %s Slave %d.\n", DRM_DEBUG_KMS("sil164 not detected got %d: from %s Slave %d.\n",
ch, adapter->name, dvo->slave_addr); ch, adapter->name, dvo->slave_addr);
goto out; goto out;
} }
sil->quiet = false; sil->quiet = false;
DRM_DEBUG("init sil164 dvo controller successfully!\n"); DRM_DEBUG_KMS("init sil164 dvo controller successfully!\n");
return true; return true;
out: out:
...@@ -241,15 +241,15 @@ static void sil164_dump_regs(struct intel_dvo_device *dvo) ...@@ -241,15 +241,15 @@ static void sil164_dump_regs(struct intel_dvo_device *dvo)
uint8_t val; uint8_t val;
sil164_readb(dvo, SIL164_FREQ_LO, &val); sil164_readb(dvo, SIL164_FREQ_LO, &val);
DRM_DEBUG("SIL164_FREQ_LO: 0x%02x\n", val); DRM_LOG_KMS("SIL164_FREQ_LO: 0x%02x\n", val);
sil164_readb(dvo, SIL164_FREQ_HI, &val); sil164_readb(dvo, SIL164_FREQ_HI, &val);
DRM_DEBUG("SIL164_FREQ_HI: 0x%02x\n", val); DRM_LOG_KMS("SIL164_FREQ_HI: 0x%02x\n", val);
sil164_readb(dvo, SIL164_REG8, &val); sil164_readb(dvo, SIL164_REG8, &val);
DRM_DEBUG("SIL164_REG8: 0x%02x\n", val); DRM_LOG_KMS("SIL164_REG8: 0x%02x\n", val);
sil164_readb(dvo, SIL164_REG9, &val); sil164_readb(dvo, SIL164_REG9, &val);
DRM_DEBUG("SIL164_REG9: 0x%02x\n", val); DRM_LOG_KMS("SIL164_REG9: 0x%02x\n", val);
sil164_readb(dvo, SIL164_REGC, &val); sil164_readb(dvo, SIL164_REGC, &val);
DRM_DEBUG("SIL164_REGC: 0x%02x\n", val); DRM_LOG_KMS("SIL164_REGC: 0x%02x\n", val);
} }
static void sil164_save(struct intel_dvo_device *dvo) static void sil164_save(struct intel_dvo_device *dvo)
......
drivers/gpu/drm/i915/dvo_tfp410.c
View file @ d0c3b04a
...@@ -130,7 +130,7 @@ static bool tfp410_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch) ...@@ -130,7 +130,7 @@ static bool tfp410_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
}; };
if (!tfp->quiet) { if (!tfp->quiet) {
DRM_DEBUG("Unable to read register 0x%02x from %s:%02x.\n", DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
addr, i2cbus->adapter.name, dvo->slave_addr); addr, i2cbus->adapter.name, dvo->slave_addr);
} }
return false; return false;
...@@ -156,7 +156,7 @@ static bool tfp410_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch) ...@@ -156,7 +156,7 @@ static bool tfp410_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
return true; return true;
if (!tfp->quiet) { if (!tfp->quiet) {
DRM_DEBUG("Unable to write register 0x%02x to %s:%d.\n", DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
addr, i2cbus->adapter.name, dvo->slave_addr); addr, i2cbus->adapter.name, dvo->slave_addr);
} }
...@@ -191,13 +191,15 @@ static bool tfp410_init(struct intel_dvo_device *dvo, ...@@ -191,13 +191,15 @@ static bool tfp410_init(struct intel_dvo_device *dvo,
tfp->quiet = true; tfp->quiet = true;
if ((id = tfp410_getid(dvo, TFP410_VID_LO)) != TFP410_VID) { if ((id = tfp410_getid(dvo, TFP410_VID_LO)) != TFP410_VID) {
DRM_DEBUG("tfp410 not detected got VID %X: from %s Slave %d.\n", DRM_DEBUG_KMS("tfp410 not detected got VID %X: from %s "
"Slave %d.\n",
id, adapter->name, dvo->slave_addr); id, adapter->name, dvo->slave_addr);
goto out; goto out;
} }
if ((id = tfp410_getid(dvo, TFP410_DID_LO)) != TFP410_DID) { if ((id = tfp410_getid(dvo, TFP410_DID_LO)) != TFP410_DID) {
DRM_DEBUG("tfp410 not detected got DID %X: from %s Slave %d.\n", DRM_DEBUG_KMS("tfp410 not detected got DID %X: from %s "
"Slave %d.\n",
id, adapter->name, dvo->slave_addr); id, adapter->name, dvo->slave_addr);
goto out; goto out;
} }
...@@ -262,33 +264,33 @@ static void tfp410_dump_regs(struct intel_dvo_device *dvo) ...@@ -262,33 +264,33 @@ static void tfp410_dump_regs(struct intel_dvo_device *dvo)
uint8_t val, val2; uint8_t val, val2;
tfp410_readb(dvo, TFP410_REV, &val); tfp410_readb(dvo, TFP410_REV, &val);
DRM_DEBUG("TFP410_REV: 0x%02X\n", val); DRM_LOG_KMS("TFP410_REV: 0x%02X\n", val);
tfp410_readb(dvo, TFP410_CTL_1, &val); tfp410_readb(dvo, TFP410_CTL_1, &val);
DRM_DEBUG("TFP410_CTL1: 0x%02X\n", val); DRM_LOG_KMS("TFP410_CTL1: 0x%02X\n", val);
tfp410_readb(dvo, TFP410_CTL_2, &val); tfp410_readb(dvo, TFP410_CTL_2, &val);
DRM_DEBUG("TFP410_CTL2: 0x%02X\n", val); DRM_LOG_KMS("TFP410_CTL2: 0x%02X\n", val);
tfp410_readb(dvo, TFP410_CTL_3, &val); tfp410_readb(dvo, TFP410_CTL_3, &val);
DRM_DEBUG("TFP410_CTL3: 0x%02X\n", val); DRM_LOG_KMS("TFP410_CTL3: 0x%02X\n", val);
tfp410_readb(dvo, TFP410_USERCFG, &val); tfp410_readb(dvo, TFP410_USERCFG, &val);
DRM_DEBUG("TFP410_USERCFG: 0x%02X\n", val); DRM_LOG_KMS("TFP410_USERCFG: 0x%02X\n", val);
tfp410_readb(dvo, TFP410_DE_DLY, &val); tfp410_readb(dvo, TFP410_DE_DLY, &val);
DRM_DEBUG("TFP410_DE_DLY: 0x%02X\n", val); DRM_LOG_KMS("TFP410_DE_DLY: 0x%02X\n", val);
tfp410_readb(dvo, TFP410_DE_CTL, &val); tfp410_readb(dvo, TFP410_DE_CTL, &val);
DRM_DEBUG("TFP410_DE_CTL: 0x%02X\n", val); DRM_LOG_KMS("TFP410_DE_CTL: 0x%02X\n", val);
tfp410_readb(dvo, TFP410_DE_TOP, &val); tfp410_readb(dvo, TFP410_DE_TOP, &val);
DRM_DEBUG("TFP410_DE_TOP: 0x%02X\n", val); DRM_LOG_KMS("TFP410_DE_TOP: 0x%02X\n", val);
tfp410_readb(dvo, TFP410_DE_CNT_LO, &val); tfp410_readb(dvo, TFP410_DE_CNT_LO, &val);
tfp410_readb(dvo, TFP410_DE_CNT_HI, &val2); tfp410_readb(dvo, TFP410_DE_CNT_HI, &val2);
DRM_DEBUG("TFP410_DE_CNT: 0x%02X%02X\n", val2, val); DRM_LOG_KMS("TFP410_DE_CNT: 0x%02X%02X\n", val2, val);
tfp410_readb(dvo, TFP410_DE_LIN_LO, &val); tfp410_readb(dvo, TFP410_DE_LIN_LO, &val);
tfp410_readb(dvo, TFP410_DE_LIN_HI, &val2); tfp410_readb(dvo, TFP410_DE_LIN_HI, &val2);
DRM_DEBUG("TFP410_DE_LIN: 0x%02X%02X\n", val2, val); DRM_LOG_KMS("TFP410_DE_LIN: 0x%02X%02X\n", val2, val);
tfp410_readb(dvo, TFP410_H_RES_LO, &val); tfp410_readb(dvo, TFP410_H_RES_LO, &val);
tfp410_readb(dvo, TFP410_H_RES_HI, &val2); tfp410_readb(dvo, TFP410_H_RES_HI, &val2);
DRM_DEBUG("TFP410_H_RES: 0x%02X%02X\n", val2, val); DRM_LOG_KMS("TFP410_H_RES: 0x%02X%02X\n", val2, val);
tfp410_readb(dvo, TFP410_V_RES_LO, &val); tfp410_readb(dvo, TFP410_V_RES_LO, &val);
tfp410_readb(dvo, TFP410_V_RES_HI, &val2); tfp410_readb(dvo, TFP410_V_RES_HI, &val2);
DRM_DEBUG("TFP410_V_RES: 0x%02X%02X\n", val2, val); DRM_LOG_KMS("TFP410_V_RES: 0x%02X%02X\n", val2, val);
} }
static void tfp410_save(struct intel_dvo_device *dvo) static void tfp410_save(struct intel_dvo_device *dvo)
......
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