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Commit d14d5dc1 authored by Martin Dalecki's avatar Martin Dalecki Committed by Linus Torvalds
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[PATCH] 2.5.19 IDE 76 

 - Since Bartek has released finally an entierly user space based setup
   monitoring utility, we can finally remove the nonfunctional PROC code from
   the host chip drivers. We have preserved it thus far only for documentation
   purposes.

 - Use generic bus master DMA setup code. There is nothing wrong with it.

 - Make the ide-scsi code actually just allow for one device id per scsi host,
   since we are registering a host per device right now.  This prevents the
   repetitive device recognition. Well registering an SCSI host of every single
   disk out there isn't the proper thing to do. I will deal with that later
   after my visual perception recovers again from already looking too long at
   the SCSI code :-).

 - Deal properly with host specific data mapping. (Could be that solves some
   problems with the driver, which where in reality kernel data corruptions.)

 - Homogenize flag handling for ATAPI drivers.
parent 4a64d56a
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Showing with 122 additions and 1433 deletions
drivers/ide/alim15x3.c
View file @ d14d5dc1
......@@ -29,215 +29,9 @@
#include "ata-timing.h"
#include "pcihost.h"
#undef DISPLAY_ALI_TIMINGS
#if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS)
#include <linux/stat.h>
#include <linux/proc_fs.h>
static int ali_get_info(char *buffer, char **addr, off_t offset, int count);
extern int (*ali_display_info)(char *, char **, off_t, int); /* ide-proc.c */
static struct pci_dev *bmide_dev;
char *fifo[4] = {
"FIFO Off",
"FIFO On ",
"DMA mode",
"PIO mode" };
char *udmaT[8] = {
"1.5T",
" 2T",
"2.5T",
" 3T",
"3.5T",
" 4T",
" 6T",
" 8T"
};
char *channel_status[8] = {
"OK ",
"busy ",
"DRQ ",
"DRQ busy ",
"error ",
"error busy ",
"error DRQ ",
"error DRQ busy"
};
static int ali_get_info (char *buffer, char **addr, off_t offset, int count)
{
byte reg53h, reg5xh, reg5yh, reg5xh1, reg5yh1;
unsigned int bibma;
byte c0, c1;
byte rev, tmp;
char *p = buffer;
char *q;
/* fetch rev. */
pci_read_config_byte(bmide_dev, 0x08, &rev);
if (rev >= 0xc1) /* M1543C or newer */
udmaT[7] = " ???";
else
fifo[3] = " ??? ";
/* first fetch bibma: */
pci_read_config_dword(bmide_dev, 0x20, &bibma);
bibma = (bibma & 0xfff0) ;
/*
* at that point bibma+0x2 et bibma+0xa are byte
* registers to investigate:
*/
c0 = inb((unsigned short)bibma + 0x02);
c1 = inb((unsigned short)bibma + 0x0a);
p += sprintf(p,
"\n Ali M15x3 Chipset.\n");
p += sprintf(p,
" ------------------\n");
pci_read_config_byte(bmide_dev, 0x78, &reg53h);
p += sprintf(p, "PCI Clock: %d.\n", reg53h);
pci_read_config_byte(bmide_dev, 0x53, &reg53h);
p += sprintf(p,
"CD_ROM FIFO:%s, CD_ROM DMA:%s\n",
(reg53h & 0x02) ? "Yes" : "No ",
(reg53h & 0x01) ? "Yes" : "No " );
pci_read_config_byte(bmide_dev, 0x74, &reg53h);
p += sprintf(p,
"FIFO Status: contains %d Words, runs%s%s\n\n",
(reg53h & 0x3f),
(reg53h & 0x40) ? " OVERWR" : "",
(reg53h & 0x80) ? " OVERRD." : "." );
p += sprintf(p,
"-------------------primary channel-------------------secondary channel---------\n\n");
pci_read_config_byte(bmide_dev, 0x09, &reg53h);
p += sprintf(p,
"channel status: %s %s\n",
(reg53h & 0x20) ? "On " : "Off",
(reg53h & 0x10) ? "On " : "Off" );
p += sprintf(p,
"both channels togth: %s %s\n",
(c0&0x80) ? "No " : "Yes",
(c1&0x80) ? "No " : "Yes" );
pci_read_config_byte(bmide_dev, 0x76, &reg53h);
p += sprintf(p,
"Channel state: %s %s\n",
channel_status[reg53h & 0x07],
channel_status[(reg53h & 0x70) >> 4] );
pci_read_config_byte(bmide_dev, 0x58, &reg5xh);
pci_read_config_byte(bmide_dev, 0x5c, &reg5yh);
p += sprintf(p,
"Add. Setup Timing: %dT %dT\n",
(reg5xh & 0x07) ? (reg5xh & 0x07) : 8,
(reg5yh & 0x07) ? (reg5yh & 0x07) : 8 );
pci_read_config_byte(bmide_dev, 0x59, &reg5xh);
pci_read_config_byte(bmide_dev, 0x5d, &reg5yh);
p += sprintf(p,
"Command Act. Count: %dT %dT\n"
"Command Rec. Count: %dT %dT\n\n",
(reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8,
(reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8,
(reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16,
(reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16 );
p += sprintf(p,
"----------------drive0-----------drive1------------drive0-----------drive1------\n\n");
p += sprintf(p,
"DMA enabled: %s %s %s %s\n",
(c0&0x20) ? "Yes" : "No ",
(c0&0x40) ? "Yes" : "No ",
(c1&0x20) ? "Yes" : "No ",
(c1&0x40) ? "Yes" : "No " );
pci_read_config_byte(bmide_dev, 0x54, &reg5xh);
pci_read_config_byte(bmide_dev, 0x55, &reg5yh);
q = "FIFO threshold: %2d Words %2d Words %2d Words %2d Words\n";
if (rev < 0xc1) {
if ((rev == 0x20) && (pci_read_config_byte(bmide_dev, 0x4f, &tmp), (tmp &= 0x20))) {
p += sprintf(p, q, 8, 8, 8, 8);
} else {
p += sprintf(p, q,
(reg5xh & 0x03) + 12,
((reg5xh & 0x30)>>4) + 12,
(reg5yh & 0x03) + 12,
((reg5yh & 0x30)>>4) + 12 );
}
} else {
int t1 = (tmp = (reg5xh & 0x03)) ? (tmp << 3) : 4;
int t2 = (tmp = ((reg5xh & 0x30)>>4)) ? (tmp << 3) : 4;
int t3 = (tmp = (reg5yh & 0x03)) ? (tmp << 3) : 4;
int t4 = (tmp = ((reg5yh & 0x30)>>4)) ? (tmp << 3) : 4;
p += sprintf(p, q, t1, t2, t3, t4);
}
#if 0
p += sprintf(p,
"FIFO threshold: %2d Words %2d Words %2d Words %2d Words\n",
(reg5xh & 0x03) + 12,
((reg5xh & 0x30)>>4) + 12,
(reg5yh & 0x03) + 12,
((reg5yh & 0x30)>>4) + 12 );
#endif
p += sprintf(p,
"FIFO mode: %s %s %s %s\n",
fifo[((reg5xh & 0x0c) >> 2)],
fifo[((reg5xh & 0xc0) >> 6)],
fifo[((reg5yh & 0x0c) >> 2)],
fifo[((reg5yh & 0xc0) >> 6)] );
pci_read_config_byte(bmide_dev, 0x5a, &reg5xh);
pci_read_config_byte(bmide_dev, 0x5b, &reg5xh1);
pci_read_config_byte(bmide_dev, 0x5e, &reg5yh);
pci_read_config_byte(bmide_dev, 0x5f, &reg5yh1);
p += sprintf(p,/*
"------------------drive0-----------drive1------------drive0-----------drive1------\n")*/
"Dt RW act. Cnt %2dT %2dT %2dT %2dT\n"
"Dt RW rec. Cnt %2dT %2dT %2dT %2dT\n\n",
(reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8,
(reg5xh1 & 0x70) ? ((reg5xh1 & 0x70) >> 4) : 8,
(reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8,
(reg5yh1 & 0x70) ? ((reg5yh1 & 0x70) >> 4) : 8,
(reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16,
(reg5xh1 & 0x0f) ? (reg5xh1 & 0x0f) : 16,
(reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16,
(reg5yh1 & 0x0f) ? (reg5yh1 & 0x0f) : 16 );
p += sprintf(p,
"-----------------------------------UDMA Timings--------------------------------\n\n");
pci_read_config_byte(bmide_dev, 0x56, &reg5xh);
pci_read_config_byte(bmide_dev, 0x57, &reg5yh);
p += sprintf(p,
"UDMA: %s %s %s %s\n"
"UDMA timings: %s %s %s %s\n\n",
(reg5xh & 0x08) ? "OK" : "No",
(reg5xh & 0x80) ? "OK" : "No",
(reg5yh & 0x08) ? "OK" : "No",
(reg5yh & 0x80) ? "OK" : "No",
udmaT[(reg5xh & 0x07)],
udmaT[(reg5xh & 0x70) >> 4],
udmaT[reg5yh & 0x07],
udmaT[(reg5yh & 0x70) >> 4] );
return p-buffer; /* => must be less than 4k! */
}
#endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS) */
static byte m5229_revision;
static byte chip_is_1543c_e;
byte ali_proc = 0;
static struct pci_dev *isa_dev;
static void ali15x3_tune_drive(struct ata_device *drive, byte pio)
......@@ -503,14 +297,6 @@ static unsigned int __init ali15x3_init_chipset(struct pci_dev *dev)
printk("%s: simplex device: DMA will fail!!\n", dev->name);
}
#if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS)
if (!ali_proc) {
ali_proc = 1;
bmide_dev = dev;
ali_display_info = &ali_get_info;
}
#endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS) */
return 0;
}
......
drivers/ide/amd74xx.c
View file @ d14d5dc1
......@@ -89,108 +89,10 @@ static unsigned char amd_enabled;
static unsigned int amd_80w;
static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3 };
#if 0
static unsigned char amd_udma2cyc[] = { 4, 6, 8, 10, 3, 2, 1, 1 };
static char *amd_dma[] = { "MWDMA16", "UDMA33", "UDMA66", "UDMA100" };
/*
* AMD /proc entry.
*/
#if 0 && defined(CONFIG_PROC_FS)
#include <linux/stat.h>
#include <linux/proc_fs.h>
byte amd74xx_proc;
int amd_base;
static struct pci_dev *bmide_dev;
extern int (*amd74xx_display_info)(char *, char **, off_t, int); /* ide-proc.c */
#define amd_print(format, arg...) p += sprintf(p, format "\n" , ## arg)
#define amd_print_drive(name, format, arg...)\
p += sprintf(p, name); for (i = 0; i < 4; i++) p += sprintf(p, format, ## arg); p += sprintf(p, "\n");
static int amd_get_info(char *buffer, char **addr, off_t offset, int count)
{
int speed[4], cycle[4], setup[4], active[4], recover[4], den[4],
uen[4], udma[4], active8b[4], recover8b[4];
struct pci_dev *dev = bmide_dev;
unsigned int v, u, i;
unsigned short c, w;
unsigned char t;
char *p = buffer;
amd_print("----------AMD BusMastering IDE Configuration----------------");
amd_print("Driver Version: 2.8");
amd_print("South Bridge: %s", bmide_dev->name);
pci_read_config_byte(dev, PCI_REVISION_ID, &t);
amd_print("Revision: IDE %#x", t);
amd_print("Highest DMA rate: %s", amd_dma[amd_config->flags & AMD_UDMA]);
amd_print("BM-DMA base: %#x", amd_base);
amd_print("PCI clock: %d.%dMHz", system_bus_speed / 1000, system_bus_speed / 100 % 10);
amd_print("-----------------------Primary IDE-------Secondary IDE------");
pci_read_config_byte(dev, AMD_IDE_CONFIG, &t);
amd_print("Prefetch Buffer: %10s%20s", (t & 0x80) ? "yes" : "no", (t & 0x20) ? "yes" : "no");
amd_print("Post Write Buffer: %10s%20s", (t & 0x40) ? "yes" : "no", (t & 0x10) ? "yes" : "no");
pci_read_config_byte(dev, AMD_IDE_ENABLE, &t);
amd_print("Enabled: %10s%20s", (t & 0x02) ? "yes" : "no", (t & 0x01) ? "yes" : "no");
c = inb(amd_base + 0x02) | (inb(amd_base + 0x0a) << 8);
amd_print("Simplex only: %10s%20s", (c & 0x80) ? "yes" : "no", (c & 0x8000) ? "yes" : "no");
amd_print("Cable Type: %10s%20s", (amd_80w & 1) ? "80w" : "40w", (amd_80w & 2) ? "80w" : "40w");
if (!system_bus_speed)
return p - buffer;
amd_print("-------------------drive0----drive1----drive2----drive3-----");
pci_read_config_byte(dev, AMD_ADDRESS_SETUP, &t);
pci_read_config_dword(dev, AMD_DRIVE_TIMING, &v);
pci_read_config_word(dev, AMD_8BIT_TIMING, &w);
pci_read_config_dword(dev, AMD_UDMA_TIMING, &u);
for (i = 0; i < 4; i++) {
setup[i] = ((t >> ((3 - i) << 1)) & 0x3) + 1;
recover8b[i] = ((w >> ((1 - (i >> 1)) << 3)) & 0xf) + 1;
active8b[i] = ((w >> (((1 - (i >> 1)) << 3) + 4)) & 0xf) + 1;
active[i] = ((v >> (((3 - i) << 3) + 4)) & 0xf) + 1;
recover[i] = ((v >> ((3 - i) << 3)) & 0xf) + 1;
udma[i] = amd_udma2cyc[((u >> ((3 - i) << 3)) & 0x7)];
uen[i] = ((u >> ((3 - i) << 3)) & 0x40) ? 1 : 0;
den[i] = (c & ((i & 1) ? 0x40 : 0x20) << ((i & 2) << 2));
if (den[i] && uen[i] && udma[i] == 1) {
speed[i] = system_bus_speed * 3;
cycle[i] = 666666 / system_bus_speed;
continue;
}
speed[i] = 4 * system_bus_speed / ((den[i] && uen[i]) ? udma[i] : (active[i] + recover[i]) * 2);
cycle[i] = 1000000 * ((den[i] && uen[i]) ? udma[i] : (active[i] + recover[i]) * 2) / system_bus_speed / 2;
}
amd_print_drive("Transfer Mode: ", "%10s", den[i] ? (uen[i] ? "UDMA" : "DMA") : "PIO");
amd_print_drive("Address Setup: ", "%8dns", 1000000 * setup[i] / system_bus_speed);
amd_print_drive("Cmd Active: ", "%8dns", 1000000 * active8b[i] / system_bus_speed);
amd_print_drive("Cmd Recovery: ", "%8dns", 1000000 * recover8b[i] / system_bus_speed);
amd_print_drive("Data Active: ", "%8dns", 1000000 * active[i] / system_bus_speed);
amd_print_drive("Data Recovery: ", "%8dns", 1000000 * recover[i] / system_bus_speed);
amd_print_drive("Cycle Time: ", "%8dns", cycle[i]);
amd_print_drive("Transfer Rate: ", "%4d.%dMB/s", speed[i] / 1000, speed[i] / 100 % 10);
return p - buffer; /* hoping it is less than 4K... */
}
#endif
static char *amd_dma[] = { "MWDMA16", "UDMA33", "UDMA66", "UDMA100" };
/*
* amd_set_speed() writes timing values to the chipset registers
......@@ -362,19 +264,6 @@ static unsigned int __init amd74xx_init_chipset(struct pci_dev *dev)
printk(KERN_INFO "AMD_IDE: %s (rev %02x) %s controller on pci%s\n",
dev->name, t, amd_dma[amd_config->flags & AMD_UDMA], dev->slot_name);
/*
* Register /proc/ide/amd74xx entry
*/
#if 0 && defined(CONFIG_PROC_FS)
if (!amd74xx_proc) {
amd_base = pci_resource_start(dev, 4);
bmide_dev = dev;
amd74xx_display_info = &amd_get_info;
amd74xx_proc = 1;
}
#endif
return 0;
}
......
drivers/ide/cmd64x.c
View file @ d14d5dc1
......@@ -82,123 +82,6 @@
#define UDIDETCR1 0x7B
#define DTPR1 0x7C
#undef DISPLAY_CMD64X_TIMINGS
#if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS)
#include <linux/stat.h>
#include <linux/proc_fs.h>
static int cmd64x_get_info(char *, char **, off_t, int);
static int cmd680_get_info(char *, char **, off_t, int);
extern int (*cmd64x_display_info)(char *, char **, off_t, int); /* ide-proc.c */
static struct pci_dev *bmide_dev;
static int cmd64x_get_info (char *buffer, char **addr, off_t offset, int count)
{
char *p = buffer;
u8 reg53 = 0, reg54 = 0, reg55 = 0, reg56 = 0; /* primary */
u8 reg57 = 0, reg58 = 0, reg5b; /* secondary */
u8 reg72 = 0, reg73 = 0; /* primary */
u8 reg7a = 0, reg7b = 0; /* secondary */
u8 reg50 = 0, reg71 = 0; /* extra */
u8 hi_byte = 0, lo_byte = 0;
switch(bmide_dev->device) {
case PCI_DEVICE_ID_CMD_649:
p += sprintf(p, "\n CMD649 Chipset.\n");
break;
case PCI_DEVICE_ID_CMD_648:
p += sprintf(p, "\n CMD648 Chipset.\n");
break;
case PCI_DEVICE_ID_CMD_646:
p += sprintf(p, "\n CMD646 Chipset.\n");
break;
case PCI_DEVICE_ID_CMD_643:
p += sprintf(p, "\n CMD643 Chipset.\n");
break;
default:
p += sprintf(p, "\n CMD64? Chipse.\n");
break;
}
(void) pci_read_config_byte(bmide_dev, CFR, &reg50);
(void) pci_read_config_byte(bmide_dev, ARTTIM0, &reg53);
(void) pci_read_config_byte(bmide_dev, DRWTIM0, &reg54);
(void) pci_read_config_byte(bmide_dev, ARTTIM1, &reg55);
(void) pci_read_config_byte(bmide_dev, DRWTIM1, &reg56);
(void) pci_read_config_byte(bmide_dev, ARTTIM2, &reg57);
(void) pci_read_config_byte(bmide_dev, DRWTIM2, &reg58);
(void) pci_read_config_byte(bmide_dev, DRWTIM3, &reg5b);
(void) pci_read_config_byte(bmide_dev, MRDMODE, &reg71);
(void) pci_read_config_byte(bmide_dev, BMIDESR0, &reg72);
(void) pci_read_config_byte(bmide_dev, UDIDETCR0, &reg73);
(void) pci_read_config_byte(bmide_dev, BMIDESR1, &reg7a);
(void) pci_read_config_byte(bmide_dev, UDIDETCR1, &reg7b);
p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
p += sprintf(p, " %sabled %sabled\n",
(reg72&0x80)?"dis":" en",(reg7a&0x80)?"dis":" en");
p += sprintf(p, "--------------- drive0 --------- drive1 -------- drive0 ---------- drive1 ------\n");
p += sprintf(p, "DMA enabled: %s %s %s %s\n",
(reg72&0x20)?"yes":"no ",(reg72&0x40)?"yes":"no ",(reg7a&0x20)?"yes":"no ",(reg7a&0x40)?"yes":"no ");
p += sprintf(p, "DMA Mode: %s(%s) %s(%s) %s(%s) %s(%s)\n",
(reg72&0x20)?((reg73&0x01)?"UDMA":" DMA"):" PIO",
(reg72&0x20)?( ((reg73&0x30)==0x30)?(((reg73&0x35)==0x35)?"3":"0"):
((reg73&0x20)==0x20)?(((reg73&0x25)==0x25)?"3":"1"):
((reg73&0x10)==0x10)?(((reg73&0x15)==0x15)?"4":"2"):
((reg73&0x00)==0x00)?(((reg73&0x05)==0x05)?"5":"2"):"X"):"?",
(reg72&0x40)?((reg73&0x02)?"UDMA":" DMA"):" PIO",
(reg72&0x40)?( ((reg73&0xC0)==0xC0)?(((reg73&0xC5)==0xC5)?"3":"0"):
((reg73&0x80)==0x80)?(((reg73&0x85)==0x85)?"3":"1"):
((reg73&0x40)==0x40)?(((reg73&0x4A)==0x4A)?"4":"2"):
((reg73&0x00)==0x00)?(((reg73&0x0A)==0x0A)?"5":"2"):"X"):"?",
(reg7a&0x20)?((reg7b&0x01)?"UDMA":" DMA"):" PIO",
(reg7a&0x20)?( ((reg7b&0x30)==0x30)?(((reg7b&0x35)==0x35)?"3":"0"):
((reg7b&0x20)==0x20)?(((reg7b&0x25)==0x25)?"3":"1"):
((reg7b&0x10)==0x10)?(((reg7b&0x15)==0x15)?"4":"2"):
((reg7b&0x00)==0x00)?(((reg7b&0x05)==0x05)?"5":"2"):"X"):"?",
(reg7a&0x40)?((reg7b&0x02)?"UDMA":" DMA"):" PIO",
(reg7a&0x40)?( ((reg7b&0xC0)==0xC0)?(((reg7b&0xC5)==0xC5)?"3":"0"):
((reg7b&0x80)==0x80)?(((reg7b&0x85)==0x85)?"3":"1"):
((reg7b&0x40)==0x40)?(((reg7b&0x4A)==0x4A)?"4":"2"):
((reg7b&0x00)==0x00)?(((reg7b&0x0A)==0x0A)?"5":"2"):"X"):"?" );
p += sprintf(p, "PIO Mode: %s %s %s %s\n",
"?", "?", "?", "?");
p += sprintf(p, " %s %s\n",
(reg50 & CFR_INTR_CH0) ? "interrupting" : "polling ",
(reg57 & ARTTIM23_INTR_CH1) ? "interrupting" : "polling");
p += sprintf(p, " %s %s\n",
(reg71 & MRDMODE_INTR_CH0) ? "pending" : "clear ",
(reg71 & MRDMODE_INTR_CH1) ? "pending" : "clear");
p += sprintf(p, " %s %s\n",
(reg71 & MRDMODE_BLK_CH0) ? "blocked" : "enabled",
(reg71 & MRDMODE_BLK_CH1) ? "blocked" : "enabled");
SPLIT_BYTE(reg50, hi_byte, lo_byte);
p += sprintf(p, "CFR = 0x%02x, HI = 0x%02x, LOW = 0x%02x\n", reg50, hi_byte, lo_byte);
SPLIT_BYTE(reg57, hi_byte, lo_byte);
p += sprintf(p, "ARTTIM23 = 0x%02x, HI = 0x%02x, LOW = 0x%02x\n", reg57, hi_byte, lo_byte);
SPLIT_BYTE(reg71, hi_byte, lo_byte);
p += sprintf(p, "MRDMODE = 0x%02x, HI = 0x%02x, LOW = 0x%02x\n", reg71, hi_byte, lo_byte);
return p-buffer; /* => must be less than 4k! */
}
static int cmd680_get_info (char *buffer, char **addr, off_t offset, int count)
{
char *p = buffer;
p += sprintf(p, "\n CMD680 Chipset.\n");
p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
p += sprintf(p, "--------------- drive0 --------- drive1 -------- drive0 ---------- drive1 ------\n");
p += sprintf(p, "PIO Mode: %s %s %s %s\n",
"?", "?", "?", "?");
return p-buffer; /* => must be less than 4k! */
}
#endif /* defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS) */
byte cmd64x_proc = 0;
byte cmd680_proc = 0;
/*
* Registers and masks for easy access by drive index:
*/
......@@ -887,13 +770,6 @@ static unsigned int cmd680_pci_init(struct pci_dev *dev)
pci_write_config_dword(dev, 0xB8, 0x4392);
pci_write_config_dword(dev, 0xBC, 0x4009);
#if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS)
if (!cmd64x_proc) {
cmd64x_proc = 1;
bmide_dev = dev;
cmd64x_display_info = &cmd680_get_info;
}
#endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_PROC_FS */
return 0;
}
......@@ -975,14 +851,6 @@ static unsigned int cmd64x_pci_init(struct pci_dev *dev)
(void) pci_write_config_byte(dev, UDIDETCR0, 0xf0);
#endif /* CONFIG_PPC */
#if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS)
if (!cmd64x_proc) {
cmd64x_proc = 1;
bmide_dev = dev;
cmd64x_display_info = &cmd64x_get_info;
}
#endif
return 0;
}
......
drivers/ide/cs5530.c
View file @ d14d5dc1
......@@ -32,50 +32,6 @@
#include "ata-timing.h"
#include "pcihost.h"
#undef DISPLAY_CS5530_TIMINGS
#if defined(DISPLAY_CS5530_TIMINGS) && defined(CONFIG_PROC_FS)
#include <linux/stat.h>
#include <linux/proc_fs.h>
static int cs5530_get_info(char *, char **, off_t, int);
extern int (*cs5530_display_info)(char *, char **, off_t, int); /* ide-proc.c */
static struct pci_dev *bmide_dev;
static int cs5530_get_info (char *buffer, char **addr, off_t offset, int count)
{
char *p = buffer;
u32 bibma = pci_resource_start(bmide_dev, 4);
u8 c0 = 0, c1 = 0;
/*
* at that point bibma+0x2 et bibma+0xa are byte registers
* to investigate:
*/
c0 = inb_p((unsigned short)bibma + 0x02);
c1 = inb_p((unsigned short)bibma + 0x0a);
p += sprintf(p, "\n Cyrix 5530 Chipset.\n");
p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
p += sprintf(p, " %sabled %sabled\n",
(c0&0x80) ? "dis" : " en",
(c1&0x80) ? "dis" : " en");
p += sprintf(p, "--------------- drive0 --------- drive1 -------- drive0 ---------- drive1 ------\n");
p += sprintf(p, "DMA enabled: %s %s %s %s\n",
(c0&0x20) ? "yes" : "no ", (c0&0x40) ? "yes" : "no ",
(c1&0x20) ? "yes" : "no ", (c1&0x40) ? "yes" : "no " );
p += sprintf(p, "UDMA\n");
p += sprintf(p, "DMA\n");
p += sprintf(p, "PIO\n");
return p-buffer;
}
#endif /* DISPLAY_CS5530_TIMINGS && CONFIG_PROC_FS */
byte cs5530_proc = 0;
/*
* Set a new transfer mode at the drive
*/
......@@ -250,14 +206,6 @@ static unsigned int __init pci_init_cs5530(struct pci_dev *dev)
unsigned short pcicmd = 0;
unsigned long flags;
#if defined(DISPLAY_CS5530_TIMINGS) && defined(CONFIG_PROC_FS)
if (!cs5530_proc) {
cs5530_proc = 1;
bmide_dev = dev;
cs5530_display_info = &cs5530_get_info;
}
#endif /* DISPLAY_CS5530_TIMINGS && CONFIG_PROC_FS */
pci_for_each_dev (dev) {
if (dev->vendor == PCI_VENDOR_ID_CYRIX) {
switch (dev->device) {
......@@ -374,7 +322,7 @@ static struct ata_pci_device chipset __initdata = {
init_chipset: pci_init_cs5530,
init_channel: ide_init_cs5530,
bootable: ON_BOARD,
flags: ATA_F_DMA | ATA_F_FDMA
flags: ATA_F_DMA
};
int __init init_cs5530(void)
......
drivers/ide/hpt34x.c
View file @ d14d5dc1
......@@ -51,49 +51,6 @@
#define HPT343_DEBUG_DRIVE_INFO 0
#undef DISPLAY_HPT34X_TIMINGS
#if defined(DISPLAY_HPT34X_TIMINGS) && defined(CONFIG_PROC_FS)
#include <linux/stat.h>
#include <linux/proc_fs.h>
static int hpt34x_get_info(char *, char **, off_t, int);
extern int (*hpt34x_display_info)(char *, char **, off_t, int); /* ide-proc.c */
static struct pci_dev *bmide_dev;
static int hpt34x_get_info (char *buffer, char **addr, off_t offset, int count)
{
char *p = buffer;
u32 bibma = pci_resource_start(bmide_dev, 4);
u8 c0 = 0, c1 = 0;
/*
* at that point bibma+0x2 et bibma+0xa are byte registers
* to investigate:
*/
c0 = inb_p((unsigned short)bibma + 0x02);
c1 = inb_p((unsigned short)bibma + 0x0a);
p += sprintf(p, "\n HPT34X Chipset.\n");
p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
p += sprintf(p, " %sabled %sabled\n",
(c0&0x80) ? "dis" : " en",
(c1&0x80) ? "dis" : " en");
p += sprintf(p, "--------------- drive0 --------- drive1 -------- drive0 ---------- drive1 ------\n");
p += sprintf(p, "DMA enabled: %s %s %s %s\n",
(c0&0x20) ? "yes" : "no ", (c0&0x40) ? "yes" : "no ",
(c1&0x20) ? "yes" : "no ", (c1&0x40) ? "yes" : "no " );
p += sprintf(p, "UDMA\n");
p += sprintf(p, "DMA\n");
p += sprintf(p, "PIO\n");
return p-buffer; /* => must be less than 4k! */
}
#endif /* defined(DISPLAY_HPT34X_TIMINGS) && defined(CONFIG_PROC_FS) */
byte hpt34x_proc = 0;
static void hpt34x_clear_chipset(struct ata_device *drive)
{
unsigned int reg1 = 0, tmp1 = 0;
......@@ -380,14 +337,6 @@ static unsigned int __init pci_init_hpt34x(struct pci_dev *dev)
__restore_flags(flags); /* local CPU only */
#if defined(DISPLAY_HPT34X_TIMINGS) && defined(CONFIG_PROC_FS)
if (!hpt34x_proc) {
hpt34x_proc = 1;
bmide_dev = dev;
hpt34x_display_info = &hpt34x_get_info;
}
#endif
return dev->irq;
}
......
drivers/ide/hpt366.c
View file @ d14d5dc1
......@@ -68,18 +68,11 @@
#include "pcihost.h"
#undef DISPLAY_HPT366_TIMINGS
/* various tuning parameters */
#define HPT_RESET_STATE_ENGINE
/*#define HPT_DELAY_INTERRUPT*/
/*#define HPT_SERIALIZE_IO*/
#if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
#include <linux/stat.h>
#include <linux/proc_fs.h>
#endif /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */
static const char *quirk_drives[] = {
"QUANTUM FIREBALLlct08 08",
"QUANTUM FIREBALLP KA6.4",
......@@ -483,99 +476,8 @@ static struct chipset_bus_clock_list_entry sixty_six_base_hpt374[] = {
#define F_LOW_PCI_50 0x2d
#define F_LOW_PCI_66 0x42
static struct pci_dev *hpt_devs[HPT366_MAX_DEVS];
static int n_hpt_devs;
static unsigned int hpt_min_rev(struct pci_dev *dev, int rev);
#if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
static u8 hpt366_proc = 0;
static int hpt366_get_info(char *, char **, off_t, int);
extern int (*hpt366_display_info)(char *, char **, off_t, int); /* ide-proc.c */
static int hpt366_get_info (char *buffer, char **addr, off_t offset, int count)
{
char *p = buffer;
char *chipset_nums[] = {"366", "366", "368",
"370", "370A", "372",
"??", "374" };
int i;
p += sprintf(p, "\n "
"HighPoint HPT366/368/370/372/374\n");
for (i = 0; i < n_hpt_devs; i++) {
struct pci_dev *dev = hpt_devs[i];
unsigned short iobase = dev->resource[4].start;
u32 class_rev;
u8 c0, c1;
pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
class_rev &= 0xff;
p += sprintf(p, "\nController: %d\n", i);
p += sprintf(p, "Chipset: HPT%s\n",
class_rev < sizeof(chipset_nums) / sizeof(char *) ? chipset_nums[class_rev] : "???");
p += sprintf(p, "--------------- Primary Channel "
"--------------- Secondary Channel "
"--------------\n");
/* get the bus master status registers */
c0 = inb_p(iobase + 0x2);
c1 = inb_p(iobase + 0xa);
p += sprintf(p, "Enabled: %s"
" %s\n",
(c0 & 0x80) ? "no" : "yes",
(c1 & 0x80) ? "no" : "yes");
if (hpt_min_rev(dev, 3)) {
u8 cbl;
cbl = inb_p(iobase + 0x7b);
outb_p(cbl | 1, iobase + 0x7b);
outb_p(cbl & ~1, iobase + 0x7b);
cbl = inb_p(iobase + 0x7a);
p += sprintf(p, "Cable: ATA-%d"
" ATA-%d\n",
(cbl & 0x02) ? 33 : 66,
(cbl & 0x01) ? 33 : 66);
p += sprintf(p, "\n");
}
p += sprintf(p, "--------------- drive0 --------- drive1 "
"------- drive0 ---------- drive1 -------\n");
p += sprintf(p, "DMA capable: %s %s"
" %s %s\n",
(c0 & 0x20) ? "yes" : "no ",
(c0 & 0x40) ? "yes" : "no ",
(c1 & 0x20) ? "yes" : "no ",
(c1 & 0x40) ? "yes" : "no ");
{
u8 c2, c3;
/* older revs don't have these registers mapped
* into io space */
pci_read_config_byte(dev, 0x43, &c0);
pci_read_config_byte(dev, 0x47, &c1);
pci_read_config_byte(dev, 0x4b, &c2);
pci_read_config_byte(dev, 0x4f, &c3);
p += sprintf(p, "Mode: %s %s"
" %s %s\n",
(c0 & 0x10) ? "UDMA" : (c0 & 0x20) ? "DMA " :
(c0 & 0x80) ? "PIO " : "off ",
(c1 & 0x10) ? "UDMA" : (c1 & 0x20) ? "DMA " :
(c1 & 0x80) ? "PIO " : "off ",
(c2 & 0x10) ? "UDMA" : (c2 & 0x20) ? "DMA " :
(c2 & 0x80) ? "PIO " : "off ",
(c3 & 0x10) ? "UDMA" : (c3 & 0x20) ? "DMA " :
(c3 & 0x80) ? "PIO " : "off ");
}
}
p += sprintf(p, "\n");
return p-buffer;/* => must be less than 4k! */
}
#endif /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */
static int check_in_drive_lists(struct ata_device *drive, const char **list)
{
struct hd_driveid *id = drive->id;
......@@ -1420,16 +1322,6 @@ static unsigned int __init hpt366_init_chipset(struct pci_dev *dev)
else
hpt366_init(dev);
if (n_hpt_devs < HPT366_MAX_DEVS)
hpt_devs[n_hpt_devs++] = dev;
#if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
if (!hpt366_proc) {
hpt366_proc = 1;
hpt366_display_info = &hpt366_get_info;
}
#endif
return dev->irq;
}
......
drivers/ide/ide-floppy.c
View file @ d14d5dc1
......@@ -133,17 +133,6 @@
*/
#define IDEFLOPPY_PC_STACK (10 + IDEFLOPPY_MAX_PC_RETRIES)
/*
* Packet command flag bits.
*/
#define PC_ABORT 0 /* Set when an error is considered normal - We won't retry */
#define PC_DMA_RECOMMENDED 2 /* 1 when we prefer to use DMA if possible */
#define PC_DMA_IN_PROGRESS 3 /* 1 while DMA in progress */
#define PC_DMA_ERROR 4 /* 1 when encountered problem during DMA */
#define PC_WRITING 5 /* Data direction */
#define PC_SUPPRESS_ERROR 6 /* Suppress error reporting */
/*
* Removable Block Access Capabilities Page
*/
......
drivers/ide/ide-pci.c
View file @ d14d5dc1
......@@ -168,8 +168,7 @@ static int __init setup_host_channel(struct pci_dev *dev,
int port,
u8 class_rev,
int pciirq,
int autodma,
unsigned short *pcicmd)
int autodma)
{
unsigned long base = 0;
unsigned long dma_base;
......@@ -319,23 +318,12 @@ static int __init setup_host_channel(struct pci_dev *dev,
goto no_dma;
}
if (!(*pcicmd & PCI_COMMAND_MASTER)) {
/*
* Set up BM-DMA capability (PnP BIOS should have done this
* already). Default to DMA off on the drive, if we had to
* configure it here. This should most propably be enabled no
* all chipsets which can be expected to be used on systems
* without a BIOS equivalent.
*/
if (!(d->flags | ATA_F_FDMA))
ch->autodma = 0;
pci_write_config_word(dev, PCI_COMMAND, *pcicmd | PCI_COMMAND_MASTER);
if (pci_read_config_word(dev, PCI_COMMAND, pcicmd) || !(*pcicmd & PCI_COMMAND_MASTER)) {
printk("%s: %s error updating PCICMD\n",
ch->name, dev->name);
dma_base = 0;
}
}
/* The function below will check itself whatever there is something to
* be done or not. We don't have therefore to care whatever it was
* already enabled by the primary channel run.
*/
pci_set_master(dev);
if (d->init_dma)
d->init_dma(ch, dma_base);
else
......@@ -472,8 +460,8 @@ static void __init setup_pci_device(struct pci_dev *dev, struct ata_pci_device *
/*
* Set up IDE chanells. First the primary, then the secondary.
*/
setup_host_channel(dev, d, ATA_PRIMARY, class_rev, pciirq, autodma, &pcicmd);
setup_host_channel(dev, d, ATA_SECONDARY, class_rev, pciirq, autodma, &pcicmd);
setup_host_channel(dev, d, ATA_PRIMARY, class_rev, pciirq, autodma);
setup_host_channel(dev, d, ATA_SECONDARY, class_rev, pciirq, autodma);
}
/*
......
drivers/ide/ide-tape.c
View file @ d14d5dc1
......@@ -701,16 +701,6 @@ typedef enum {
idetape_direction_write
} idetape_chrdev_direction_t;
/*
* Packet command flag bits.
*/
#define PC_ABORT 0 /* Set when an error is considered normal - We won't retry */
#define PC_WAIT_FOR_DSC 1 /* 1 When polling for DSC on a media access command */
#define PC_DMA_RECOMMENDED 2 /* 1 when we prefer to use DMA if possible */
#define PC_DMA_IN_PROGRESS 3 /* 1 while DMA in progress */
#define PC_DMA_ERROR 4 /* 1 when encountered problem during DMA */
#define PC_WRITING 5 /* Data direction */
/*
* Capabilities and Mechanical Status Page
*/
......
drivers/ide/pcihost.h
View file @ d14d5dc1
......@@ -105,13 +105,12 @@ typedef struct ide_pci_enablebit_s {
#define ATA_F_DMA 0x001
#define ATA_F_NODMA 0x002 /* no DMA mode supported at all */
#define ATA_F_NOADMA 0x004 /* DMA has to be enabled explicitely */
#define ATA_F_FDMA 0x008 /* force autodma */
#define ATA_F_FIXIRQ 0x010 /* fixed irq wiring */
#define ATA_F_SER 0x020 /* serialize on first and second channel interrupts */
#define ATA_F_IRQ 0x040 /* trust IRQ information from config */
#define ATA_F_PHACK 0x080 /* apply PROMISE hacks */
#define ATA_F_HPTHACK 0x100 /* apply HPT366 hacks */
#define ATA_F_SIMPLEX 0x200 /* force treatment as simple device */
#define ATA_F_FIXIRQ 0x008 /* fixed irq wiring */
#define ATA_F_SER 0x010 /* serialize on first and second channel interrupts */
#define ATA_F_IRQ 0x020 /* trust IRQ information from config */
#define ATA_F_PHACK 0x040 /* apply PROMISE hacks */
#define ATA_F_HPTHACK 0x080 /* apply HPT366 hacks */
#define ATA_F_SIMPLEX 0x100 /* force treatment as simple device */
struct ata_pci_device {
......
drivers/ide/piix.c
View file @ d14d5dc1
......@@ -108,129 +108,6 @@ static unsigned int piix_80w;
static char *piix_dma[] = { "MWDMA16", "UDMA33", "UDMA66", "UDMA100", "UDMA133" };
/*
* PIIX/ICH /proc entry.
*/
#if 0 && defined(CONFIG_PROC_FS)
#include <linux/stat.h>
#include <linux/proc_fs.h>
byte piix_proc;
int piix_base;
static struct pci_dev *bmide_dev;
extern int (*piix_display_info)(char *, char **, off_t, int); /* ide-proc.c */
#define piix_print(format, arg...) p += sprintf(p, format "\n" , ## arg)
#define piix_print_drive(name, format, arg...)\
p += sprintf(p, name); for (i = 0; i < 4; i++) p += sprintf(p, format, ## arg); p += sprintf(p, "\n");
static int piix_get_info(char *buffer, char **addr, off_t offset, int count)
{
int speed[4], cycle[4], active[4], recover[4], dmaen[4], uen[4], udma[4], umul;
struct pci_dev *dev = bmide_dev;
unsigned int i, u;
unsigned short c, d, e;
unsigned char t;
char *p = buffer;
piix_print("----------PIIX BusMastering IDE Configuration---------------");
piix_print("Driver Version: 1.3");
piix_print("South Bridge: %s", bmide_dev->name);
pci_read_config_byte(dev, PCI_REVISION_ID, &t);
piix_print("Revision: IDE %#x", t);
piix_print("Highest DMA rate: %s", piix_config->flags & PIIX_NODMA ? "No DMA"
: piix_dma[piix_config->flags & PIIX_UDMA]);
piix_print("BM-DMA base: %#x", piix_base);
piix_print("PCI clock: %d.%dMHz", system_bus_speed / 1000, system_bus_speed / 100 % 10);
piix_print("-----------------------Primary IDE-------Secondary IDE------");
pci_read_config_word(dev, PIIX_IDETIM0, &d);
pci_read_config_word(dev, PIIX_IDETIM1, &e);
piix_print("Enabled: %10s%20s", (d & 0x8000) ? "yes" : "no", (e & 0x8000) ? "yes" : "no");
c = inb(piix_base + 0x02) | (inb(piix_base + 0x0a) << 8);
piix_print("Simplex only: %10s%20s", (c & 0x80) ? "yes" : "no", (c & 0x8000) ? "yes" : "no");
piix_print("Cable Type: %10s%20s", (piix_80w & 1) ? "80w" : "40w", (piix_80w & 2) ? "80w" : "40w");
if (!system_bus_speed)
return p - buffer;
piix_print("-------------------drive0----drive1----drive2----drive3-----");
piix_print_drive("Prefetch+Post: ", "%10s", (((i & 2) ? d : e) & (1 << (2 + ((i & 1) << 2)))) ? "yes" : "no");
for (i = 0; i < 4; i++) {
pci_read_config_word(dev, PIIX_IDETIM0 + (i & 2), &d);
if (~piix_config->flags & PIIX_NO_SITRE)
pci_read_config_byte(dev, PIIX_SIDETIM, &t);
umul = 4;
udma[i] = uen[i] = 0;
active[i] = 12;
recover[i] = 18;
switch (i & 1) {
case 1: if (~d & 0x10) break;
if ((~piix_config->flags & PIIX_NO_SITRE) && (d & 0x4000)) {
active[i] = 5 - ((t >> (((i & 2) << 1) + 2)) & 3);
recover[i] = 4 - ((t >> (((i & 2) << 1) + 0)) & 3);
break;
}
case 0: if (~d & 0x01) break;
active[i] = 5 - ((d >> 12) & 3);
recover[i] = 4 - ((d >> 8) & 3);
}
dmaen[i] = (c & ((i & 1) ? 0x40 : 0x20) << ((i & 2) << 2));
cycle[i] = 1000000 / system_bus_speed * (active[i] + recover[i]);
speed[i] = 2 * system_bus_speed / (active[i] + recover[i]);
if (!(piix_config->flags & PIIX_UDMA))
continue;
pci_read_config_byte(dev, PIIX_UDMACTL, &t);
uen[i] = (t & (1 << i)) ? dmaen[i] : 0;
if (!uen[i])
continue;
pci_read_config_word(dev, PIIX_UDMATIM, &e);
pci_read_config_dword(dev, PIIX_IDECFG, &u);
if (~piix_config->flags & PIIX_VICTORY) {
if ((piix_config->flags & PIIX_UDMA) >= PIIX_UDMA_66 && (u & (1 << i))) umul = 2;
if ((piix_config->flags & PIIX_UDMA) >= PIIX_UDMA_100 && (u & (1 << (i + 12)))) umul = 1;
udma[i] = (4 - ((e >> (i << 2)) & 3)) * umul;
} else udma[i] = (8 - ((e >> (i << 2)) & 7)) * 2;
speed[i] = 8 * system_bus_speed / udma[i];
cycle[i] = 250000 * udma[i] / system_bus_speed;
}
piix_print_drive("Transfer Mode: ", "%10s", dmaen[i] ? (uen[i] ? "UDMA" : "DMA") : "PIO");
piix_print_drive("Address Setup: ", "%8dns", (1000000 / system_bus_speed) * 3);
piix_print_drive("Cmd Active: ", "%8dns", (1000000 / system_bus_speed) * 12);
piix_print_drive("Cmd Recovery: ", "%8dns", (1000000 / system_bus_speed) * 18);
piix_print_drive("Data Active: ", "%8dns", (1000000 / system_bus_speed) * active[i]);
piix_print_drive("Data Recovery: ", "%8dns", (1000000 / system_bus_speed) * recover[i]);
piix_print_drive("Cycle Time: ", "%8dns", cycle[i]);
piix_print_drive("Transfer Rate: ", "%4d.%dMB/s", speed[i] / 1000, speed[i] / 100 % 10);
return p - buffer; /* hoping it is less than 4K... */
}
#endif
/*
* piix_set_speed() writes timing values to the chipset registers
*/
......@@ -497,19 +374,6 @@ static unsigned int __init piix_init_chipset(struct pci_dev *dev)
printk(KERN_INFO "PIIX: %s %s controller on pci%s\n",
dev->name, piix_dma[piix_config->flags & PIIX_UDMA], dev->slot_name);
/*
* Register /proc/ide/piix entry
*/
#if 0 && defined(CONFIG_PROC_FS)
if (!piix_proc) {
piix_base = pci_resource_start(dev, 4);
bmide_dev = dev;
piix_display_info = &piix_get_info;
piix_proc = 1;
}
#endif
return 0;
}
......
drivers/ide/probe.c
View file @ d14d5dc1
......@@ -37,10 +37,8 @@
#include <asm/uaccess.h>
#include <asm/io.h>
extern struct ata_device * get_info_ptr(kdev_t);
/*
* This is called from the partition-table code in pt/msdos.c.
*
......@@ -532,7 +530,7 @@ static inline void do_identify(struct ata_device *drive, u8 cmd)
}
}
drive->type = ATA_DISK;
printk("ATA DISK drive\n");
printk("DISK drive\n");
/* Initialize our quirk list. */
if (drive->channel->quirkproc)
......@@ -614,7 +612,7 @@ static int identify(struct ata_device *drive, u8 cmd)
goto out;
} else
#endif
OUT_BYTE(cmd,IDE_COMMAND_REG); /* ask drive for ID */
OUT_BYTE(cmd, IDE_COMMAND_REG); /* ask drive for ID */
timeout = ((cmd == WIN_IDENTIFY) ? WAIT_WORSTCASE : WAIT_PIDENTIFY) / 2;
timeout += jiffies;
do {
......@@ -673,29 +671,31 @@ static int identify(struct ata_device *drive, u8 cmd)
static int do_probe(struct ata_device *drive, u8 cmd)
{
int rc;
struct ata_channel *hwif = drive->channel;
struct ata_channel *ch = drive->channel;
u8 select;
if (drive->present) { /* avoid waiting for inappropriate probes */
if ((drive->type != ATA_DISK) && (cmd == WIN_IDENTIFY))
return 4;
}
#ifdef DEBUG
printk("probing for %s: present=%d, type=%d, probetype=%s\n",
printk("probing for %s: present=%d, type=%02x, probetype=%s\n",
drive->name, drive->present, drive->type,
(cmd == WIN_IDENTIFY) ? "ATA" : "ATAPI");
#endif
mdelay(50); /* needed for some systems (e.g. crw9624 as drive0 with disk as slave) */
SELECT_DRIVE(hwif,drive);
SELECT_DRIVE(ch, drive);
mdelay(50);
if (IN_BYTE(IDE_SELECT_REG) != drive->select.all && !drive->present) {
select = IN_BYTE(IDE_SELECT_REG);
if (select != drive->select.all && !drive->present) {
if (drive->select.b.unit != 0) {
SELECT_DRIVE(hwif,&hwif->drives[0]); /* exit with drive0 selected */
SELECT_DRIVE(ch, &ch->drives[0]); /* exit with drive0 selected */
mdelay(50); /* allow BUSY_STAT to assert & clear */
}
return 3; /* no i/f present: mmm.. this should be a 4 -ml */
}
if (OK_STAT(GET_STAT(),READY_STAT,BUSY_STAT) || drive->present || cmd == WIN_PIDENTIFY)
if (OK_STAT(GET_STAT(), READY_STAT, BUSY_STAT) || drive->present || cmd == WIN_PIDENTIFY)
{
if ((rc = identify(drive,cmd))) /* send cmd and wait */
rc = identify(drive,cmd); /* failed: try again */
......@@ -713,12 +713,12 @@ static int do_probe(struct ata_device *drive, u8 cmd)
}
if (rc == 1)
printk("%s: no response (status = 0x%02x)\n", drive->name, GET_STAT());
(void) GET_STAT(); /* ensure drive irq is clear */
GET_STAT(); /* ensure drive irq is clear */
} else
rc = 3; /* not present or maybe ATAPI */
if (drive->select.b.unit != 0) {
SELECT_DRIVE(hwif,&hwif->drives[0]); /* exit with drive0 selected */
SELECT_DRIVE(ch, &ch->drives[0]); /* exit with drive0 selected */
mdelay(50);
GET_STAT(); /* ensure drive irq is clear */
}
......
drivers/ide/serverworks.c
View file @ d14d5dc1
......@@ -95,146 +95,10 @@
#include "ata-timing.h"
#include "pcihost.h"
#undef DISPLAY_SVWKS_TIMINGS
#undef SVWKS_DEBUG_DRIVE_INFO
static u8 svwks_revision;
#if defined(DISPLAY_SVWKS_TIMINGS) && defined(CONFIG_PROC_FS)
#include <linux/stat.h>
#include <linux/proc_fs.h>
static struct pci_dev *bmide_dev;
static int svwks_get_info(char *, char **, off_t, int);
extern int (*svwks_display_info)(char *, char **, off_t, int); /* ide-proc.c */
static int svwks_get_info (char *buffer, char **addr, off_t offset, int count)
{
char *p = buffer;
u32 bibma = pci_resource_start(bmide_dev, 4);
u32 reg40, reg44;
u16 reg48, reg56;
u8 reg54, c0=0, c1=0;
pci_read_config_dword(bmide_dev, 0x40, &reg40);
pci_read_config_dword(bmide_dev, 0x44, &reg44);
pci_read_config_word(bmide_dev, 0x48, &reg48);
pci_read_config_byte(bmide_dev, 0x54, &reg54);
pci_read_config_word(bmide_dev, 0x56, &reg56);
/*
* at that point bibma+0x2 et bibma+0xa are byte registers
* to investigate:
*/
c0 = inb_p((unsigned short)bibma + 0x02);
c1 = inb_p((unsigned short)bibma + 0x0a);
switch(bmide_dev->device) {
case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
p += sprintf(p, "\n "
"ServerWorks CSB5 Chipset (rev %02x)\n",
svwks_revision);
break;
case PCI_DEVICE_ID_SERVERWORKS_OSB4IDE:
p += sprintf(p, "\n "
"ServerWorks OSB4 Chipset (rev %02x)\n",
svwks_revision);
break;
default:
p += sprintf(p, "\n "
"ServerWorks %04x Chipset (rev %02x)\n",
bmide_dev->device, svwks_revision);
break;
}
p += sprintf(p, "------------------------------- General Status ---------------------------------\n");
p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
p += sprintf(p, " %sabled %sabled\n",
(c0&0x80) ? "dis" : " en",
(c1&0x80) ? "dis" : " en");
p += sprintf(p, "--------------- drive0 --------- drive1 -------- drive0 ---------- drive1 ------\n");
p += sprintf(p, "DMA enabled: %s %s %s %s\n",
(c0&0x20) ? "yes" : "no ",
(c0&0x40) ? "yes" : "no ",
(c1&0x20) ? "yes" : "no ",
(c1&0x40) ? "yes" : "no " );
p += sprintf(p, "UDMA enabled: %s %s %s %s\n",
(reg54 & 0x01) ? "yes" : "no ",
(reg54 & 0x02) ? "yes" : "no ",
(reg54 & 0x04) ? "yes" : "no ",
(reg54 & 0x08) ? "yes" : "no " );
p += sprintf(p, "UDMA enabled: %s %s %s %s\n",
((reg56&0x0005)==0x0005)?"5":
((reg56&0x0004)==0x0004)?"4":
((reg56&0x0003)==0x0003)?"3":
((reg56&0x0002)==0x0002)?"2":
((reg56&0x0001)==0x0001)?"1":
((reg56&0x000F))?"?":"0",
((reg56&0x0050)==0x0050)?"5":
((reg56&0x0040)==0x0040)?"4":
((reg56&0x0030)==0x0030)?"3":
((reg56&0x0020)==0x0020)?"2":
((reg56&0x0010)==0x0010)?"1":
((reg56&0x00F0))?"?":"0",
((reg56&0x0500)==0x0500)?"5":
((reg56&0x0400)==0x0400)?"4":
((reg56&0x0300)==0x0300)?"3":
((reg56&0x0200)==0x0200)?"2":
((reg56&0x0100)==0x0100)?"1":
((reg56&0x0F00))?"?":"0",
((reg56&0x5000)==0x5000)?"5":
((reg56&0x4000)==0x4000)?"4":
((reg56&0x3000)==0x3000)?"3":
((reg56&0x2000)==0x2000)?"2":
((reg56&0x1000)==0x1000)?"1":
((reg56&0xF000))?"?":"0");
p += sprintf(p, "DMA enabled: %s %s %s %s\n",
((reg44&0x00002000)==0x00002000)?"2":
((reg44&0x00002100)==0x00002100)?"1":
((reg44&0x00007700)==0x00007700)?"0":
((reg44&0x0000FF00)==0x0000FF00)?"X":"?",
((reg44&0x00000020)==0x00000020)?"2":
((reg44&0x00000021)==0x00000021)?"1":
((reg44&0x00000077)==0x00000077)?"0":
((reg44&0x000000FF)==0x000000FF)?"X":"?",
((reg44&0x20000000)==0x20000000)?"2":
((reg44&0x21000000)==0x21000000)?"1":
((reg44&0x77000000)==0x77000000)?"0":
((reg44&0xFF000000)==0xFF000000)?"X":"?",
((reg44&0x00200000)==0x00200000)?"2":
((reg44&0x00210000)==0x00210000)?"1":
((reg44&0x00770000)==0x00770000)?"0":
((reg44&0x00FF0000)==0x00FF0000)?"X":"?");
p += sprintf(p, "PIO enabled: %s %s %s %s\n",
((reg40&0x00002000)==0x00002000)?"4":
((reg40&0x00002200)==0x00002200)?"3":
((reg40&0x00003400)==0x00003400)?"2":
((reg40&0x00004700)==0x00004700)?"1":
((reg40&0x00005D00)==0x00005D00)?"0":"?",
((reg40&0x00000020)==0x00000020)?"4":
((reg40&0x00000022)==0x00000022)?"3":
((reg40&0x00000034)==0x00000034)?"2":
((reg40&0x00000047)==0x00000047)?"1":
((reg40&0x0000005D)==0x0000005D)?"0":"?",
((reg40&0x20000000)==0x20000000)?"4":
((reg40&0x22000000)==0x22000000)?"3":
((reg40&0x34000000)==0x34000000)?"2":
((reg40&0x47000000)==0x47000000)?"1":
((reg40&0x5D000000)==0x5D000000)?"0":"?",
((reg40&0x00200000)==0x00200000)?"4":
((reg40&0x00220000)==0x00220000)?"3":
((reg40&0x00340000)==0x00340000)?"2":
((reg40&0x00470000)==0x00470000)?"1":
((reg40&0x005D0000)==0x005D0000)?"0":"?");
return p-buffer; /* => must be less than 4k! */
}
static byte svwks_proc;
#endif /* defined(DISPLAY_SVWKS_TIMINGS) && defined(CONFIG_PROC_FS) */
#define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
static struct pci_dev *isa_dev;
......@@ -570,13 +434,6 @@ static unsigned int __init svwks_init_chipset(struct pci_dev *dev)
pci_write_config_byte(dev, 0x5A, btr);
}
#if defined(DISPLAY_SVWKS_TIMINGS) && defined(CONFIG_PROC_FS)
if (!svwks_proc) {
svwks_proc = 1;
bmide_dev = dev;
svwks_display_info = &svwks_get_info;
}
#endif /* DISPLAY_SVWKS_TIMINGS && CONFIG_PROC_FS */
return 0;
}
......
drivers/ide/sis5513.c
View file @ d14d5dc1
......@@ -59,7 +59,6 @@
/* When BROKEN_LEVEL is defined it limits the DMA mode
at boot time to its value */
// #define BROKEN_LEVEL XFER_SW_DMA_0
#undef DISPLAY_SIS_TIMINGS
/* Miscellaneaous flags */
#define SIS5513_LATENCY 0x01
......@@ -208,207 +207,6 @@ static byte cycle_time_value[][XFER_UDMA_5 - XFER_UDMA_0 + 1] = {
static struct pci_dev *host_dev = NULL;
/*
* Printing configuration
*/
#if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS)
#include <linux/stat.h>
#include <linux/proc_fs.h>
static int sis_get_info(char *, char **, off_t, int);
extern int (*sis_display_info)(char *, char **, off_t, int); /* ide-proc.c */
static struct pci_dev *bmide_dev;
static char* cable_type[] = {
"80 pins",
"40 pins"
};
static char* recovery_time[] ={
"12 PCICLK", "1 PCICLK",
"2 PCICLK", "3 PCICLK",
"4 PCICLK", "5 PCICLCK",
"6 PCICLK", "7 PCICLCK",
"8 PCICLK", "9 PCICLCK",
"10 PCICLK", "11 PCICLK",
"13 PCICLK", "14 PCICLK",
"15 PCICLK", "15 PCICLK"
};
static char* active_time[] = {
"8 PCICLK", "1 PCICLCK",
"2 PCICLK", "3 PCICLK",
"4 PCICLK", "5 PCICLK",
"6 PCICLK", "12 PCICLK"
};
static char* cycle_time[] = {
"Reserved", "2 CLK",
"3 CLK", "4 CLK",
"5 CLK", "6 CLK",
"7 CLK", "8 CLK",
"9 CLK", "10 CLK",
"11 CLK", "12 CLK",
"Reserved", "Reserved",
"Reserved", "Reserved"
};
/* Generic add master or slave info function */
static char* get_drives_info (char *buffer, byte pos)
{
byte reg00, reg01, reg10, reg11; /* timing registers */
char* p = buffer;
/* Postwrite/Prefetch */
pci_read_config_byte(bmide_dev, 0x4b, &reg00);
p += sprintf(p, "Drive %d: Postwrite %s \t \t Postwrite %s\n",
pos, (reg00 & (0x10 << pos)) ? "Enabled" : "Disabled",
(reg00 & (0x40 << pos)) ? "Enabled" : "Disabled");
p += sprintf(p, " Prefetch %s \t \t Prefetch %s\n",
(reg00 & (0x01 << pos)) ? "Enabled" : "Disabled",
(reg00 & (0x04 << pos)) ? "Enabled" : "Disabled");
pci_read_config_byte(bmide_dev, 0x40+2*pos, &reg00);
pci_read_config_byte(bmide_dev, 0x41+2*pos, &reg01);
pci_read_config_byte(bmide_dev, 0x44+2*pos, &reg10);
pci_read_config_byte(bmide_dev, 0x45+2*pos, &reg11);
/* UDMA */
if (chipset_family >= ATA_33) {
p += sprintf(p, " UDMA %s \t \t \t UDMA %s\n",
(reg01 & 0x80) ? "Enabled" : "Disabled",
(reg11 & 0x80) ? "Enabled" : "Disabled");
p += sprintf(p, " UDMA Cycle Time ");
switch(chipset_family) {
case ATA_33: p += sprintf(p, cycle_time[(reg01 & 0x60) >> 5]); break;
case ATA_66:
case ATA_100a: p += sprintf(p, cycle_time[(reg01 & 0x70) >> 4]); break;
case ATA_100: p += sprintf(p, cycle_time[reg01 & 0x0F]); break;
case ATA_133:
default: p += sprintf(p, "133+ ?"); break;
}
p += sprintf(p, " \t UDMA Cycle Time ");
switch(chipset_family) {
case ATA_33: p += sprintf(p, cycle_time[(reg11 & 0x60) >> 5]); break;
case ATA_66:
case ATA_100a: p += sprintf(p, cycle_time[(reg11 & 0x70) >> 4]); break;
case ATA_100: p += sprintf(p, cycle_time[reg11 & 0x0F]); break;
case ATA_133:
default: p += sprintf(p, "133+ ?"); break;
}
p += sprintf(p, "\n");
}
/* Data Active */
p += sprintf(p, " Data Active Time ");
switch(chipset_family) {
case ATA_00:
case ATA_16: /* confirmed */
case ATA_33:
case ATA_66:
case ATA_100a: p += sprintf(p, active_time[reg01 & 0x07]); break;
case ATA_100: p += sprintf(p, active_time[(reg00 & 0x70) >> 4]); break;
case ATA_133:
default: p += sprintf(p, "133+ ?"); break;
}
p += sprintf(p, " \t Data Active Time ");
switch(chipset_family) {
case ATA_00:
case ATA_16:
case ATA_33:
case ATA_66:
case ATA_100a: p += sprintf(p, active_time[reg11 & 0x07]); break;
case ATA_100: p += sprintf(p, active_time[(reg10 & 0x70) >> 4]); break;
case ATA_133:
default: p += sprintf(p, "133+ ?"); break;
}
p += sprintf(p, "\n");
/* Data Recovery */
/* warning: may need (reg&0x07) for pre ATA66 chips */
p += sprintf(p, " Data Recovery Time %s \t Data Recovery Time %s\n",
recovery_time[reg00 & 0x0f], recovery_time[reg10 & 0x0f]);
return p;
}
static char* get_masters_info(char* buffer)
{
return get_drives_info(buffer, 0);
}
static char* get_slaves_info(char* buffer)
{
return get_drives_info(buffer, 1);
}
/* Main get_info, called on /proc/ide/sis reads */
static int sis_get_info (char *buffer, char **addr, off_t offset, int count)
{
char *p = buffer;
byte reg;
u16 reg2, reg3;
p += sprintf(p, "\nSiS 5513 ");
switch(chipset_family) {
case ATA_00: p += sprintf(p, "Unknown???"); break;
case ATA_16: p += sprintf(p, "DMA 16"); break;
case ATA_33: p += sprintf(p, "Ultra 33"); break;
case ATA_66: p += sprintf(p, "Ultra 66"); break;
case ATA_100a:
case ATA_100: p += sprintf(p, "Ultra 100"); break;
case ATA_133:
default: p+= sprintf(p, "Ultra 133+"); break;
}
p += sprintf(p, " chipset\n");
p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
/* Status */
pci_read_config_byte(bmide_dev, 0x4a, &reg);
p += sprintf(p, "Channel Status: ");
if (chipset_family < ATA_66) {
p += sprintf(p, "%s \t \t \t \t %s\n",
(reg & 0x04) ? "On" : "Off",
(reg & 0x02) ? "On" : "Off");
} else {
p += sprintf(p, "%s \t \t \t \t %s \n",
(reg & 0x02) ? "On" : "Off",
(reg & 0x04) ? "On" : "Off");
}
/* Operation Mode */
pci_read_config_byte(bmide_dev, 0x09, &reg);
p += sprintf(p, "Operation Mode: %s \t \t \t %s \n",
(reg & 0x01) ? "Native" : "Compatible",
(reg & 0x04) ? "Native" : "Compatible");
/* 80-pin cable ? */
if (chipset_family > ATA_33) {
pci_read_config_byte(bmide_dev, 0x48, &reg);
p += sprintf(p, "Cable Type: %s \t \t \t %s\n",
(reg & 0x10) ? cable_type[1] : cable_type[0],
(reg & 0x20) ? cable_type[1] : cable_type[0]);
}
/* Prefetch Count */
pci_read_config_word(bmide_dev, 0x4c, &reg2);
pci_read_config_word(bmide_dev, 0x4e, &reg3);
p += sprintf(p, "Prefetch Count: %d \t \t \t \t %d\n",
reg2, reg3);
p = get_masters_info(p);
p = get_slaves_info(p);
return p-buffer;
}
byte sis_proc = 0;
#endif
static int sis5513_ratemask(struct ata_device *drive)
{
int map = 0;
......@@ -800,14 +598,6 @@ static unsigned int __init pci_init_sis5513(struct pci_dev *dev)
case ATA_00:
default: break;
}
#if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS)
if (!sis_proc) {
sis_proc = 1;
bmide_dev = dev;
sis_display_info = &sis_get_info;
}
#endif
}
#ifdef DEBUG
sis5513_load_verify_registers(dev, "pci_init_sis5513 end");
......
drivers/ide/via82cxxx.c
View file @ d14d5dc1
......@@ -134,139 +134,6 @@ static unsigned char via_enabled;
static unsigned int via_80w;
static char *via_dma[] = { "MWDMA16", "UDMA33", "UDMA66", "UDMA100", "UDMA133" };
/*
* VIA /proc entry.
*/
#if 0 && defined(CONFIG_PROC_FS)
#include <linux/stat.h>
#include <linux/proc_fs.h>
int via_proc, via_base;
static struct pci_dev *bmide_dev, *isa_dev;
extern int (*via_display_info)(char *, char **, off_t, int); /* ide-proc.c */
static char *via_control3[] = { "No limit", "64", "128", "192" };
#define via_print(format, arg...) p += sprintf(p, format "\n" , ## arg)
#define via_print_drive(name, format, arg...)\
p += sprintf(p, name); for (i = 0; i < 4; i++) p += sprintf(p, format, ## arg); p += sprintf(p, "\n");
static int via_get_info(char *buffer, char **addr, off_t offset, int count)
{
int speed[4], cycle[4], setup[4], active[4], recover[4], den[4],
uen[4], udma[4], umul[4], active8b[4], recover8b[4];
struct pci_dev *dev = bmide_dev;
unsigned int v, u, i;
unsigned short c, w;
unsigned char t, x;
char *p = buffer;
via_print("----------VIA BusMastering IDE Configuration----------------");
via_print("Driver Version: 3.34");
via_print("South Bridge: VIA %s", via_config->name);
pci_read_config_byte(isa_dev, PCI_REVISION_ID, &t);
pci_read_config_byte(dev, PCI_REVISION_ID, &x);
via_print("Revision: ISA %#x IDE %#x", t, x);
via_print("Highest DMA rate: %s", via_dma[via_config->flags & VIA_UDMA]);
via_print("BM-DMA base: %#x", via_base);
via_print("PCI clock: %d.%dMHz", system_bus_speed / 1000, system_bus_speed / 100 % 10);
pci_read_config_byte(dev, VIA_MISC_1, &t);
via_print("Master Read Cycle IRDY: %dws", (t & 64) >> 6);
via_print("Master Write Cycle IRDY: %dws", (t & 32) >> 5);
via_print("BM IDE Status Register Read Retry: %s", (t & 8) ? "yes" : "no");
pci_read_config_byte(dev, VIA_MISC_3, &t);
via_print("Max DRDY Pulse Width: %s%s", via_control3[(t & 0x03)], (t & 0x03) ? " PCI clocks" : "");
via_print("-----------------------Primary IDE-------Secondary IDE------");
via_print("Read DMA FIFO flush: %10s%20s", (t & 0x80) ? "yes" : "no", (t & 0x40) ? "yes" : "no");
via_print("End Sector FIFO flush: %10s%20s", (t & 0x20) ? "yes" : "no", (t & 0x10) ? "yes" : "no");
pci_read_config_byte(dev, VIA_IDE_CONFIG, &t);
via_print("Prefetch Buffer: %10s%20s", (t & 0x80) ? "yes" : "no", (t & 0x20) ? "yes" : "no");
via_print("Post Write Buffer: %10s%20s", (t & 0x40) ? "yes" : "no", (t & 0x10) ? "yes" : "no");
pci_read_config_byte(dev, VIA_IDE_ENABLE, &t);
via_print("Enabled: %10s%20s", (t & 0x02) ? "yes" : "no", (t & 0x01) ? "yes" : "no");
c = inb(via_base + 0x02) | (inb(via_base + 0x0a) << 8);
via_print("Simplex only: %10s%20s", (c & 0x80) ? "yes" : "no", (c & 0x8000) ? "yes" : "no");
via_print("Cable Type: %10s%20s", (via_80w & 1) ? "80w" : "40w", (via_80w & 2) ? "80w" : "40w");
via_print("-------------------drive0----drive1----drive2----drive3-----");
pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
pci_read_config_dword(dev, VIA_DRIVE_TIMING, &v);
pci_read_config_word(dev, VIA_8BIT_TIMING, &w);
if (via_config->flags & VIA_UDMA)
pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
else u = 0;
for (i = 0; i < 4; i++) {
setup[i] = ((t >> ((3 - i) << 1)) & 0x3) + 1;
recover8b[i] = ((w >> ((1 - (i >> 1)) << 3)) & 0xf) + 1;
active8b[i] = ((w >> (((1 - (i >> 1)) << 3) + 4)) & 0xf) + 1;
active[i] = ((v >> (((3 - i) << 3) + 4)) & 0xf) + 1;
recover[i] = ((v >> ((3 - i) << 3)) & 0xf) + 1;
udma[i] = ((u >> ((3 - i) << 3)) & 0x7) + 2;
umul[i] = ((u >> (((3 - i) & 2) << 3)) & 0x8) ? 1 : 2;
uen[i] = ((u >> ((3 - i) << 3)) & 0x20);
den[i] = (c & ((i & 1) ? 0x40 : 0x20) << ((i & 2) << 2));
speed[i] = 2 * system_bus_speed / (active[i] + recover[i]);
cycle[i] = 1000000 * (active[i] + recover[i]) / system_bus_speed;
if (!uen[i] || !den[i])
continue;
switch (via_config->flags & VIA_UDMA) {
case VIA_UDMA_33:
speed[i] = 2 * system_bus_speed / udma[i];
cycle[i] = 1000000 * udma[i] / system_bus_speed;
break;
case VIA_UDMA_66:
speed[i] = 4 * system_bus_speed / (udma[i] * umul[i]);
cycle[i] = 500000 * (udma[i] * umul[i]) / system_bus_speed;
break;
case VIA_UDMA_100:
speed[i] = 6 * system_bus_speed / udma[i];
cycle[i] = 333333 * udma[i] / system_bus_speed;
break;
case VIA_UDMA_133:
speed[i] = 8 * system_bus_speed / udma[i];
cycle[i] = 250000 * udma[i] / system_bus_speed;
break;
}
}
via_print_drive("Transfer Mode: ", "%10s", den[i] ? (uen[i] ? "UDMA" : "DMA") : "PIO");
via_print_drive("Address Setup: ", "%8dns", 1000000 * setup[i] / system_bus_speed);
via_print_drive("Cmd Active: ", "%8dns", 1000000 * active8b[i] / system_bus_speed);
via_print_drive("Cmd Recovery: ", "%8dns", 1000000 * recover8b[i] / system_bus_speed);
via_print_drive("Data Active: ", "%8dns", 1000000 * active[i] / system_bus_speed);
via_print_drive("Data Recovery: ", "%8dns", 1000000 * recover[i] / system_bus_speed);
via_print_drive("Cycle Time: ", "%8dns", cycle[i]);
via_print_drive("Transfer Rate: ", "%4d.%dMB/s", speed[i] / 1000, speed[i] / 100 % 10);
return p - buffer; /* hoping it is less than 4K... */
}
#endif
/*
* via_set_speed() writes timing values to the chipset registers
*/
......
drivers/scsi/ide-scsi.c
View file @ d14d5dc1
This diff is collapsed.
drivers/scsi/scsi_scan.c
View file @ d14d5dc1
......@@ -25,16 +25,16 @@
/*
* Flags for irregular SCSI devices that need special treatment
*/
#define BLIST_NOLUN 0x001 /* Don't scan for LUNs */
#define BLIST_FORCELUN 0x002 /* Known to have LUNs, force sanning */
#define BLIST_BORKEN 0x004 /* Flag for broken handshaking */
#define BLIST_KEY 0x008 /* Needs to be unlocked by special command */
#define BLIST_SINGLELUN 0x010 /* LUNs should better not be used in parallel */
#define BLIST_NOLUN 0x001 /* Don't scan for LUNs */
#define BLIST_FORCELUN 0x002 /* Known to have LUNs, force sanning */
#define BLIST_BORKEN 0x004 /* Flag for broken handshaking */
#define BLIST_KEY 0x008 /* Needs to be unlocked by special command */
#define BLIST_SINGLELUN 0x010 /* LUNs should better not be used in parallel */
#define BLIST_NOTQ 0x020 /* Buggy Tagged Command Queuing */
#define BLIST_SPARSELUN 0x040 /* Non consecutive LUN numbering */
#define BLIST_SPARSELUN 0x040 /* Non consecutive LUN numbering */
#define BLIST_MAX5LUN 0x080 /* Avoid LUNS >= 5 */
#define BLIST_ISDISK 0x100 /* Treat as (removable) disk */
#define BLIST_ISROM 0x200 /* Treat as (removable) CD-ROM */
#define BLIST_ISDISK 0x100 /* Treat as (removable) disk */
#define BLIST_ISROM 0x200 /* Treat as (removable) CD-ROM */
#define BLIST_LARGELUN 0x400 /* LUNs larger than 7 despite reporting as SCSI 2 */
#define BLIST_INQUIRY_36 0x800 /* override additional length field */
#define BLIST_INQUIRY_58 0x1000 /* ... for broken inquiry responses */
......@@ -86,7 +86,7 @@ static struct dev_info device_list[] =
{"MAXTOR", "MXT-1240S", "I1.2", BLIST_NOLUN}, /* Locks up when LUN>0 polled */
{"MAXTOR", "XT-4170S", "B5A", BLIST_NOLUN}, /* Locks-up sometimes when LUN>0 polled. */
{"MAXTOR", "XT-8760S", "B7B", BLIST_NOLUN}, /* guess what? */
{"MEDIAVIS", "RENO CD-ROMX2A", "2.03", BLIST_NOLUN}, /*Responds to all lun */
{"MEDIAVIS", "RENO CD-ROMX2A", "2.03", BLIST_NOLUN}, /* Responds to all lun */
{"NEC", "CD-ROM DRIVE:841", "1.0", BLIST_NOLUN}, /* Locks-up when LUN>0 polled. */
{"PHILIPS", "PCA80SC", "V4-2", BLIST_NOLUN}, /* Responds to all lun */
{"RODIME", "RO3000S", "2.33", BLIST_NOLUN}, /* Locks up if polled for lun != 0 */
......@@ -98,7 +98,7 @@ static struct dev_info device_list[] =
* SCSI code to reset bus.*/
{"SEAGATE", "ST296", "921", BLIST_NOLUN}, /* Responds to all lun */
{"SEAGATE", "ST1581", "6538", BLIST_NOLUN}, /* Responds to all lun */
{"SONY", "CD-ROM CDU-541", "4.3d", BLIST_NOLUN},
{"SONY", "CD-ROM CDU-541", "4.3d", BLIST_NOLUN},
{"SONY", "CD-ROM CDU-55S", "1.0i", BLIST_NOLUN},
{"SONY", "CD-ROM CDU-561", "1.7x", BLIST_NOLUN},
{"SONY", "CD-ROM CDU-8012", "*", BLIST_NOLUN},
......@@ -120,8 +120,7 @@ static struct dev_info device_list[] =
{"HP", "C1790A", "", BLIST_NOLUN}, /* scanjet iip */
{"HP", "C2500A", "", BLIST_NOLUN}, /* scanjet iicx */
{"YAMAHA", "CDR100", "1.00", BLIST_NOLUN}, /* Locks up if polled for lun != 0 */
{"YAMAHA", "CDR102", "1.00", BLIST_NOLUN}, /* Locks up if polled for lun != 0
* extra reset */
{"YAMAHA", "CDR102", "1.00", BLIST_NOLUN}, /* Locks up if polled for lun != 0 extra reset */
{"YAMAHA", "CRW8424S", "1.0", BLIST_NOLUN}, /* Locks up if polled for lun != 0 */
{"YAMAHA", "CRW6416S", "1.0c", BLIST_NOLUN}, /* Locks up if polled for lun != 0 */
{"MITSUMI", "CD-R CR-2201CS", "6119", BLIST_NOLUN}, /* Locks up if polled for lun != 0 */
......@@ -453,7 +452,7 @@ void scan_scsis(struct Scsi_Host *shpnt,
else
lun0_sl = find_lun0_scsi_level(channel, dev, shpnt);
scan_scsis_single(channel, dev, lun, lun0_sl, &SDpnt, shpnt,
scsi_result);
scsi_result);
if (SDpnt != oldSDpnt) {
/* it could happen the blockdevice hasn't yet been inited */
......
include/linux/atapi.h
View file @ d14d5dc1
......@@ -20,6 +20,19 @@
#define IDEFLOPPY_PC_BUFFER_SIZE 256
#define IDETAPE_PC_BUFFER_SIZE 256
/*
* Packet flags bits.
*/
#define PC_ABORT 0 /* set when an error is considered normal - we won't retry */
#define PC_WAIT_FOR_DSC 1 /* 1 when polling for DSC on a media access command */
#define PC_DMA_RECOMMENDED 2 /* 1 when we prefer to use DMA if possible */
#define PC_DMA_IN_PROGRESS 3 /* 1 while DMA in progress */
#define PC_DMA_ERROR 4 /* 1 when encountered problem during DMA */
#define PC_WRITING 5 /* data direction */
#define PC_SUPPRESS_ERROR 6 /* suppress error reporting */
#define PC_TRANSFORM 7 /* transform SCSI commands */
/* This struct get's shared between different drivers.
*/
struct atapi_packet_command {
......
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