Commit d16c0d72 authored by Nishanth Menon's avatar Nishanth Menon Committed by Tony Lindgren

ARM: OMAP: DRA7: powerdomain data: Set L3init and L4per to ON

As per the latest revision F of public TRM for DRA7/AM57xx SoCs
SPRUHZ6F[1] (April 2016), L4Per and L3init power domains now operate in
always "ON" mode due to asymmetric aging limitations. Update the same

[1] http://www.ti.com/lit/pdf/spruhz6Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 8d29bdba
...@@ -111,7 +111,7 @@ static struct powerdomain l4per_7xx_pwrdm = { ...@@ -111,7 +111,7 @@ static struct powerdomain l4per_7xx_pwrdm = {
.name = "l4per_pwrdm", .name = "l4per_pwrdm",
.prcm_offs = DRA7XX_PRM_L4PER_INST, .prcm_offs = DRA7XX_PRM_L4PER_INST,
.prcm_partition = DRA7XX_PRM_PARTITION, .prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_RET_ON, .pwrsts = PWRSTS_ON,
.pwrsts_logic_ret = PWRSTS_RET, .pwrsts_logic_ret = PWRSTS_RET,
.banks = 2, .banks = 2,
.pwrsts_mem_ret = { .pwrsts_mem_ret = {
...@@ -260,7 +260,7 @@ static struct powerdomain l3init_7xx_pwrdm = { ...@@ -260,7 +260,7 @@ static struct powerdomain l3init_7xx_pwrdm = {
.name = "l3init_pwrdm", .name = "l3init_pwrdm",
.prcm_offs = DRA7XX_PRM_L3INIT_INST, .prcm_offs = DRA7XX_PRM_L3INIT_INST,
.prcm_partition = DRA7XX_PRM_PARTITION, .prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_RET_ON, .pwrsts = PWRSTS_ON,
.pwrsts_logic_ret = PWRSTS_RET, .pwrsts_logic_ret = PWRSTS_RET,
.banks = 3, .banks = 3,
.pwrsts_mem_ret = { .pwrsts_mem_ret = {
......
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