Commit d23dfefa authored by Fabio Estevam's avatar Fabio Estevam Committed by Shawn Guo

ARM: dts: imx6sl-warp: Add changes for rev1.12

Warp board rev1.12 is the version of the hardware that will be publicly
available for the customers.

It uses UART5 as the Bluetooth serial port as well as some
additional signals for HOSTWAKE on Wifi and Bluetooth.

Make the changes to support the rev1.12 hardware.
Signed-off-by: default avatarFabio Estevam <fabio.estevam@freescale.com>
Acked-by: default avatarOtavio Salvador <otavio@ossystems.com.br>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent d28be499
...@@ -61,7 +61,9 @@ memory { ...@@ -61,7 +61,9 @@ memory {
usdhc3_pwrseq: usdhc3_pwrseq { usdhc3_pwrseq: usdhc3_pwrseq {
compatible = "mmc-pwrseq-simple"; compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>, /* WL_REG_ON */ reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>, /* WL_REG_ON */
<&gpio4 7 GPIO_ACTIVE_LOW>, /* WL_HOSTWAKE */
<&gpio3 25 GPIO_ACTIVE_LOW>, /* BT_REG_ON */ <&gpio3 25 GPIO_ACTIVE_LOW>, /* BT_REG_ON */
<&gpio3 27 GPIO_ACTIVE_LOW>, /* BT_HOSTWAKE */
<&gpio4 4 GPIO_ACTIVE_LOW>, /* BT_WAKE */ <&gpio4 4 GPIO_ACTIVE_LOW>, /* BT_WAKE */
<&gpio4 6 GPIO_ACTIVE_LOW>; /* BT_RST_N */ <&gpio4 6 GPIO_ACTIVE_LOW>; /* BT_RST_N */
}; };
...@@ -73,16 +75,16 @@ &uart1 { ...@@ -73,16 +75,16 @@ &uart1 {
status = "okay"; status = "okay";
}; };
&uart2 { &uart3 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>; pinctrl-0 = <&pinctrl_uart3>;
fsl,uart-has-rtscts;
status = "okay"; status = "okay";
}; };
&uart3 { &uart5 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>; pinctrl-0 = <&pinctrl_uart5>;
fsl,uart-has-rtscts;
status = "okay"; status = "okay";
}; };
...@@ -130,14 +132,6 @@ MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x41b0b1 ...@@ -130,14 +132,6 @@ MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x41b0b1
>; >;
}; };
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6SL_PAD_EPDC_D12__UART2_RX_DATA 0x41b0b1
MX6SL_PAD_EPDC_D13__UART2_TX_DATA 0x41b0b1
MX6SL_PAD_EPDC_D14__UART2_RTS_B 0x4130B1
MX6SL_PAD_EPDC_D15__UART2_CTS_B 0x4130B1
>;
};
pinctrl_uart3: uart3grp { pinctrl_uart3: uart3grp {
fsl,pins = < fsl,pins = <
...@@ -146,6 +140,15 @@ MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x41b0b1 ...@@ -146,6 +140,15 @@ MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x41b0b1
>; >;
}; };
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA 0x41b0b1
MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA 0x41b0b1
MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B 0x4130b1
MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B 0x4130b1
>;
};
pinctrl_usdhc2: usdhc2grp { pinctrl_usdhc2: usdhc2grp {
fsl,pins = < fsl,pins = <
MX6SL_PAD_SD2_CMD__SD2_CMD 0x417059 MX6SL_PAD_SD2_CMD__SD2_CMD 0x417059
......
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