Commit d28e2568 authored by Dave Airlie's avatar Dave Airlie

Merge tag 'amd-drm-fixes-5.14-2021-07-28' of...

Merge tag 'amd-drm-fixes-5.14-2021-07-28' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes

amd-drm-fixes-5.14-2021-07-28:

amdgpu:
- Fix resource leak in an error path
- Avoid stack contents exposure in error path
- pmops check fix for S0ix vs S3
- DCN 2.1 display fixes
- DCN 2.0 display fix
- Backlight control fix for laptops with HDR panels
- Maintainers updates
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210729025817.4145-1-alexander.deucher@amd.com
parents 80c7917d ec30ce41
...@@ -15468,6 +15468,8 @@ M: Pan, Xinhui <Xinhui.Pan@amd.com> ...@@ -15468,6 +15468,8 @@ M: Pan, Xinhui <Xinhui.Pan@amd.com>
L: amd-gfx@lists.freedesktop.org L: amd-gfx@lists.freedesktop.org
S: Supported S: Supported
T: git https://gitlab.freedesktop.org/agd5f/linux.git T: git https://gitlab.freedesktop.org/agd5f/linux.git
B: https://gitlab.freedesktop.org/drm/amd/-/issues
C: irc://irc.oftc.net/radeon
F: drivers/gpu/drm/amd/ F: drivers/gpu/drm/amd/
F: drivers/gpu/drm/radeon/ F: drivers/gpu/drm/radeon/
F: include/uapi/drm/amdgpu_drm.h F: include/uapi/drm/amdgpu_drm.h
......
...@@ -26,6 +26,7 @@ ...@@ -26,6 +26,7 @@
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/power_supply.h> #include <linux/power_supply.h>
#include <linux/pm_runtime.h> #include <linux/pm_runtime.h>
#include <linux/suspend.h>
#include <acpi/video.h> #include <acpi/video.h>
#include <acpi/actbl.h> #include <acpi/actbl.h>
...@@ -1042,7 +1043,7 @@ bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev) ...@@ -1042,7 +1043,7 @@ bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev)
#if defined(CONFIG_AMD_PMC) || defined(CONFIG_AMD_PMC_MODULE) #if defined(CONFIG_AMD_PMC) || defined(CONFIG_AMD_PMC_MODULE)
if (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0) { if (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0) {
if (adev->flags & AMD_IS_APU) if (adev->flags & AMD_IS_APU)
return true; return pm_suspend_target_state == PM_SUSPEND_TO_IDLE;
} }
#endif #endif
return false; return false;
......
...@@ -3504,13 +3504,13 @@ int amdgpu_device_init(struct amdgpu_device *adev, ...@@ -3504,13 +3504,13 @@ int amdgpu_device_init(struct amdgpu_device *adev,
r = amdgpu_device_get_job_timeout_settings(adev); r = amdgpu_device_get_job_timeout_settings(adev);
if (r) { if (r) {
dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n"); dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
goto failed_unmap; return r;
} }
/* early init functions */ /* early init functions */
r = amdgpu_device_ip_early_init(adev); r = amdgpu_device_ip_early_init(adev);
if (r) if (r)
goto failed_unmap; return r;
/* doorbell bar mapping and doorbell index init*/ /* doorbell bar mapping and doorbell index init*/
amdgpu_device_doorbell_init(adev); amdgpu_device_doorbell_init(adev);
...@@ -3736,10 +3736,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, ...@@ -3736,10 +3736,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
failed: failed:
amdgpu_vf_error_trans_all(adev); amdgpu_vf_error_trans_all(adev);
failed_unmap:
iounmap(adev->rmmio);
adev->rmmio = NULL;
return r; return r;
} }
......
...@@ -67,7 +67,7 @@ static int psp_v12_0_init_microcode(struct psp_context *psp) ...@@ -67,7 +67,7 @@ static int psp_v12_0_init_microcode(struct psp_context *psp)
err = psp_init_asd_microcode(psp, chip_name); err = psp_init_asd_microcode(psp, chip_name);
if (err) if (err)
goto out; return err;
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
...@@ -80,7 +80,7 @@ static int psp_v12_0_init_microcode(struct psp_context *psp) ...@@ -80,7 +80,7 @@ static int psp_v12_0_init_microcode(struct psp_context *psp)
} else { } else {
err = amdgpu_ucode_validate(adev->psp.ta_fw); err = amdgpu_ucode_validate(adev->psp.ta_fw);
if (err) if (err)
goto out2; goto out;
ta_hdr = (const struct ta_firmware_header_v1_0 *) ta_hdr = (const struct ta_firmware_header_v1_0 *)
adev->psp.ta_fw->data; adev->psp.ta_fw->data;
...@@ -105,10 +105,9 @@ static int psp_v12_0_init_microcode(struct psp_context *psp) ...@@ -105,10 +105,9 @@ static int psp_v12_0_init_microcode(struct psp_context *psp)
return 0; return 0;
out2: out:
release_firmware(adev->psp.ta_fw); release_firmware(adev->psp.ta_fw);
adev->psp.ta_fw = NULL; adev->psp.ta_fw = NULL;
out:
if (err) { if (err) {
dev_err(adev->dev, dev_err(adev->dev,
"psp v12.0: Failed to load firmware \"%s\"\n", "psp v12.0: Failed to load firmware \"%s\"\n",
......
...@@ -2429,9 +2429,9 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) ...@@ -2429,9 +2429,9 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
max_cll = conn_base->hdr_sink_metadata.hdmi_type1.max_cll; max_cll = conn_base->hdr_sink_metadata.hdmi_type1.max_cll;
min_cll = conn_base->hdr_sink_metadata.hdmi_type1.min_cll; min_cll = conn_base->hdr_sink_metadata.hdmi_type1.min_cll;
if (caps->ext_caps->bits.oled == 1 || if (caps->ext_caps->bits.oled == 1 /*||
caps->ext_caps->bits.sdr_aux_backlight_control == 1 || caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
caps->ext_caps->bits.hdr_aux_backlight_control == 1) caps->ext_caps->bits.hdr_aux_backlight_control == 1*/)
caps->aux_support = true; caps->aux_support = true;
if (amdgpu_backlight == 0) if (amdgpu_backlight == 0)
......
...@@ -197,7 +197,7 @@ void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, struct ...@@ -197,7 +197,7 @@ void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, struct
REG_UPDATE(DENTIST_DISPCLK_CNTL, REG_UPDATE(DENTIST_DISPCLK_CNTL,
DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider); DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider);
// REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 5, 100); REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 1000);
REG_UPDATE(DENTIST_DISPCLK_CNTL, REG_UPDATE(DENTIST_DISPCLK_CNTL,
DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider); DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider);
REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100); REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100);
......
...@@ -109,6 +109,7 @@ struct _vcs_dpi_ip_params_st dcn2_1_ip = { ...@@ -109,6 +109,7 @@ struct _vcs_dpi_ip_params_st dcn2_1_ip = {
.max_page_table_levels = 4, .max_page_table_levels = 4,
.pte_chunk_size_kbytes = 2, .pte_chunk_size_kbytes = 2,
.meta_chunk_size_kbytes = 2, .meta_chunk_size_kbytes = 2,
.min_meta_chunk_size_bytes = 256,
.writeback_chunk_size_kbytes = 2, .writeback_chunk_size_kbytes = 2,
.line_buffer_size_bits = 789504, .line_buffer_size_bits = 789504,
.is_line_buffer_bpp_fixed = 0, .is_line_buffer_bpp_fixed = 0,
......
...@@ -841,6 +841,9 @@ static bool CalculatePrefetchSchedule( ...@@ -841,6 +841,9 @@ static bool CalculatePrefetchSchedule(
else else
*DestinationLinesForPrefetch = dst_y_prefetch_equ; *DestinationLinesForPrefetch = dst_y_prefetch_equ;
// Limit to prevent overflow in DST_Y_PREFETCH register
*DestinationLinesForPrefetch = dml_min(*DestinationLinesForPrefetch, 63.75);
dml_print("DML: VStartup: %d\n", VStartup); dml_print("DML: VStartup: %d\n", VStartup);
dml_print("DML: TCalc: %f\n", TCalc); dml_print("DML: TCalc: %f\n", TCalc);
dml_print("DML: TWait: %f\n", TWait); dml_print("DML: TWait: %f\n", TWait);
......
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