ARM: at91: make ecc register base soc independant

Signed-off-by: default avatarJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: default avatarNicolas Ferre <nicolas.ferre@atmel.com>
parent 80e91cb8
...@@ -398,8 +398,8 @@ static struct resource nand_resources[] = { ...@@ -398,8 +398,8 @@ static struct resource nand_resources[] = {
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
.start = AT91_BASE_SYS + AT91_ECC, .start = AT91CAP9_BASE_ECC,
.end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1, .end = AT91CAP9_BASE_ECC + SZ_512 - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
} }
}; };
......
...@@ -399,8 +399,8 @@ static struct resource nand_resources[] = { ...@@ -399,8 +399,8 @@ static struct resource nand_resources[] = {
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
.start = AT91_BASE_SYS + AT91_ECC, .start = AT91SAM9260_BASE_ECC,
.end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1, .end = AT91SAM9260_BASE_ECC + SZ_512 - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
} }
}; };
......
...@@ -473,8 +473,8 @@ static struct resource nand_resources[] = { ...@@ -473,8 +473,8 @@ static struct resource nand_resources[] = {
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
.start = AT91_BASE_SYS + AT91_ECC0, .start = AT91SAM9263_BASE_ECC0,
.end = AT91_BASE_SYS + AT91_ECC0 + SZ_512 - 1, .end = AT91SAM9263_BASE_ECC0 + SZ_512 - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
} }
}; };
......
...@@ -529,8 +529,8 @@ static struct resource nand_resources[] = { ...@@ -529,8 +529,8 @@ static struct resource nand_resources[] = {
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
.start = AT91_BASE_SYS + AT91_ECC, .start = AT91SAM9G45_BASE_ECC,
.end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1, .end = AT91SAM9G45_BASE_ECC + SZ_512 - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
} }
}; };
......
...@@ -248,8 +248,8 @@ static struct resource nand_resources[] = { ...@@ -248,8 +248,8 @@ static struct resource nand_resources[] = {
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
.start = AT91_BASE_SYS + AT91_ECC, .start = AT91SAM9RL_BASE_ECC,
.end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1, .end = AT91SAM9RL_BASE_ECC + SZ_512 - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
} }
}; };
......
...@@ -79,7 +79,6 @@ ...@@ -79,7 +79,6 @@
/* /*
* System Peripherals (offset from AT91_BASE_SYS) * System Peripherals (offset from AT91_BASE_SYS)
*/ */
#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS) #define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS)
#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
#define AT91_SMC (0xffffe800 - AT91_BASE_SYS) #define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
...@@ -98,6 +97,7 @@ ...@@ -98,6 +97,7 @@
(0xfffffd50 - AT91_BASE_SYS) : \ (0xfffffd50 - AT91_BASE_SYS) : \
(0xfffffd60 - AT91_BASE_SYS)) (0xfffffd60 - AT91_BASE_SYS))
#define AT91CAP9_BASE_ECC 0xffffe200
#define AT91CAP9_BASE_PIOA 0xfffff200 #define AT91CAP9_BASE_PIOA 0xfffff200
#define AT91CAP9_BASE_PIOB 0xfffff400 #define AT91CAP9_BASE_PIOB 0xfffff400
#define AT91CAP9_BASE_PIOC 0xfffff600 #define AT91CAP9_BASE_PIOC 0xfffff600
......
...@@ -80,7 +80,6 @@ ...@@ -80,7 +80,6 @@
/* /*
* System Peripherals (offset from AT91_BASE_SYS) * System Peripherals (offset from AT91_BASE_SYS)
*/ */
#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) #define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
...@@ -95,6 +94,7 @@ ...@@ -95,6 +94,7 @@
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
#define AT91SAM9260_BASE_ECC 0xffffe800
#define AT91SAM9260_BASE_PIOA 0xfffff400 #define AT91SAM9260_BASE_PIOA 0xfffff400
#define AT91SAM9260_BASE_PIOB 0xfffff600 #define AT91SAM9260_BASE_PIOB 0xfffff600
#define AT91SAM9260_BASE_PIOC 0xfffff800 #define AT91SAM9260_BASE_PIOC 0xfffff800
......
...@@ -74,10 +74,8 @@ ...@@ -74,10 +74,8 @@
/* /*
* System Peripherals (offset from AT91_BASE_SYS) * System Peripherals (offset from AT91_BASE_SYS)
*/ */
#define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS)
#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS) #define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS)
#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS) #define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS)
#define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS)
#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) #define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
#define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS) #define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
...@@ -93,6 +91,8 @@ ...@@ -93,6 +91,8 @@
#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS) #define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
#define AT91SAM9263_BASE_ECC0 0xffffe000
#define AT91SAM9263_BASE_ECC1 0xffffe600
#define AT91SAM9263_BASE_PIOA 0xfffff200 #define AT91SAM9263_BASE_PIOA 0xfffff200
#define AT91SAM9263_BASE_PIOB 0xfffff400 #define AT91SAM9263_BASE_PIOB 0xfffff400
#define AT91SAM9263_BASE_PIOC 0xfffff600 #define AT91SAM9263_BASE_PIOC 0xfffff600
......
...@@ -86,7 +86,6 @@ ...@@ -86,7 +86,6 @@
/* /*
* System Peripherals (offset from AT91_BASE_SYS) * System Peripherals (offset from AT91_BASE_SYS)
*/ */
#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
#define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS) #define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS)
#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
#define AT91_SMC (0xffffe800 - AT91_BASE_SYS) #define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
...@@ -103,6 +102,7 @@ ...@@ -103,6 +102,7 @@
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS) #define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS)
#define AT91SAM9G45_BASE_ECC 0xffffe200
#define AT91SAM9G45_BASE_PIOA 0xfffff200 #define AT91SAM9G45_BASE_PIOA 0xfffff200
#define AT91SAM9G45_BASE_PIOB 0xfffff400 #define AT91SAM9G45_BASE_PIOB 0xfffff400
#define AT91SAM9G45_BASE_PIOC 0xfffff600 #define AT91SAM9G45_BASE_PIOC 0xfffff600
......
...@@ -70,7 +70,6 @@ ...@@ -70,7 +70,6 @@
* System Peripherals (offset from AT91_BASE_SYS) * System Peripherals (offset from AT91_BASE_SYS)
*/ */
#define AT91_DMA (0xffffe600 - AT91_BASE_SYS) #define AT91_DMA (0xffffe600 - AT91_BASE_SYS)
#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) #define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
...@@ -87,6 +86,7 @@ ...@@ -87,6 +86,7 @@
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) #define AT91_RTC (0xfffffe00 - AT91_BASE_SYS)
#define AT91SAM9RL_BASE_ECC 0xffffe800
#define AT91SAM9RL_BASE_PIOA 0xfffff400 #define AT91SAM9RL_BASE_PIOA 0xfffff400
#define AT91SAM9RL_BASE_PIOB 0xfffff600 #define AT91SAM9RL_BASE_PIOB 0xfffff600
#define AT91SAM9RL_BASE_PIOC 0xfffff800 #define AT91SAM9RL_BASE_PIOC 0xfffff800
......
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