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Commit d2a7bd36 authored by Xi Pardee's avatar Xi Pardee Committed by Hans de Goede
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platform/x86:intel/pmc: Add Meteor Lake IOE-M PMC related maps 

Add device ID and register maps for the PMC in IO expansion die M in
Meteor Lake.
Signed-off-by: default avatarXi Pardee <xi.pardee@intel.com>
Signed-off-by: default avatarRajvi Jingar <rajvi.jingar@linux.intel.com>
Reviewed-by: default avatarIlpo Järvinen <ilpo.jarvinen@linux.intel.com>
Link: https://lore.kernel.org/r/20230613225347.2720665-9-rajvi.jingar@linux.intel.comSigned-off-by: default avatarHans de Goede <hdegoede@redhat.com>
parent 9f17728d
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Showing with 151 additions and 0 deletions
drivers/platform/x86/intel/pmc/core.h
View file @ d2a7bd36
......@@ -478,6 +478,12 @@ extern const struct pmc_bit_map mtl_ioep_vnn_req_status_3_map[];
extern const struct pmc_bit_map mtl_ioep_vnn_misc_status_map[];
extern const struct pmc_bit_map *mtl_ioep_lpm_maps[];
extern const struct pmc_reg_map mtl_ioep_reg_map;
extern const struct pmc_bit_map mtl_ioem_pfear_map[];
extern const struct pmc_bit_map *ext_mtl_ioem_pfear_map[];
extern const struct pmc_bit_map mtl_ioem_power_gating_status_1_map[];
extern const struct pmc_bit_map mtl_ioem_vnn_req_status_1_map[];
extern const struct pmc_bit_map *mtl_ioem_lpm_maps[];
extern const struct pmc_reg_map mtl_ioem_reg_map;
extern void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev);
extern int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value);
......
drivers/platform/x86/intel/pmc/mtl.c
View file @ d2a7bd36
......@@ -784,8 +784,149 @@ const struct pmc_reg_map mtl_ioep_reg_map = {
.ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED,
};
const struct pmc_bit_map mtl_ioem_pfear_map[] = {
{"PMC_0", BIT(0)},
{"OPI", BIT(1)},
{"TCSS", BIT(2)},
{"RSVD3", BIT(3)},
{"SPA", BIT(4)},
{"SPB", BIT(5)},
{"SPC", BIT(6)},
{"IOE_D2D_3", BIT(7)},
{"RSVD8", BIT(0)},
{"RSVD9", BIT(1)},
{"SPE", BIT(2)},
{"RSVD11", BIT(3)},
{"RSVD12", BIT(4)},
{"SPD", BIT(5)},
{"ACE_7", BIT(6)},
{"RSVD15", BIT(7)},
{"ACE_0", BIT(0)},
{"FIACPCB_P", BIT(1)},
{"P2S", BIT(2)},
{"RSVD19", BIT(3)},
{"ACE_8", BIT(4)},
{"IOE_D2D_0", BIT(5)},
{"FUSE", BIT(6)},
{"RSVD23", BIT(7)},
{"FIACPCB_P5", BIT(0)},
{"ACE_3", BIT(1)},
{"RSF5", BIT(2)},
{"ACE_2", BIT(3)},
{"ACE_4", BIT(4)},
{"RSVD29", BIT(5)},
{"RSF10", BIT(6)},
{"MPFPW5", BIT(7)},
{"PSF9", BIT(0)},
{"MPFPW4", BIT(1)},
{"RSVD34", BIT(2)},
{"RSVD35", BIT(3)},
{"RSVD36", BIT(4)},
{"RSVD37", BIT(5)},
{"RSVD38", BIT(6)},
{"RSVD39", BIT(7)},
{"SBR0", BIT(0)},
{"SBR1", BIT(1)},
{"SBR2", BIT(2)},
{"SBR3", BIT(3)},
{"SBR4", BIT(4)},
{"RSVD45", BIT(5)},
{"RSVD46", BIT(6)},
{"RSVD47", BIT(7)},
{"RSVD48", BIT(0)},
{"FIA_P5", BIT(1)},
{"RSVD50", BIT(2)},
{"RSVD51", BIT(3)},
{"RSVD52", BIT(4)},
{"RSVD53", BIT(5)},
{"RSVD54", BIT(6)},
{"ACE_1", BIT(7)},
{"RSVD56", BIT(0)},
{"ACE_5", BIT(1)},
{"RSVD58", BIT(2)},
{"G5FPW1", BIT(3)},
{"RSVD60", BIT(4)},
{"ACE_6", BIT(5)},
{"RSVD62", BIT(6)},
{"GBETSN1", BIT(7)},
{"RSVD64", BIT(0)},
{"FIA", BIT(1)},
{"RSVD66", BIT(2)},
{"FIA_P", BIT(3)},
{"TAM", BIT(4)},
{"GBETSN", BIT(5)},
{"IOE_D2D_2", BIT(6)},
{"IOE_D2D_1", BIT(7)},
{"SPF", BIT(0)},
{"PMC_1", BIT(1)},
{}
};
const struct pmc_bit_map *ext_mtl_ioem_pfear_map[] = {
mtl_ioem_pfear_map,
NULL
};
const struct pmc_bit_map mtl_ioem_power_gating_status_1_map[] = {
{"PSF9_PGD0_PG_STS", BIT(0)},
{"MPFPW4_PGD0_PG_STS", BIT(1)},
{"SBR0_PGD0_PG_STS", BIT(8)},
{"SBR1_PGD0_PG_STS", BIT(9)},
{"SBR2_PGD0_PG_STS", BIT(10)},
{"SBR3_PGD0_PG_STS", BIT(11)},
{"SBR4_PGD0_PG_STS", BIT(12)},
{"FIA_P5_PGD0_PG_STS", BIT(17)},
{"ACE_PGD1_PGD0_PG_STS", BIT(23)},
{"ACE_PGD5_PGD1_PG_STS", BIT(25)},
{"G5FPW1_PGD0_PG_STS", BIT(27)},
{"ACE_PGD6_PG_STS", BIT(29)},
{"GBETSN1_PGD0_PG_STS", BIT(31)},
{}
};
const struct pmc_bit_map *mtl_ioem_lpm_maps[] = {
mtl_ioep_clocksource_status_map,
mtl_ioep_power_gating_status_0_map,
mtl_ioem_power_gating_status_1_map,
mtl_ioep_power_gating_status_2_map,
mtl_ioep_d3_status_0_map,
mtl_ioep_d3_status_1_map,
mtl_ioep_d3_status_2_map,
mtl_ioep_d3_status_3_map,
mtl_ioep_vnn_req_status_0_map,
mtl_ioep_vnn_req_status_1_map,
mtl_ioep_vnn_req_status_2_map,
mtl_ioep_vnn_req_status_3_map,
mtl_ioep_vnn_misc_status_map,
mtl_socm_signal_status_map,
NULL
};
const struct pmc_reg_map mtl_ioem_reg_map = {
.regmap_length = MTL_IOE_PMC_MMIO_REG_LEN,
.pfear_sts = ext_mtl_ioem_pfear_map,
.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
.ppfear_buckets = MTL_IOE_PPFEAR_NUM_ENTRIES,
.lpm_status_offset = MTL_LPM_STATUS_OFFSET,
.lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
.lpm_sts = mtl_ioem_lpm_maps,
.ltr_show_sts = mtl_ioep_ltr_show_map,
.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
.ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED,
};
#define PMC_DEVID_SOCM 0x7e7f
#define PMC_DEVID_IOEP 0x7ecf
#define PMC_DEVID_IOEM 0x7ebf
static struct pmc_info mtl_pmc_info_list[] = {
{
.devid = PMC_DEVID_SOCM,
......@@ -795,6 +936,10 @@ static struct pmc_info mtl_pmc_info_list[] = {
.devid = PMC_DEVID_IOEP,
.map = &mtl_ioep_reg_map,
},
{
.devid = PMC_DEVID_IOEM,
.map = &mtl_ioem_reg_map
},
{}
};
......
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