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Commit d2a8e92f authored by Hans Verkuil's avatar Hans Verkuil Committed by Mauro Carvalho Chehab
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media: vpfe_capture: remove deprecated davinci drivers 

The vpfe_capture drivers do not use the vb2 framework for streaming
video, instead they use the old vb1 framework and nobody stepped in to
convert these drivers to vb2.

The hardware is very old, so the decision was made to remove them
altogether since we want to get rid of the old vb1 framework.
Signed-off-by: default avatarHans Verkuil <hverkuil-cisco@xs4all.nl>
Acked-by: default avatarLad Prabhakar <prabhakar.csengg@gmail.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@kernel.org>
parent 3673237b
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drivers/staging/media/Kconfig
View file @ d2a8e92f
......@@ -54,7 +54,6 @@ if STAGING_MEDIA_DEPRECATED
source "drivers/staging/media/deprecated/atmel/Kconfig"
source "drivers/staging/media/deprecated/saa7146/Kconfig"
source "drivers/staging/media/deprecated/tm6000/Kconfig"
source "drivers/staging/media/deprecated/vpfe_capture/Kconfig"
endif
endif
drivers/staging/media/Makefile
View file @ d2a8e92f
......@@ -10,5 +10,4 @@ obj-$(CONFIG_VIDEO_SUNXI) += sunxi/
obj-$(CONFIG_VIDEO_TEGRA) += tegra-video/
obj-$(CONFIG_VIDEO_IPU3_IMGU) += ipu3/
obj-$(CONFIG_VIDEO_TM6000) += deprecated/tm6000/
obj-y += deprecated/vpfe_capture/
obj-y += deprecated/saa7146/
drivers/staging/media/deprecated/vpfe_capture/Kconfig deleted 100644 → 0
View file @ 3673237b
# SPDX-License-Identifier: GPL-2.0-only
config VIDEO_DM6446_CCDC
tristate "TI DM6446 CCDC video capture driver"
depends on V4L_PLATFORM_DRIVERS
depends on VIDEO_DEV
depends on ARCH_DAVINCI || COMPILE_TEST
depends on I2C
select VIDEOBUF_DMA_CONTIG
help
Enables DaVinci CCD hw module. DaVinci CCDC hw interfaces
with decoder modules such as TVP5146 over BT656 or
sensor module such as MT9T001 over a raw interface. This
module configures the interface and CCDC/ISIF to do
video frame capture from slave decoders.
This driver is deprecated and is scheduled for removal by
the beginning of 2023. See the TODO file for more information.
To compile this driver as a module, choose M here. There will
be two modules called vpfe_capture.ko and dm644x_ccdc.ko
config VIDEO_DM355_CCDC
tristate "TI DM355 CCDC video capture driver"
depends on V4L_PLATFORM_DRIVERS
depends on VIDEO_DEV
depends on ARCH_DAVINCI || COMPILE_TEST
depends on I2C
select VIDEOBUF_DMA_CONTIG
help
Enables DM355 CCD hw module. DM355 CCDC hw interfaces
with decoder modules such as TVP5146 over BT656 or
sensor module such as MT9T001 over a raw interface. This
module configures the interface and CCDC/ISIF to do
video frame capture from a slave decoders
This driver is deprecated and is scheduled for removal by
the beginning of 2023. See the TODO file for more information.
To compile this driver as a module, choose M here. There will
be two modules called vpfe_capture.ko and dm355_ccdc.ko
config VIDEO_DM365_ISIF
tristate "TI DM365 ISIF video capture driver"
depends on V4L_PLATFORM_DRIVERS
depends on VIDEO_DEV
depends on ARCH_DAVINCI || COMPILE_TEST
depends on I2C
select VIDEOBUF_DMA_CONTIG
help
Enables ISIF hw module. This is the hardware module for
configuring ISIF in VPFE to capture Raw Bayer RGB data from
a image sensor or YUV data from a YUV source.
This driver is deprecated and is scheduled for removal by
the beginning of 2023. See the TODO file for more information.
To compile this driver as a module, choose M here. There will
be two modules called vpfe_capture.ko and isif.ko
drivers/staging/media/deprecated/vpfe_capture/Makefile deleted 100644 → 0
View file @ 3673237b
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_VIDEO_DM6446_CCDC) += vpfe_capture.o dm644x_ccdc.o
obj-$(CONFIG_VIDEO_DM355_CCDC) += vpfe_capture.o dm355_ccdc.o
obj-$(CONFIG_VIDEO_DM365_ISIF) += vpfe_capture.o isif.o
drivers/staging/media/deprecated/vpfe_capture/TODO deleted 100644 → 0
View file @ 3673237b
These are one of the few drivers still not using the vb2
framework, so these drivers are now deprecated with the intent of
removing them altogether by the beginning of 2023.
In order to keep these drivers they have to be converted to vb2.
If someone is interested in doing this work, then contact the
linux-media mailinglist (https://linuxtv.org/lists.php).
drivers/staging/media/deprecated/vpfe_capture/ccdc_hw_device.h deleted 100644 → 0
View file @ 3673237b
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2008-2009 Texas Instruments Inc
*
* ccdc device API
*/
#ifndef _CCDC_HW_DEVICE_H
#define _CCDC_HW_DEVICE_H
#ifdef __KERNEL__
#include <linux/videodev2.h>
#include <linux/device.h>
#include <media/davinci/vpfe_types.h>
#include <media/davinci/ccdc_types.h>
/*
* ccdc hw operations
*/
struct ccdc_hw_ops {
/* Pointer to initialize function to initialize ccdc device */
int (*open) (struct device *dev);
/* Pointer to deinitialize function */
int (*close) (struct device *dev);
/* set ccdc base address */
void (*set_ccdc_base)(void *base, int size);
/* Pointer to function to enable or disable ccdc */
void (*enable) (int en);
/* reset sbl. only for 6446 */
void (*reset) (void);
/* enable output to sdram */
void (*enable_out_to_sdram) (int en);
/* Pointer to function to set hw parameters */
int (*set_hw_if_params) (struct vpfe_hw_if_param *param);
/* get interface parameters */
int (*get_hw_if_params) (struct vpfe_hw_if_param *param);
/* Pointer to function to configure ccdc */
int (*configure) (void);
/* Pointer to function to set buffer type */
int (*set_buftype) (enum ccdc_buftype buf_type);
/* Pointer to function to get buffer type */
enum ccdc_buftype (*get_buftype) (void);
/* Pointer to function to set frame format */
int (*set_frame_format) (enum ccdc_frmfmt frm_fmt);
/* Pointer to function to get frame format */
enum ccdc_frmfmt (*get_frame_format) (void);
/* enumerate hw pix formats */
int (*enum_pix)(u32 *hw_pix, int i);
/* Pointer to function to set buffer type */
u32 (*get_pixel_format) (void);
/* Pointer to function to get pixel format. */
int (*set_pixel_format) (u32 pixfmt);
/* Pointer to function to set image window */
int (*set_image_window) (struct v4l2_rect *win);
/* Pointer to function to set image window */
void (*get_image_window) (struct v4l2_rect *win);
/* Pointer to function to get line length */
unsigned int (*get_line_length) (void);
/* Pointer to function to set frame buffer address */
void (*setfbaddr) (unsigned long addr);
/* Pointer to function to get field id */
int (*getfid) (void);
};
struct ccdc_hw_device {
/* ccdc device name */
char name[32];
/* module owner */
struct module *owner;
/* hw ops */
struct ccdc_hw_ops hw_ops;
};
/* Used by CCDC module to register & unregister with vpfe capture driver */
int vpfe_register_ccdc_device(const struct ccdc_hw_device *dev);
void vpfe_unregister_ccdc_device(const struct ccdc_hw_device *dev);
#endif
#endif
drivers/staging/media/deprecated/vpfe_capture/dm355_ccdc.h deleted 100644 → 0
View file @ 3673237b
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2005-2009 Texas Instruments Inc
*/
#ifndef _DM355_CCDC_H
#define _DM355_CCDC_H
#include <media/davinci/ccdc_types.h>
#include <media/davinci/vpfe_types.h>
/* enum for No of pixel per line to be avg. in Black Clamping */
enum ccdc_sample_length {
CCDC_SAMPLE_1PIXELS,
CCDC_SAMPLE_2PIXELS,
CCDC_SAMPLE_4PIXELS,
CCDC_SAMPLE_8PIXELS,
CCDC_SAMPLE_16PIXELS
};
/* enum for No of lines in Black Clamping */
enum ccdc_sample_line {
CCDC_SAMPLE_1LINES,
CCDC_SAMPLE_2LINES,
CCDC_SAMPLE_4LINES,
CCDC_SAMPLE_8LINES,
CCDC_SAMPLE_16LINES
};
/* enum for Alaw gamma width */
enum ccdc_gamma_width {
CCDC_GAMMA_BITS_13_4,
CCDC_GAMMA_BITS_12_3,
CCDC_GAMMA_BITS_11_2,
CCDC_GAMMA_BITS_10_1,
CCDC_GAMMA_BITS_09_0
};
enum ccdc_colpats {
CCDC_RED,
CCDC_GREEN_RED,
CCDC_GREEN_BLUE,
CCDC_BLUE
};
struct ccdc_col_pat {
enum ccdc_colpats olop;
enum ccdc_colpats olep;
enum ccdc_colpats elop;
enum ccdc_colpats elep;
};
enum ccdc_datasft {
CCDC_DATA_NO_SHIFT,
CCDC_DATA_SHIFT_1BIT,
CCDC_DATA_SHIFT_2BIT,
CCDC_DATA_SHIFT_3BIT,
CCDC_DATA_SHIFT_4BIT,
CCDC_DATA_SHIFT_5BIT,
CCDC_DATA_SHIFT_6BIT
};
enum ccdc_data_size {
CCDC_DATA_16BITS,
CCDC_DATA_15BITS,
CCDC_DATA_14BITS,
CCDC_DATA_13BITS,
CCDC_DATA_12BITS,
CCDC_DATA_11BITS,
CCDC_DATA_10BITS,
CCDC_DATA_8BITS
};
enum ccdc_mfilt1 {
CCDC_NO_MEDIAN_FILTER1,
CCDC_AVERAGE_FILTER1,
CCDC_MEDIAN_FILTER1
};
enum ccdc_mfilt2 {
CCDC_NO_MEDIAN_FILTER2,
CCDC_AVERAGE_FILTER2,
CCDC_MEDIAN_FILTER2
};
/* structure for ALaw */
struct ccdc_a_law {
/* Enable/disable A-Law */
unsigned char enable;
/* Gamma Width Input */
enum ccdc_gamma_width gamma_wd;
};
/* structure for Black Clamping */
struct ccdc_black_clamp {
/* only if bClampEnable is TRUE */
unsigned char b_clamp_enable;
/* only if bClampEnable is TRUE */
enum ccdc_sample_length sample_pixel;
/* only if bClampEnable is TRUE */
enum ccdc_sample_line sample_ln;
/* only if bClampEnable is TRUE */
unsigned short start_pixel;
/* only if bClampEnable is FALSE */
unsigned short sgain;
unsigned short dc_sub;
};
/* structure for Black Level Compensation */
struct ccdc_black_compensation {
/* Constant value to subtract from Red component */
unsigned char r;
/* Constant value to subtract from Gr component */
unsigned char gr;
/* Constant value to subtract from Blue component */
unsigned char b;
/* Constant value to subtract from Gb component */
unsigned char gb;
};
struct ccdc_float {
int integer;
unsigned int decimal;
};
#define CCDC_CSC_COEFF_TABLE_SIZE 16
/* structure for color space converter */
struct ccdc_csc {
unsigned char enable;
/*
* S8Q5. Use 2 decimal precision, user values range from -3.00 to 3.99.
* example - to use 1.03, set integer part as 1, and decimal part as 3
* to use -1.03, set integer part as -1 and decimal part as 3
*/
struct ccdc_float coeff[CCDC_CSC_COEFF_TABLE_SIZE];
};
/* Structures for Vertical Defect Correction*/
enum ccdc_vdf_csl {
CCDC_VDF_NORMAL,
CCDC_VDF_HORZ_INTERPOL_SAT,
CCDC_VDF_HORZ_INTERPOL
};
enum ccdc_vdf_cuda {
CCDC_VDF_WHOLE_LINE_CORRECT,
CCDC_VDF_UPPER_DISABLE
};
enum ccdc_dfc_mwr {
CCDC_DFC_MWR_WRITE_COMPLETE,
CCDC_DFC_WRITE_REG
};
enum ccdc_dfc_mrd {
CCDC_DFC_READ_COMPLETE,
CCDC_DFC_READ_REG
};
enum ccdc_dfc_ma_rst {
CCDC_DFC_INCR_ADDR,
CCDC_DFC_CLR_ADDR
};
enum ccdc_dfc_mclr {
CCDC_DFC_CLEAR_COMPLETE,
CCDC_DFC_CLEAR
};
struct ccdc_dft_corr_ctl {
enum ccdc_vdf_csl vdfcsl;
enum ccdc_vdf_cuda vdfcuda;
unsigned int vdflsft;
};
struct ccdc_dft_corr_mem_ctl {
enum ccdc_dfc_mwr dfcmwr;
enum ccdc_dfc_mrd dfcmrd;
enum ccdc_dfc_ma_rst dfcmarst;
enum ccdc_dfc_mclr dfcmclr;
};
#define CCDC_DFT_TABLE_SIZE 16
/*
* Main Structure for vertical defect correction. Vertical defect
* correction can correct up to 16 defects if defects less than 16
* then pad the rest with 0
*/
struct ccdc_vertical_dft {
unsigned char ver_dft_en;
unsigned char gen_dft_en;
unsigned int saturation_ctl;
struct ccdc_dft_corr_ctl dft_corr_ctl;
struct ccdc_dft_corr_mem_ctl dft_corr_mem_ctl;
int table_size;
unsigned int dft_corr_horz[CCDC_DFT_TABLE_SIZE];
unsigned int dft_corr_vert[CCDC_DFT_TABLE_SIZE];
unsigned int dft_corr_sub1[CCDC_DFT_TABLE_SIZE];
unsigned int dft_corr_sub2[CCDC_DFT_TABLE_SIZE];
unsigned int dft_corr_sub3[CCDC_DFT_TABLE_SIZE];
};
struct ccdc_data_offset {
unsigned char horz_offset;
unsigned char vert_offset;
};
/*
* Structure for CCDC configuration parameters for raw capture mode passed
* by application
*/
struct ccdc_config_params_raw {
/* data shift to be applied before storing */
enum ccdc_datasft datasft;
/* data size value from 8 to 16 bits */
enum ccdc_data_size data_sz;
/* median filter for sdram */
enum ccdc_mfilt1 mfilt1;
enum ccdc_mfilt2 mfilt2;
/* low pass filter enable/disable */
unsigned char lpf_enable;
/* Threshold of median filter */
int med_filt_thres;
/*
* horz and vertical data offset. Applicable for defect correction
* and lsc
*/
struct ccdc_data_offset data_offset;
/* Structure for Optional A-Law */
struct ccdc_a_law alaw;
/* Structure for Optical Black Clamp */
struct ccdc_black_clamp blk_clamp;
/* Structure for Black Compensation */
struct ccdc_black_compensation blk_comp;
/* structure for vertical Defect Correction Module Configuration */
struct ccdc_vertical_dft vertical_dft;
/* structure for color space converter Module Configuration */
struct ccdc_csc csc;
/* color patters for bayer capture */
struct ccdc_col_pat col_pat_field0;
struct ccdc_col_pat col_pat_field1;
};
#ifdef __KERNEL__
#include <linux/io.h>
#define CCDC_WIN_PAL {0, 0, 720, 576}
#define CCDC_WIN_VGA {0, 0, 640, 480}
struct ccdc_params_ycbcr {
/* pixel format */
enum ccdc_pixfmt pix_fmt;
/* progressive or interlaced frame */
enum ccdc_frmfmt frm_fmt;
/* video window */
struct v4l2_rect win;
/* field id polarity */
enum vpfe_pin_pol fid_pol;
/* vertical sync polarity */
enum vpfe_pin_pol vd_pol;
/* horizontal sync polarity */
enum vpfe_pin_pol hd_pol;
/* enable BT.656 embedded sync mode */
int bt656_enable;
/* cb:y:cr:y or y:cb:y:cr in memory */
enum ccdc_pixorder pix_order;
/* interleaved or separated fields */
enum ccdc_buftype buf_type;
};
/* Gain applied to Raw Bayer data */
struct ccdc_gain {
unsigned short r_ye;
unsigned short gr_cy;
unsigned short gb_g;
unsigned short b_mg;
};
/* Structure for CCDC configuration parameters for raw capture mode */
struct ccdc_params_raw {
/* pixel format */
enum ccdc_pixfmt pix_fmt;
/* progressive or interlaced frame */
enum ccdc_frmfmt frm_fmt;
/* video window */
struct v4l2_rect win;
/* field id polarity */
enum vpfe_pin_pol fid_pol;
/* vertical sync polarity */
enum vpfe_pin_pol vd_pol;
/* horizontal sync polarity */
enum vpfe_pin_pol hd_pol;
/* interleaved or separated fields */
enum ccdc_buftype buf_type;
/* Gain values */
struct ccdc_gain gain;
/* offset */
unsigned int ccdc_offset;
/* horizontal flip enable */
unsigned char horz_flip_enable;
/*
* enable to store the image in inverse order in memory
* (bottom to top)
*/
unsigned char image_invert_enable;
/* Configurable part of raw data */
struct ccdc_config_params_raw config_params;
};
#endif
#endif /* DM355_CCDC_H */
drivers/staging/media/deprecated/vpfe_capture/dm355_ccdc_regs.h deleted 100644 → 0
View file @ 3673237b
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2005-2009 Texas Instruments Inc
*/
#ifndef _DM355_CCDC_REGS_H
#define _DM355_CCDC_REGS_H
/**************************************************************************\
* Register OFFSET Definitions
\**************************************************************************/
#define SYNCEN 0x00
#define MODESET 0x04
#define HDWIDTH 0x08
#define VDWIDTH 0x0c
#define PPLN 0x10
#define LPFR 0x14
#define SPH 0x18
#define NPH 0x1c
#define SLV0 0x20
#define SLV1 0x24
#define NLV 0x28
#define CULH 0x2c
#define CULV 0x30
#define HSIZE 0x34
#define SDOFST 0x38
#define STADRH 0x3c
#define STADRL 0x40
#define CLAMP 0x44
#define DCSUB 0x48
#define COLPTN 0x4c
#define BLKCMP0 0x50
#define BLKCMP1 0x54
#define MEDFILT 0x58
#define RYEGAIN 0x5c
#define GRCYGAIN 0x60
#define GBGGAIN 0x64
#define BMGGAIN 0x68
#define OFFSET 0x6c
#define OUTCLIP 0x70
#define VDINT0 0x74
#define VDINT1 0x78
#define RSV0 0x7c
#define GAMMAWD 0x80
#define REC656IF 0x84
#define CCDCFG 0x88
#define FMTCFG 0x8c
#define FMTPLEN 0x90
#define FMTSPH 0x94
#define FMTLNH 0x98
#define FMTSLV 0x9c
#define FMTLNV 0xa0
#define FMTRLEN 0xa4
#define FMTHCNT 0xa8
#define FMT_ADDR_PTR_B 0xac
#define FMT_ADDR_PTR(i) (FMT_ADDR_PTR_B + (i * 4))
#define FMTPGM_VF0 0xcc
#define FMTPGM_VF1 0xd0
#define FMTPGM_AP0 0xd4
#define FMTPGM_AP1 0xd8
#define FMTPGM_AP2 0xdc
#define FMTPGM_AP3 0xe0
#define FMTPGM_AP4 0xe4
#define FMTPGM_AP5 0xe8
#define FMTPGM_AP6 0xec
#define FMTPGM_AP7 0xf0
#define LSCCFG1 0xf4
#define LSCCFG2 0xf8
#define LSCH0 0xfc
#define LSCV0 0x100
#define LSCKH 0x104
#define LSCKV 0x108
#define LSCMEMCTL 0x10c
#define LSCMEMD 0x110
#define LSCMEMQ 0x114
#define DFCCTL 0x118
#define DFCVSAT 0x11c
#define DFCMEMCTL 0x120
#define DFCMEM0 0x124
#define DFCMEM1 0x128
#define DFCMEM2 0x12c
#define DFCMEM3 0x130
#define DFCMEM4 0x134
#define CSCCTL 0x138
#define CSCM0 0x13c
#define CSCM1 0x140
#define CSCM2 0x144
#define CSCM3 0x148
#define CSCM4 0x14c
#define CSCM5 0x150
#define CSCM6 0x154
#define CSCM7 0x158
#define DATAOFST 0x15c
#define CCDC_REG_LAST DATAOFST
/**************************************************************
* Define for various register bit mask and shifts for CCDC
*
**************************************************************/
#define CCDC_RAW_IP_MODE 0
#define CCDC_VDHDOUT_INPUT 0
#define CCDC_YCINSWP_RAW (0 << 4)
#define CCDC_EXWEN_DISABLE 0
#define CCDC_DATAPOL_NORMAL 0
#define CCDC_CCDCFG_FIDMD_LATCH_VSYNC 0
#define CCDC_CCDCFG_FIDMD_NO_LATCH_VSYNC (1 << 6)
#define CCDC_CCDCFG_WENLOG_AND 0
#define CCDC_CCDCFG_TRGSEL_WEN 0
#define CCDC_CCDCFG_EXTRG_DISABLE 0
#define CCDC_CFA_MOSAIC 0
#define CCDC_Y8POS_SHIFT 11
#define CCDC_VDC_DFCVSAT_MASK 0x3fff
#define CCDC_DATAOFST_MASK 0x0ff
#define CCDC_DATAOFST_H_SHIFT 0
#define CCDC_DATAOFST_V_SHIFT 8
#define CCDC_GAMMAWD_CFA_MASK 1
#define CCDC_GAMMAWD_CFA_SHIFT 5
#define CCDC_GAMMAWD_INPUT_SHIFT 2
#define CCDC_FID_POL_MASK 1
#define CCDC_FID_POL_SHIFT 4
#define CCDC_HD_POL_MASK 1
#define CCDC_HD_POL_SHIFT 3
#define CCDC_VD_POL_MASK 1
#define CCDC_VD_POL_SHIFT 2
#define CCDC_VD_POL_NEGATIVE (1 << 2)
#define CCDC_FRM_FMT_MASK 1
#define CCDC_FRM_FMT_SHIFT 7
#define CCDC_DATA_SZ_MASK 7
#define CCDC_DATA_SZ_SHIFT 8
#define CCDC_VDHDOUT_MASK 1
#define CCDC_VDHDOUT_SHIFT 0
#define CCDC_EXWEN_MASK 1
#define CCDC_EXWEN_SHIFT 5
#define CCDC_INPUT_MODE_MASK 3
#define CCDC_INPUT_MODE_SHIFT 12
#define CCDC_PIX_FMT_MASK 3
#define CCDC_PIX_FMT_SHIFT 12
#define CCDC_DATAPOL_MASK 1
#define CCDC_DATAPOL_SHIFT 6
#define CCDC_WEN_ENABLE (1 << 1)
#define CCDC_VDHDEN_ENABLE (1 << 16)
#define CCDC_LPF_ENABLE (1 << 14)
#define CCDC_ALAW_ENABLE 1
#define CCDC_ALAW_GAMMA_WD_MASK 7
#define CCDC_REC656IF_BT656_EN 3
#define CCDC_FMTCFG_FMTMODE_MASK 3
#define CCDC_FMTCFG_FMTMODE_SHIFT 1
#define CCDC_FMTCFG_LNUM_MASK 3
#define CCDC_FMTCFG_LNUM_SHIFT 4
#define CCDC_FMTCFG_ADDRINC_MASK 7
#define CCDC_FMTCFG_ADDRINC_SHIFT 8
#define CCDC_CCDCFG_FIDMD_SHIFT 6
#define CCDC_CCDCFG_WENLOG_SHIFT 8
#define CCDC_CCDCFG_TRGSEL_SHIFT 9
#define CCDC_CCDCFG_EXTRG_SHIFT 10
#define CCDC_CCDCFG_MSBINVI_SHIFT 13
#define CCDC_HSIZE_FLIP_SHIFT 12
#define CCDC_HSIZE_FLIP_MASK 1
#define CCDC_HSIZE_VAL_MASK 0xFFF
#define CCDC_SDOFST_FIELD_INTERLEAVED 0x249
#define CCDC_SDOFST_INTERLACE_INVERSE 0x4B6D
#define CCDC_SDOFST_INTERLACE_NORMAL 0x0B6D
#define CCDC_SDOFST_PROGRESSIVE_INVERSE 0x4000
#define CCDC_SDOFST_PROGRESSIVE_NORMAL 0
#define CCDC_START_PX_HOR_MASK 0x7FFF
#define CCDC_NUM_PX_HOR_MASK 0x7FFF
#define CCDC_START_VER_ONE_MASK 0x7FFF
#define CCDC_START_VER_TWO_MASK 0x7FFF
#define CCDC_NUM_LINES_VER 0x7FFF
#define CCDC_BLK_CLAMP_ENABLE (1 << 15)
#define CCDC_BLK_SGAIN_MASK 0x1F
#define CCDC_BLK_ST_PXL_MASK 0x1FFF
#define CCDC_BLK_SAMPLE_LN_MASK 3
#define CCDC_BLK_SAMPLE_LN_SHIFT 13
#define CCDC_NUM_LINE_CALC_MASK 3
#define CCDC_NUM_LINE_CALC_SHIFT 14
#define CCDC_BLK_DC_SUB_MASK 0x3FFF
#define CCDC_BLK_COMP_MASK 0xFF
#define CCDC_BLK_COMP_GB_COMP_SHIFT 8
#define CCDC_BLK_COMP_GR_COMP_SHIFT 0
#define CCDC_BLK_COMP_R_COMP_SHIFT 8
#define CCDC_LATCH_ON_VSYNC_DISABLE (1 << 15)
#define CCDC_LATCH_ON_VSYNC_ENABLE (0 << 15)
#define CCDC_FPC_ENABLE (1 << 15)
#define CCDC_FPC_FPC_NUM_MASK 0x7FFF
#define CCDC_DATA_PACK_ENABLE (1 << 11)
#define CCDC_FMT_HORZ_FMTLNH_MASK 0x1FFF
#define CCDC_FMT_HORZ_FMTSPH_MASK 0x1FFF
#define CCDC_FMT_HORZ_FMTSPH_SHIFT 16
#define CCDC_FMT_VERT_FMTLNV_MASK 0x1FFF
#define CCDC_FMT_VERT_FMTSLV_MASK 0x1FFF
#define CCDC_FMT_VERT_FMTSLV_SHIFT 16
#define CCDC_VP_OUT_VERT_NUM_MASK 0x3FFF
#define CCDC_VP_OUT_VERT_NUM_SHIFT 17
#define CCDC_VP_OUT_HORZ_NUM_MASK 0x1FFF
#define CCDC_VP_OUT_HORZ_NUM_SHIFT 4
#define CCDC_VP_OUT_HORZ_ST_MASK 0xF
#define CCDC_CSC_COEF_INTEG_MASK 7
#define CCDC_CSC_COEF_DECIMAL_MASK 0x1f
#define CCDC_CSC_COEF_INTEG_SHIFT 5
#define CCDC_CSCM_MSB_SHIFT 8
#define CCDC_CSC_ENABLE 1
#define CCDC_CSC_DEC_MAX 32
#define CCDC_MFILT1_SHIFT 10
#define CCDC_MFILT2_SHIFT 8
#define CCDC_MED_FILT_THRESH 0x3FFF
#define CCDC_LPF_MASK 1
#define CCDC_LPF_SHIFT 14
#define CCDC_OFFSET_MASK 0x3FF
#define CCDC_DATASFT_MASK 7
#define CCDC_DATASFT_SHIFT 8
#define CCDC_DF_ENABLE 1
#define CCDC_FMTPLEN_P0_MASK 0xF
#define CCDC_FMTPLEN_P1_MASK 0xF
#define CCDC_FMTPLEN_P2_MASK 7
#define CCDC_FMTPLEN_P3_MASK 7
#define CCDC_FMTPLEN_P0_SHIFT 0
#define CCDC_FMTPLEN_P1_SHIFT 4
#define CCDC_FMTPLEN_P2_SHIFT 8
#define CCDC_FMTPLEN_P3_SHIFT 12
#define CCDC_FMTSPH_MASK 0x1FFF
#define CCDC_FMTLNH_MASK 0x1FFF
#define CCDC_FMTSLV_MASK 0x1FFF
#define CCDC_FMTLNV_MASK 0x7FFF
#define CCDC_FMTRLEN_MASK 0x1FFF
#define CCDC_FMTHCNT_MASK 0x1FFF
#define CCDC_ADP_INIT_MASK 0x1FFF
#define CCDC_ADP_LINE_SHIFT 13
#define CCDC_ADP_LINE_MASK 3
#define CCDC_FMTPGN_APTR_MASK 7
#define CCDC_DFCCTL_GDFCEN_MASK 1
#define CCDC_DFCCTL_VDFCEN_MASK 1
#define CCDC_DFCCTL_VDFC_DISABLE (0 << 4)
#define CCDC_DFCCTL_VDFCEN_SHIFT 4
#define CCDC_DFCCTL_VDFCSL_MASK 3
#define CCDC_DFCCTL_VDFCSL_SHIFT 5
#define CCDC_DFCCTL_VDFCUDA_MASK 1
#define CCDC_DFCCTL_VDFCUDA_SHIFT 7
#define CCDC_DFCCTL_VDFLSFT_MASK 3
#define CCDC_DFCCTL_VDFLSFT_SHIFT 8
#define CCDC_DFCMEMCTL_DFCMARST_MASK 1
#define CCDC_DFCMEMCTL_DFCMARST_SHIFT 2
#define CCDC_DFCMEMCTL_DFCMWR_MASK 1
#define CCDC_DFCMEMCTL_DFCMWR_SHIFT 0
#define CCDC_DFCMEMCTL_INC_ADDR (0 << 2)
#define CCDC_LSCCFG_GFTSF_MASK 7
#define CCDC_LSCCFG_GFTSF_SHIFT 1
#define CCDC_LSCCFG_GFTINV_MASK 0xf
#define CCDC_LSCCFG_GFTINV_SHIFT 4
#define CCDC_LSC_GFTABLE_SEL_MASK 3
#define CCDC_LSC_GFTABLE_EPEL_SHIFT 8
#define CCDC_LSC_GFTABLE_OPEL_SHIFT 10
#define CCDC_LSC_GFTABLE_EPOL_SHIFT 12
#define CCDC_LSC_GFTABLE_OPOL_SHIFT 14
#define CCDC_LSC_GFMODE_MASK 3
#define CCDC_LSC_GFMODE_SHIFT 4
#define CCDC_LSC_DISABLE 0
#define CCDC_LSC_ENABLE 1
#define CCDC_LSC_TABLE1_SLC 0
#define CCDC_LSC_TABLE2_SLC 1
#define CCDC_LSC_TABLE3_SLC 2
#define CCDC_LSC_MEMADDR_RESET (1 << 2)
#define CCDC_LSC_MEMADDR_INCR (0 << 2)
#define CCDC_LSC_FRAC_MASK_T1 0xFF
#define CCDC_LSC_INT_MASK 3
#define CCDC_LSC_FRAC_MASK 0x3FFF
#define CCDC_LSC_CENTRE_MASK 0x3FFF
#define CCDC_LSC_COEF_MASK 0xff
#define CCDC_LSC_COEFL_SHIFT 0
#define CCDC_LSC_COEFU_SHIFT 8
#define CCDC_GAIN_MASK 0x7FF
#define CCDC_SYNCEN_VDHDEN_MASK (1 << 0)
#define CCDC_SYNCEN_WEN_MASK (1 << 1)
#define CCDC_SYNCEN_WEN_SHIFT 1
/* Power on Defaults in hardware */
#define MODESET_DEFAULT 0x200
#define CULH_DEFAULT 0xFFFF
#define CULV_DEFAULT 0xFF
#define GAIN_DEFAULT 256
#define OUTCLIP_DEFAULT 0x3FFF
#define LSCCFG2_DEFAULT 0xE
#endif
drivers/staging/media/deprecated/vpfe_capture/dm644x_ccdc.h deleted 100644 → 0
View file @ 3673237b
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2006-2009 Texas Instruments Inc
*/
#ifndef _DM644X_CCDC_H
#define _DM644X_CCDC_H
#include <media/davinci/ccdc_types.h>
#include <media/davinci/vpfe_types.h>
/* enum for No of pixel per line to be avg. in Black Clamping*/
enum ccdc_sample_length {
CCDC_SAMPLE_1PIXELS,
CCDC_SAMPLE_2PIXELS,
CCDC_SAMPLE_4PIXELS,
CCDC_SAMPLE_8PIXELS,
CCDC_SAMPLE_16PIXELS
};
/* enum for No of lines in Black Clamping */
enum ccdc_sample_line {
CCDC_SAMPLE_1LINES,
CCDC_SAMPLE_2LINES,
CCDC_SAMPLE_4LINES,
CCDC_SAMPLE_8LINES,
CCDC_SAMPLE_16LINES
};
/* enum for Alaw gamma width */
enum ccdc_gamma_width {
CCDC_GAMMA_BITS_15_6, /* use bits 15-6 for gamma */
CCDC_GAMMA_BITS_14_5,
CCDC_GAMMA_BITS_13_4,
CCDC_GAMMA_BITS_12_3,
CCDC_GAMMA_BITS_11_2,
CCDC_GAMMA_BITS_10_1,
CCDC_GAMMA_BITS_09_0 /* use bits 9-0 for gamma */
};
/* returns the highest bit used for the gamma */
static inline u8 ccdc_gamma_width_max_bit(enum ccdc_gamma_width width)
{
return 15 - width;
}
enum ccdc_data_size {
CCDC_DATA_16BITS,
CCDC_DATA_15BITS,
CCDC_DATA_14BITS,
CCDC_DATA_13BITS,
CCDC_DATA_12BITS,
CCDC_DATA_11BITS,
CCDC_DATA_10BITS,
CCDC_DATA_8BITS
};
/* returns the highest bit used for this data size */
static inline u8 ccdc_data_size_max_bit(enum ccdc_data_size sz)
{
return sz == CCDC_DATA_8BITS ? 7 : 15 - sz;
}
/* structure for ALaw */
struct ccdc_a_law {
/* Enable/disable A-Law */
unsigned char enable;
/* Gamma Width Input */
enum ccdc_gamma_width gamma_wd;
};
/* structure for Black Clamping */
struct ccdc_black_clamp {
unsigned char enable;
/* only if bClampEnable is TRUE */
enum ccdc_sample_length sample_pixel;
/* only if bClampEnable is TRUE */
enum ccdc_sample_line sample_ln;
/* only if bClampEnable is TRUE */
unsigned short start_pixel;
/* only if bClampEnable is TRUE */
unsigned short sgain;
/* only if bClampEnable is FALSE */
unsigned short dc_sub;
};
/* structure for Black Level Compensation */
struct ccdc_black_compensation {
/* Constant value to subtract from Red component */
char r;
/* Constant value to subtract from Gr component */
char gr;
/* Constant value to subtract from Blue component */
char b;
/* Constant value to subtract from Gb component */
char gb;
};
/* Structure for CCDC configuration parameters for raw capture mode passed
* by application
*/
struct ccdc_config_params_raw {
/* data size value from 8 to 16 bits */
enum ccdc_data_size data_sz;
/* Structure for Optional A-Law */
struct ccdc_a_law alaw;
/* Structure for Optical Black Clamp */
struct ccdc_black_clamp blk_clamp;
/* Structure for Black Compensation */
struct ccdc_black_compensation blk_comp;
};
#ifdef __KERNEL__
#include <linux/io.h>
/* Define to enable/disable video port */
#define FP_NUM_BYTES 4
/* Define for extra pixel/line and extra lines/frame */
#define NUM_EXTRAPIXELS 8
#define NUM_EXTRALINES 8
/* settings for commonly used video formats */
#define CCDC_WIN_PAL {0, 0, 720, 576}
/* ntsc square pixel */
#define CCDC_WIN_VGA {0, 0, (640 + NUM_EXTRAPIXELS), (480 + NUM_EXTRALINES)}
/* Structure for CCDC configuration parameters for raw capture mode */
struct ccdc_params_raw {
/* pixel format */
enum ccdc_pixfmt pix_fmt;
/* progressive or interlaced frame */
enum ccdc_frmfmt frm_fmt;
/* video window */
struct v4l2_rect win;
/* field id polarity */
enum vpfe_pin_pol fid_pol;
/* vertical sync polarity */
enum vpfe_pin_pol vd_pol;
/* horizontal sync polarity */
enum vpfe_pin_pol hd_pol;
/* interleaved or separated fields */
enum ccdc_buftype buf_type;
/*
* enable to store the image in inverse
* order in memory(bottom to top)
*/
unsigned char image_invert_enable;
/* configurable parameters */
struct ccdc_config_params_raw config_params;
};
struct ccdc_params_ycbcr {
/* pixel format */
enum ccdc_pixfmt pix_fmt;
/* progressive or interlaced frame */
enum ccdc_frmfmt frm_fmt;
/* video window */
struct v4l2_rect win;
/* field id polarity */
enum vpfe_pin_pol fid_pol;
/* vertical sync polarity */
enum vpfe_pin_pol vd_pol;
/* horizontal sync polarity */
enum vpfe_pin_pol hd_pol;
/* enable BT.656 embedded sync mode */
int bt656_enable;
/* cb:y:cr:y or y:cb:y:cr in memory */
enum ccdc_pixorder pix_order;
/* interleaved or separated fields */
enum ccdc_buftype buf_type;
};
#endif
#endif /* _DM644X_CCDC_H */
drivers/staging/media/deprecated/vpfe_capture/dm644x_ccdc_regs.h deleted 100644 → 0
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2006-2009 Texas Instruments Inc
*/
#ifndef _DM644X_CCDC_REGS_H
#define _DM644X_CCDC_REGS_H
/**************************************************************************\
* Register OFFSET Definitions
\**************************************************************************/
#define CCDC_PID 0x0
#define CCDC_PCR 0x4
#define CCDC_SYN_MODE 0x8
#define CCDC_HD_VD_WID 0xc
#define CCDC_PIX_LINES 0x10
#define CCDC_HORZ_INFO 0x14
#define CCDC_VERT_START 0x18
#define CCDC_VERT_LINES 0x1c
#define CCDC_CULLING 0x20
#define CCDC_HSIZE_OFF 0x24
#define CCDC_SDOFST 0x28
#define CCDC_SDR_ADDR 0x2c
#define CCDC_CLAMP 0x30
#define CCDC_DCSUB 0x34
#define CCDC_COLPTN 0x38
#define CCDC_BLKCMP 0x3c
#define CCDC_FPC 0x40
#define CCDC_FPC_ADDR 0x44
#define CCDC_VDINT 0x48
#define CCDC_ALAW 0x4c
#define CCDC_REC656IF 0x50
#define CCDC_CCDCFG 0x54
#define CCDC_FMTCFG 0x58
#define CCDC_FMT_HORZ 0x5c
#define CCDC_FMT_VERT 0x60
#define CCDC_FMT_ADDR0 0x64
#define CCDC_FMT_ADDR1 0x68
#define CCDC_FMT_ADDR2 0x6c
#define CCDC_FMT_ADDR3 0x70
#define CCDC_FMT_ADDR4 0x74
#define CCDC_FMT_ADDR5 0x78
#define CCDC_FMT_ADDR6 0x7c
#define CCDC_FMT_ADDR7 0x80
#define CCDC_PRGEVEN_0 0x84
#define CCDC_PRGEVEN_1 0x88
#define CCDC_PRGODD_0 0x8c
#define CCDC_PRGODD_1 0x90
#define CCDC_VP_OUT 0x94
#define CCDC_REG_END 0x98
/***************************************************************
* Define for various register bit mask and shifts for CCDC
****************************************************************/
#define CCDC_FID_POL_MASK 1
#define CCDC_FID_POL_SHIFT 4
#define CCDC_HD_POL_MASK 1
#define CCDC_HD_POL_SHIFT 3
#define CCDC_VD_POL_MASK 1
#define CCDC_VD_POL_SHIFT 2
#define CCDC_HSIZE_OFF_MASK 0xffffffe0
#define CCDC_32BYTE_ALIGN_VAL 31
#define CCDC_FRM_FMT_MASK 0x1
#define CCDC_FRM_FMT_SHIFT 7
#define CCDC_DATA_SZ_MASK 7
#define CCDC_DATA_SZ_SHIFT 8
#define CCDC_PIX_FMT_MASK 3
#define CCDC_PIX_FMT_SHIFT 12
#define CCDC_VP2SDR_DISABLE 0xFFFBFFFF
#define CCDC_WEN_ENABLE BIT(17)
#define CCDC_SDR2RSZ_DISABLE 0xFFF7FFFF
#define CCDC_VDHDEN_ENABLE BIT(16)
#define CCDC_LPF_ENABLE BIT(14)
#define CCDC_ALAW_ENABLE BIT(3)
#define CCDC_ALAW_GAMMA_WD_MASK 7
#define CCDC_BLK_CLAMP_ENABLE BIT(31)
#define CCDC_BLK_SGAIN_MASK 0x1F
#define CCDC_BLK_ST_PXL_MASK 0x7FFF
#define CCDC_BLK_ST_PXL_SHIFT 10
#define CCDC_BLK_SAMPLE_LN_MASK 7
#define CCDC_BLK_SAMPLE_LN_SHIFT 28
#define CCDC_BLK_SAMPLE_LINE_MASK 7
#define CCDC_BLK_SAMPLE_LINE_SHIFT 25
#define CCDC_BLK_DC_SUB_MASK 0x03FFF
#define CCDC_BLK_COMP_MASK 0xFF
#define CCDC_BLK_COMP_GB_COMP_SHIFT 8
#define CCDC_BLK_COMP_GR_COMP_SHIFT 16
#define CCDC_BLK_COMP_R_COMP_SHIFT 24
#define CCDC_LATCH_ON_VSYNC_DISABLE BIT(15)
#define CCDC_FPC_ENABLE BIT(15)
#define CCDC_FPC_DISABLE 0
#define CCDC_FPC_FPC_NUM_MASK 0x7FFF
#define CCDC_DATA_PACK_ENABLE BIT(11)
#define CCDC_FMTCFG_VPIN_MASK 7
#define CCDC_FMTCFG_VPIN_SHIFT 12
#define CCDC_FMT_HORZ_FMTLNH_MASK 0x1FFF
#define CCDC_FMT_HORZ_FMTSPH_MASK 0x1FFF
#define CCDC_FMT_HORZ_FMTSPH_SHIFT 16
#define CCDC_FMT_VERT_FMTLNV_MASK 0x1FFF
#define CCDC_FMT_VERT_FMTSLV_MASK 0x1FFF
#define CCDC_FMT_VERT_FMTSLV_SHIFT 16
#define CCDC_VP_OUT_VERT_NUM_MASK 0x3FFF
#define CCDC_VP_OUT_VERT_NUM_SHIFT 17
#define CCDC_VP_OUT_HORZ_NUM_MASK 0x1FFF
#define CCDC_VP_OUT_HORZ_NUM_SHIFT 4
#define CCDC_VP_OUT_HORZ_ST_MASK 0xF
#define CCDC_HORZ_INFO_SPH_SHIFT 16
#define CCDC_VERT_START_SLV0_SHIFT 16
#define CCDC_VDINT_VDINT0_SHIFT 16
#define CCDC_VDINT_VDINT1_MASK 0xFFFF
#define CCDC_PPC_RAW 1
#define CCDC_DCSUB_DEFAULT_VAL 0
#define CCDC_CLAMP_DEFAULT_VAL 0
#define CCDC_ENABLE_VIDEO_PORT 0x8000
#define CCDC_DISABLE_VIDEO_PORT 0
#define CCDC_COLPTN_VAL 0xBB11BB11
#define CCDC_TWO_BYTES_PER_PIXEL 2
#define CCDC_INTERLACED_IMAGE_INVERT 0x4B6D
#define CCDC_INTERLACED_NO_IMAGE_INVERT 0x0249
#define CCDC_PROGRESSIVE_IMAGE_INVERT 0x4000
#define CCDC_PROGRESSIVE_NO_IMAGE_INVERT 0
#define CCDC_INTERLACED_HEIGHT_SHIFT 1
#define CCDC_SYN_MODE_INPMOD_SHIFT 12
#define CCDC_SYN_MODE_INPMOD_MASK 3
#define CCDC_SYN_MODE_8BITS (7 << 8)
#define CCDC_SYN_MODE_10BITS (6 << 8)
#define CCDC_SYN_MODE_11BITS (5 << 8)
#define CCDC_SYN_MODE_12BITS (4 << 8)
#define CCDC_SYN_MODE_13BITS (3 << 8)
#define CCDC_SYN_MODE_14BITS (2 << 8)
#define CCDC_SYN_MODE_15BITS (1 << 8)
#define CCDC_SYN_MODE_16BITS (0 << 8)
#define CCDC_SYN_FLDMODE_MASK 1
#define CCDC_SYN_FLDMODE_SHIFT 7
#define CCDC_REC656IF_BT656_EN 3
#define CCDC_SYN_MODE_VD_POL_NEGATIVE BIT(2)
#define CCDC_CCDCFG_Y8POS_SHIFT 11
#define CCDC_CCDCFG_BW656_10BIT BIT(5)
#define CCDC_SDOFST_FIELD_INTERLEAVED 0x249
#define CCDC_NO_CULLING 0xffff00ff
#endif
drivers/staging/media/deprecated/vpfe_capture/isif.c deleted 100644 → 0
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drivers/staging/media/deprecated/vpfe_capture/isif.h deleted 100644 → 0
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drivers/staging/media/deprecated/vpfe_capture/isif_regs.h deleted 100644 → 0
View file @ 3673237b
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2008-2009 Texas Instruments Inc
*/
#ifndef _ISIF_REGS_H
#define _ISIF_REGS_H
/* ISIF registers relative offsets */
#define SYNCEN 0x00
#define MODESET 0x04
#define HDW 0x08
#define VDW 0x0c
#define PPLN 0x10
#define LPFR 0x14
#define SPH 0x18
#define LNH 0x1c
#define SLV0 0x20
#define SLV1 0x24
#define LNV 0x28
#define CULH 0x2c
#define CULV 0x30
#define HSIZE 0x34
#define SDOFST 0x38
#define CADU 0x3c
#define CADL 0x40
#define LINCFG0 0x44
#define LINCFG1 0x48
#define CCOLP 0x4c
#define CRGAIN 0x50
#define CGRGAIN 0x54
#define CGBGAIN 0x58
#define CBGAIN 0x5c
#define COFSTA 0x60
#define FLSHCFG0 0x64
#define FLSHCFG1 0x68
#define FLSHCFG2 0x6c
#define VDINT0 0x70
#define VDINT1 0x74
#define VDINT2 0x78
#define MISC 0x7c
#define CGAMMAWD 0x80
#define REC656IF 0x84
#define CCDCFG 0x88
/*****************************************************
* Defect Correction registers
*****************************************************/
#define DFCCTL 0x8c
#define VDFSATLV 0x90
#define DFCMEMCTL 0x94
#define DFCMEM0 0x98
#define DFCMEM1 0x9c
#define DFCMEM2 0xa0
#define DFCMEM3 0xa4
#define DFCMEM4 0xa8
/****************************************************
* Black Clamp registers
****************************************************/
#define CLAMPCFG 0xac
#define CLDCOFST 0xb0
#define CLSV 0xb4
#define CLHWIN0 0xb8
#define CLHWIN1 0xbc
#define CLHWIN2 0xc0
#define CLVRV 0xc4
#define CLVWIN0 0xc8
#define CLVWIN1 0xcc
#define CLVWIN2 0xd0
#define CLVWIN3 0xd4
/****************************************************
* Lense Shading Correction
****************************************************/
#define DATAHOFST 0xd8
#define DATAVOFST 0xdc
#define LSCHVAL 0xe0
#define LSCVVAL 0xe4
#define TWODLSCCFG 0xe8
#define TWODLSCOFST 0xec
#define TWODLSCINI 0xf0
#define TWODLSCGRBU 0xf4
#define TWODLSCGRBL 0xf8
#define TWODLSCGROF 0xfc
#define TWODLSCORBU 0x100
#define TWODLSCORBL 0x104
#define TWODLSCOROF 0x108
#define TWODLSCIRQEN 0x10c
#define TWODLSCIRQST 0x110
/****************************************************
* Data formatter
****************************************************/
#define FMTCFG 0x114
#define FMTPLEN 0x118
#define FMTSPH 0x11c
#define FMTLNH 0x120
#define FMTSLV 0x124
#define FMTLNV 0x128
#define FMTRLEN 0x12c
#define FMTHCNT 0x130
#define FMTAPTR_BASE 0x134
/* Below macro for addresses FMTAPTR0 - FMTAPTR15 */
#define FMTAPTR(i) (FMTAPTR_BASE + (i * 4))
#define FMTPGMVF0 0x174
#define FMTPGMVF1 0x178
#define FMTPGMAPU0 0x17c
#define FMTPGMAPU1 0x180
#define FMTPGMAPS0 0x184
#define FMTPGMAPS1 0x188
#define FMTPGMAPS2 0x18c
#define FMTPGMAPS3 0x190
#define FMTPGMAPS4 0x194
#define FMTPGMAPS5 0x198
#define FMTPGMAPS6 0x19c
#define FMTPGMAPS7 0x1a0
/************************************************
* Color Space Converter
************************************************/
#define CSCCTL 0x1a4
#define CSCM0 0x1a8
#define CSCM1 0x1ac
#define CSCM2 0x1b0
#define CSCM3 0x1b4
#define CSCM4 0x1b8
#define CSCM5 0x1bc
#define CSCM6 0x1c0
#define CSCM7 0x1c4
#define OBWIN0 0x1c8
#define OBWIN1 0x1cc
#define OBWIN2 0x1d0
#define OBWIN3 0x1d4
#define OBVAL0 0x1d8
#define OBVAL1 0x1dc
#define OBVAL2 0x1e0
#define OBVAL3 0x1e4
#define OBVAL4 0x1e8
#define OBVAL5 0x1ec
#define OBVAL6 0x1f0
#define OBVAL7 0x1f4
#define CLKCTL 0x1f8
/* Masks & Shifts below */
#define START_PX_HOR_MASK 0x7FFF
#define NUM_PX_HOR_MASK 0x7FFF
#define START_VER_ONE_MASK 0x7FFF
#define START_VER_TWO_MASK 0x7FFF
#define NUM_LINES_VER 0x7FFF
/* gain - offset masks */
#define GAIN_INTEGER_SHIFT 9
#define OFFSET_MASK 0xFFF
#define GAIN_SDRAM_EN_SHIFT 12
#define GAIN_IPIPE_EN_SHIFT 13
#define GAIN_H3A_EN_SHIFT 14
#define OFST_SDRAM_EN_SHIFT 8
#define OFST_IPIPE_EN_SHIFT 9
#define OFST_H3A_EN_SHIFT 10
#define GAIN_OFFSET_EN_MASK 0x7700
/* Culling */
#define CULL_PAT_EVEN_LINE_SHIFT 8
/* CCDCFG register */
#define ISIF_YCINSWP_RAW (0x00 << 4)
#define ISIF_YCINSWP_YCBCR (0x01 << 4)
#define ISIF_CCDCFG_FIDMD_LATCH_VSYNC (0x00 << 6)
#define ISIF_CCDCFG_WENLOG_AND (0x00 << 8)
#define ISIF_CCDCFG_TRGSEL_WEN (0x00 << 9)
#define ISIF_CCDCFG_EXTRG_DISABLE (0x00 << 10)
#define ISIF_LATCH_ON_VSYNC_DISABLE (0x01 << 15)
#define ISIF_LATCH_ON_VSYNC_ENABLE (0x00 << 15)
#define ISIF_DATA_PACK_MASK 3
#define ISIF_DATA_PACK16 0
#define ISIF_DATA_PACK12 1
#define ISIF_DATA_PACK8 2
#define ISIF_PIX_ORDER_SHIFT 11
#define ISIF_BW656_ENABLE (0x01 << 5)
/* MODESET registers */
#define ISIF_VDHDOUT_INPUT (0x00 << 0)
#define ISIF_INPUT_SHIFT 12
#define ISIF_RAW_INPUT_MODE 0
#define ISIF_FID_POL_SHIFT 4
#define ISIF_HD_POL_SHIFT 3
#define ISIF_VD_POL_SHIFT 2
#define ISIF_DATAPOL_NORMAL 0
#define ISIF_DATAPOL_SHIFT 6
#define ISIF_EXWEN_DISABLE 0
#define ISIF_EXWEN_SHIFT 5
#define ISIF_FRM_FMT_SHIFT 7
#define ISIF_DATASFT_SHIFT 8
#define ISIF_LPF_SHIFT 14
#define ISIF_LPF_MASK 1
/* GAMMAWD registers */
#define ISIF_ALAW_GAMMA_WD_MASK 0xF
#define ISIF_ALAW_GAMMA_WD_SHIFT 1
#define ISIF_ALAW_ENABLE 1
#define ISIF_GAMMAWD_CFA_SHIFT 5
/* HSIZE registers */
#define ISIF_HSIZE_FLIP_MASK 1
#define ISIF_HSIZE_FLIP_SHIFT 12
/* MISC registers */
#define ISIF_DPCM_EN_SHIFT 12
#define ISIF_DPCM_PREDICTOR_SHIFT 13
/* Black clamp related */
#define ISIF_BC_MODE_COLOR_SHIFT 4
#define ISIF_HORZ_BC_MODE_SHIFT 1
#define ISIF_HORZ_BC_WIN_SEL_SHIFT 5
#define ISIF_HORZ_BC_PIX_LIMIT_SHIFT 6
#define ISIF_HORZ_BC_WIN_H_SIZE_SHIFT 8
#define ISIF_HORZ_BC_WIN_V_SIZE_SHIFT 12
#define ISIF_VERT_BC_RST_VAL_SEL_SHIFT 4
#define ISIF_VERT_BC_LINE_AVE_COEF_SHIFT 8
/* VDFC registers */
#define ISIF_VDFC_EN_SHIFT 4
#define ISIF_VDFC_CORR_MOD_SHIFT 5
#define ISIF_VDFC_CORR_WHOLE_LN_SHIFT 7
#define ISIF_VDFC_LEVEL_SHFT_SHIFT 8
#define ISIF_VDFC_POS_MASK 0x1FFF
#define ISIF_DFCMEMCTL_DFCMARST_SHIFT 2
/* CSC registers */
#define ISIF_CSC_COEF_INTEG_MASK 7
#define ISIF_CSC_COEF_DECIMAL_MASK 0x1f
#define ISIF_CSC_COEF_INTEG_SHIFT 5
#define ISIF_CSCM_MSB_SHIFT 8
#define ISIF_DF_CSC_SPH_MASK 0x1FFF
#define ISIF_DF_CSC_LNH_MASK 0x1FFF
#define ISIF_DF_CSC_SLV_MASK 0x1FFF
#define ISIF_DF_CSC_LNV_MASK 0x1FFF
#define ISIF_DF_NUMLINES 0x7FFF
#define ISIF_DF_NUMPIX 0x1FFF
/* Offsets for LSC/DFC/Gain */
#define ISIF_DATA_H_OFFSET_MASK 0x1FFF
#define ISIF_DATA_V_OFFSET_MASK 0x1FFF
/* Linearization */
#define ISIF_LIN_CORRSFT_SHIFT 4
#define ISIF_LIN_SCALE_FACT_INTEG_SHIFT 10
/* Pattern registers */
#define ISIF_PG_EN (1 << 3)
#define ISIF_SEL_PG_SRC (3 << 4)
#define ISIF_PG_VD_POL_SHIFT 0
#define ISIF_PG_HD_POL_SHIFT 1
/*random other junk*/
#define ISIF_SYNCEN_VDHDEN_MASK (1 << 0)
#define ISIF_SYNCEN_WEN_MASK (1 << 1)
#define ISIF_SYNCEN_WEN_SHIFT 1
#endif
include/media/davinci/ccdc_types.h deleted 100644 → 0
View file @ 3673237b
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2008-2009 Texas Instruments Inc
*
**************************************************************************/
#ifndef _CCDC_TYPES_H
#define _CCDC_TYPES_H
enum ccdc_pixfmt {
CCDC_PIXFMT_RAW,
CCDC_PIXFMT_YCBCR_16BIT,
CCDC_PIXFMT_YCBCR_8BIT
};
enum ccdc_frmfmt {
CCDC_FRMFMT_PROGRESSIVE,
CCDC_FRMFMT_INTERLACED
};
/* PIXEL ORDER IN MEMORY from LSB to MSB */
/* only applicable for 8-bit input mode */
enum ccdc_pixorder {
CCDC_PIXORDER_YCBYCR,
CCDC_PIXORDER_CBYCRY,
};
enum ccdc_buftype {
CCDC_BUFTYPE_FLD_INTERLEAVED,
CCDC_BUFTYPE_FLD_SEPARATED
};
#endif
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