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Commit d2f1000c authored by Bjorn Helgaas's avatar Bjorn Helgaas Committed by Greg Kroah-Hartman
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net/mlx4_core: Use device ID defines 

[ Upstream commit c19e4b90 ]

We added a bunch of new Mellanox device ID definitions because they'll be
used by INTx quirks.  Use them in the mlx4 ID table also so grep can find
both places.  No functional change intended.
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Acked-by: default avatarTariq Toukan <tariqt@mellanox.com>
Signed-off-by: default avatarSasha Levin <alexander.levin@verizon.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent dcc4c675
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Showing with 43 additions and 41 deletions
drivers/net/ethernet/mellanox/mlx4/main.c
View file @ d2f1000c
...@@ -4020,49 +4020,51 @@ int mlx4_restart_one(struct pci_dev *pdev) ...@@ -4020,49 +4020,51 @@ int mlx4_restart_one(struct pci_dev *pdev)
return err; return err;
} }
#define MLX_SP(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_FORCE_SENSE_PORT }
#define MLX_VF(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_IS_VF }
#define MLX_GN(id) { PCI_VDEVICE(MELLANOX, id), 0 }
static const struct pci_device_id mlx4_pci_table[] = { static const struct pci_device_id mlx4_pci_table[] = {
/* MT25408 "Hermon" SDR */ /* MT25408 "Hermon" */
{ PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT }, MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_SDR), /* SDR */
/* MT25408 "Hermon" DDR */ MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR), /* DDR */
{ PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT }, MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR), /* QDR */
/* MT25408 "Hermon" QDR */ MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2), /* DDR Gen2 */
{ PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT }, MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2), /* QDR Gen2 */
/* MT25408 "Hermon" DDR PCIe gen2 */ MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN), /* EN 10GigE */
{ PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT }, MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2), /* EN 10GigE Gen2 */
/* MT25408 "Hermon" QDR PCIe gen2 */ /* MT25458 ConnectX EN 10GBASE-T */
{ PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT }, MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN),
/* MT25408 "Hermon" EN 10GigE */ MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2), /* Gen2 */
{ PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT }, /* MT26468 ConnectX EN 10GigE PCIe Gen2*/
/* MT25408 "Hermon" EN 10GigE PCIe gen2 */ MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2),
{ PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT }, /* MT26438 ConnectX EN 40GigE PCIe Gen2 5GT/s */
/* MT25458 ConnectX EN 10GBASE-T 10GigE */ MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2),
{ PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT }, /* MT26478 ConnectX2 40GigE PCIe Gen2 */
/* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */ MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX2),
{ PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT }, /* MT25400 Family [ConnectX-2] */
/* MT26468 ConnectX EN 10GigE PCIe gen2*/ MLX_VF(0x1002), /* Virtual Function */
{ PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
/* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
{ PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
/* MT26478 ConnectX2 40GigE PCIe gen2 */
{ PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
/* MT25400 Family [ConnectX-2 Virtual Function] */
{ PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
/* MT27500 Family [ConnectX-3] */ /* MT27500 Family [ConnectX-3] */
{ PCI_VDEVICE(MELLANOX, 0x1003), 0 }, MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3),
/* MT27500 Family [ConnectX-3 Virtual Function] */ MLX_VF(0x1004), /* Virtual Function */
{ PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF }, MLX_GN(0x1005), /* MT27510 Family */
{ PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */ MLX_GN(0x1006), /* MT27511 Family */
{ PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */ MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO), /* MT27520 Family */
{ PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */ MLX_GN(0x1008), /* MT27521 Family */
{ PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */ MLX_GN(0x1009), /* MT27530 Family */
{ PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */ MLX_GN(0x100a), /* MT27531 Family */
{ PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */ MLX_GN(0x100b), /* MT27540 Family */
{ PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */ MLX_GN(0x100c), /* MT27541 Family */
{ PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */ MLX_GN(0x100d), /* MT27550 Family */
{ PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */ MLX_GN(0x100e), /* MT27551 Family */
{ PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */ MLX_GN(0x100f), /* MT27560 Family */
{ PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */ MLX_GN(0x1010), /* MT27561 Family */
{ PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
/*
* See the mellanox_check_broken_intx_masking() quirk when
* adding devices
*/
{ 0, } { 0, }
}; };
......
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