Commit d411cf02 authored by Greentime Hu's avatar Greentime Hu Committed by Paul Walmsley

riscv: fix scratch register clearing in M-mode.

This patch fixes that the sscratch register clearing in M-mode. It cleared
sscratch register in M-mode, but it should clear mscratch register. That will
cause kernel trap if the CPU core doesn't support S-mode when trying to access
sscratch.

Fixes: 9e806356 ("riscv: clear the instruction cache and all registers when booting")
Signed-off-by: default avatarGreentime Hu <greentime.hu@sifive.com>
Reviewed-by: default avatarAnup Patel <anup@brainfault.org>
Signed-off-by: default avatarPaul Walmsley <paul.walmsley@sifive.com>
parent 0312a3d4
...@@ -246,7 +246,7 @@ ENTRY(reset_regs) ...@@ -246,7 +246,7 @@ ENTRY(reset_regs)
li t4, 0 li t4, 0
li t5, 0 li t5, 0
li t6, 0 li t6, 0
csrw sscratch, 0 csrw CSR_SCRATCH, 0
#ifdef CONFIG_FPU #ifdef CONFIG_FPU
csrr t0, CSR_MISA csrr t0, CSR_MISA
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment