Commit d5583d4f authored by Huang Rui's avatar Huang Rui Committed by Alex Deucher

drm/amdgpu: export mmhub set clockgating into gmc

Signed-off-by: default avatarHuang Rui <ray.huang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 77f6c763
...@@ -809,7 +809,9 @@ static int gmc_v9_0_soft_reset(void *handle) ...@@ -809,7 +809,9 @@ static int gmc_v9_0_soft_reset(void *handle)
static int gmc_v9_0_set_clockgating_state(void *handle, static int gmc_v9_0_set_clockgating_state(void *handle,
enum amd_clockgating_state state) enum amd_clockgating_state state)
{ {
return 0; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
return mmhub_v1_0_set_clockgating(adev, state);
} }
static int gmc_v9_0_set_powergating_state(void *handle, static int gmc_v9_0_set_powergating_state(void *handle,
......
...@@ -538,11 +538,9 @@ static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev, ...@@ -538,11 +538,9 @@ static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev,
WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATHUB_MISC_CNTL), data); WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATHUB_MISC_CNTL), data);
} }
static int mmhub_v1_0_set_clockgating_state(void *handle, int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
enum amd_clockgating_state state) enum amd_clockgating_state state)
{ {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (amdgpu_sriov_vf(adev)) if (amdgpu_sriov_vf(adev))
return 0; return 0;
...@@ -565,6 +563,12 @@ static int mmhub_v1_0_set_clockgating_state(void *handle, ...@@ -565,6 +563,12 @@ static int mmhub_v1_0_set_clockgating_state(void *handle,
return 0; return 0;
} }
static int mmhub_v1_0_set_clockgating_state(void *handle,
enum amd_clockgating_state state)
{
return 0;
}
static void mmhub_v1_0_get_clockgating_state(void *handle, u32 *flags) static void mmhub_v1_0_get_clockgating_state(void *handle, u32 *flags)
{ {
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
......
...@@ -29,6 +29,8 @@ void mmhub_v1_0_gart_disable(struct amdgpu_device *adev); ...@@ -29,6 +29,8 @@ void mmhub_v1_0_gart_disable(struct amdgpu_device *adev);
void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
bool value); bool value);
void mmhub_v1_0_init(struct amdgpu_device *adev); void mmhub_v1_0_init(struct amdgpu_device *adev);
int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
enum amd_clockgating_state state);
extern const struct amd_ip_funcs mmhub_v1_0_ip_funcs; extern const struct amd_ip_funcs mmhub_v1_0_ip_funcs;
extern const struct amdgpu_ip_block_version mmhub_v1_0_ip_block; extern const struct amdgpu_ip_block_version mmhub_v1_0_ip_block;
......
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