Commit d583804c authored by Shubhrajyoti Datta's avatar Shubhrajyoti Datta Committed by Stephen Boyd

clk: zynq: trivial warning fix

Fix the below warning

WARNING: Missing a blank line after declarations
+               int enable = !!(fclk_enable & BIT(i - fclk0));
+               zynq_clk_register_fclk(i, clk_output_name[i],
Signed-off-by: default avatarShubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Link: https://lore.kernel.org/r/20220222130903.17235-2-shubhrajyoti.datta@xilinx.comSigned-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent bb7f4b8c
...@@ -349,6 +349,7 @@ static void __init zynq_clk_setup(struct device_node *np) ...@@ -349,6 +349,7 @@ static void __init zynq_clk_setup(struct device_node *np)
/* Peripheral clocks */ /* Peripheral clocks */
for (i = fclk0; i <= fclk3; i++) { for (i = fclk0; i <= fclk3; i++) {
int enable = !!(fclk_enable & BIT(i - fclk0)); int enable = !!(fclk_enable & BIT(i - fclk0));
zynq_clk_register_fclk(i, clk_output_name[i], zynq_clk_register_fclk(i, clk_output_name[i],
SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0), SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0),
periph_parents, enable); periph_parents, enable);
......
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