Commit d642e4e7 authored by Paul Burton's avatar Paul Burton Committed by Ralf Baechle

MIPS: smp-cps: Clear Status IPL field when using EIC

When using an external interrupt controller (EIC) the interrupt mask
bits in the cop0 Status register are reused for the Interrupt Priority
Level, and any interrupts with a priority lower than the field will be
ignored. Clear the field to 0 by default such that all interrupts are
serviced.
Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Reviewed-by: default avatarMatt Redfearn <matt.redfearn@imgtec.com>
Tested-by: default avatarMatt Redfearn <matt.redfearn@imgtec.com>
Cc: Qais Yousef <qsyousef@gmail.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13273/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 640356a4
...@@ -359,8 +359,12 @@ static void cps_init_secondary(void) ...@@ -359,8 +359,12 @@ static void cps_init_secondary(void)
BUG_ON(ident != mips_cm_vp_id(smp_processor_id())); BUG_ON(ident != mips_cm_vp_id(smp_processor_id()));
} }
change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 | if (cpu_has_veic)
STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7); clear_c0_status(ST0_IM);
else
change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
STATUSF_IP4 | STATUSF_IP5 |
STATUSF_IP6 | STATUSF_IP7);
} }
static void cps_smp_finish(void) static void cps_smp_finish(void)
......
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