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Commit d742ea6b authored by Jakub Kicinski's avatar Jakub Kicinski
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Merge branch '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue 

Tony Nguyen says:

====================
Intel Wired LAN Driver Updates 2022-09-28 (ice)

Arkadiusz implements a single pin initialization function, checking feature
bits, instead of having separate device functions and updates sub-device
IDs for recognizing E810T devices.

Martyna adds support for switchdev filters on VLAN priority field.

* '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue:
  ice: Add support for VLAN priority filters in switchdev
  ice: support features on new E810T variants
  ice: Merge pin initialization of E810 and E810T adapters
====================

Link: https://lore.kernel.org/r/20220928203217.411078-1-anthony.l.nguyen@intel.comSigned-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents b5155ddd 34800178
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Showing with 93 additions and 58 deletions
drivers/net/ethernet/intel/ice/ice_common.c
View file @ d742ea6b
......@@ -182,9 +182,23 @@ bool ice_is_e810t(struct ice_hw *hw)
{
switch (hw->device_id) {
case ICE_DEV_ID_E810C_SFP:
if (hw->subsystem_device_id == ICE_SUBDEV_ID_E810T ||
hw->subsystem_device_id == ICE_SUBDEV_ID_E810T2)
switch (hw->subsystem_device_id) {
case ICE_SUBDEV_ID_E810T:
case ICE_SUBDEV_ID_E810T2:
case ICE_SUBDEV_ID_E810T3:
case ICE_SUBDEV_ID_E810T4:
case ICE_SUBDEV_ID_E810T6:
case ICE_SUBDEV_ID_E810T7:
return true;
}
break;
case ICE_DEV_ID_E810C_QSFP:
switch (hw->subsystem_device_id) {
case ICE_SUBDEV_ID_E810T2:
case ICE_SUBDEV_ID_E810T3:
case ICE_SUBDEV_ID_E810T5:
return true;
}
break;
default:
break;
......
drivers/net/ethernet/intel/ice/ice_devids.h
View file @ d742ea6b
......@@ -24,6 +24,11 @@
#define ICE_DEV_ID_E810C_SFP 0x1593
#define ICE_SUBDEV_ID_E810T 0x000E
#define ICE_SUBDEV_ID_E810T2 0x000F
#define ICE_SUBDEV_ID_E810T3 0x0010
#define ICE_SUBDEV_ID_E810T4 0x0011
#define ICE_SUBDEV_ID_E810T5 0x0012
#define ICE_SUBDEV_ID_E810T6 0x02E9
#define ICE_SUBDEV_ID_E810T7 0x02EA
/* Intel(R) Ethernet Controller E810-XXV for backplane */
#define ICE_DEV_ID_E810_XXV_BACKPLANE 0x1599
/* Intel(R) Ethernet Controller E810-XXV for QSFP */
......
drivers/net/ethernet/intel/ice/ice_ptp.c
View file @ d742ea6b
......@@ -2217,49 +2217,26 @@ ice_ptp_setup_sma_pins_e810t(struct ice_pf *pf, struct ptp_clock_info *info)
}
/**
* ice_ptp_setup_pins_e810t - Setup PTP pins in sysfs
* ice_ptp_setup_pins_e810 - Setup PTP pins in sysfs
* @pf: pointer to the PF instance
* @info: PTP clock capabilities
*/
static void
ice_ptp_setup_pins_e810t(struct ice_pf *pf, struct ptp_clock_info *info)
ice_ptp_setup_pins_e810(struct ice_pf *pf, struct ptp_clock_info *info)
{
/* Check if SMA controller is in the netlist */
if (ice_is_feature_supported(pf, ICE_F_SMA_CTRL) &&
!ice_is_pca9575_present(&pf->hw))
ice_clear_feature_support(pf, ICE_F_SMA_CTRL);
if (!ice_is_feature_supported(pf, ICE_F_SMA_CTRL)) {
info->n_ext_ts = N_EXT_TS_E810_NO_SMA;
info->n_per_out = N_PER_OUT_E810T_NO_SMA;
return;
}
info->n_per_out = N_PER_OUT_E810;
info->n_per_out = N_PER_OUT_E810T;
if (ice_is_feature_supported(pf, ICE_F_PTP_EXTTS))
info->n_ext_ts = N_EXT_TS_E810;
if (ice_is_feature_supported(pf, ICE_F_PTP_EXTTS)) {
if (ice_is_feature_supported(pf, ICE_F_SMA_CTRL)) {
info->n_ext_ts = N_EXT_TS_E810;
info->n_pins = NUM_PTP_PINS_E810T;
info->verify = ice_verify_pin_e810t;
}
/* Complete setup of the SMA pins */
ice_ptp_setup_sma_pins_e810t(pf, info);
}
/**
* ice_ptp_setup_pins_e810 - Setup PTP pins in sysfs
* @pf: pointer to the PF instance
* @info: PTP clock capabilities
*/
static void ice_ptp_setup_pins_e810(struct ice_pf *pf, struct ptp_clock_info *info)
{
info->n_per_out = N_PER_OUT_E810;
if (!ice_is_feature_supported(pf, ICE_F_PTP_EXTTS))
return;
info->n_ext_ts = N_EXT_TS_E810;
/* Complete setup of the SMA pins */
ice_ptp_setup_sma_pins_e810t(pf, info);
}
}
/**
......@@ -2296,11 +2273,7 @@ static void
ice_ptp_set_funcs_e810(struct ice_pf *pf, struct ptp_clock_info *info)
{
info->enable = ice_ptp_gpio_enable_e810;
if (ice_is_e810t(&pf->hw))
ice_ptp_setup_pins_e810t(pf, info);
else
ice_ptp_setup_pins_e810(pf, info);
ice_ptp_setup_pins_e810(pf, info);
}
/**
......
drivers/net/ethernet/intel/ice/ice_ptp.h
View file @ d742ea6b
......@@ -235,8 +235,8 @@ struct ice_ptp {
#define N_EXT_TS_E810 3
#define N_PER_OUT_E810 4
#define N_PER_OUT_E810T 3
#define N_PER_OUT_E810T_NO_SMA 2
#define N_EXT_TS_E810_NO_SMA 2
#define N_PER_OUT_NO_SMA_E810T 2
#define N_EXT_TS_NO_SMA_E810T 2
#define ETH_GLTSYN_ENA(_i) (0x03000348 + ((_i) * 4))
#if IS_ENABLED(CONFIG_PTP_1588_CLOCK)
......
drivers/net/ethernet/intel/ice/ice_tc_lib.c
View file @ d742ea6b
......@@ -51,11 +51,11 @@ ice_tc_count_lkups(u32 flags, struct ice_tc_flower_lyr_2_4_hdrs *headers,
lkups_cnt++;
/* is VLAN specified? */
if (flags & ICE_TC_FLWR_FIELD_VLAN)
if (flags & (ICE_TC_FLWR_FIELD_VLAN | ICE_TC_FLWR_FIELD_VLAN_PRIO))
lkups_cnt++;
/* is CVLAN specified? */
if (flags & ICE_TC_FLWR_FIELD_CVLAN)
if (flags & (ICE_TC_FLWR_FIELD_CVLAN | ICE_TC_FLWR_FIELD_CVLAN_PRIO))
lkups_cnt++;
/* are PPPoE options specified? */
......@@ -389,7 +389,7 @@ ice_tc_fill_rules(struct ice_hw *hw, u32 flags,
}
/* copy VLAN info */
if (flags & ICE_TC_FLWR_FIELD_VLAN) {
if (flags & (ICE_TC_FLWR_FIELD_VLAN | ICE_TC_FLWR_FIELD_VLAN_PRIO)) {
vlan_tpid = be16_to_cpu(headers->vlan_hdr.vlan_tpid);
rule_info->vlan_type =
ice_check_supported_vlan_tpid(vlan_tpid);
......@@ -398,15 +398,45 @@ ice_tc_fill_rules(struct ice_hw *hw, u32 flags,
list[i].type = ICE_VLAN_EX;
else
list[i].type = ICE_VLAN_OFOS;
list[i].h_u.vlan_hdr.vlan = headers->vlan_hdr.vlan_id;
list[i].m_u.vlan_hdr.vlan = cpu_to_be16(0xFFFF);
if (flags & ICE_TC_FLWR_FIELD_VLAN) {
list[i].h_u.vlan_hdr.vlan = headers->vlan_hdr.vlan_id;
list[i].m_u.vlan_hdr.vlan = cpu_to_be16(0x0FFF);
}
if (flags & ICE_TC_FLWR_FIELD_VLAN_PRIO) {
if (flags & ICE_TC_FLWR_FIELD_VLAN) {
list[i].m_u.vlan_hdr.vlan = cpu_to_be16(0xEFFF);
} else {
list[i].m_u.vlan_hdr.vlan = cpu_to_be16(0xE000);
list[i].h_u.vlan_hdr.vlan = 0;
}
list[i].h_u.vlan_hdr.vlan |=
headers->vlan_hdr.vlan_prio;
}
i++;
}
if (flags & ICE_TC_FLWR_FIELD_CVLAN) {
if (flags & (ICE_TC_FLWR_FIELD_CVLAN | ICE_TC_FLWR_FIELD_CVLAN_PRIO)) {
list[i].type = ICE_VLAN_IN;
list[i].h_u.vlan_hdr.vlan = headers->cvlan_hdr.vlan_id;
list[i].m_u.vlan_hdr.vlan = cpu_to_be16(0xFFFF);
if (flags & ICE_TC_FLWR_FIELD_CVLAN) {
list[i].h_u.vlan_hdr.vlan = headers->cvlan_hdr.vlan_id;
list[i].m_u.vlan_hdr.vlan = cpu_to_be16(0x0FFF);
}
if (flags & ICE_TC_FLWR_FIELD_CVLAN_PRIO) {
if (flags & ICE_TC_FLWR_FIELD_CVLAN) {
list[i].m_u.vlan_hdr.vlan = cpu_to_be16(0xEFFF);
} else {
list[i].m_u.vlan_hdr.vlan = cpu_to_be16(0xE000);
list[i].h_u.vlan_hdr.vlan = 0;
}
list[i].h_u.vlan_hdr.vlan |=
headers->cvlan_hdr.vlan_prio;
}
i++;
}
......@@ -1280,16 +1310,22 @@ ice_parse_cls_flower(struct net_device *filter_dev, struct ice_vsi *vsi,
if (match.mask->vlan_id) {
if (match.mask->vlan_id == VLAN_VID_MASK) {
fltr->flags |= ICE_TC_FLWR_FIELD_VLAN;
headers->vlan_hdr.vlan_id =
cpu_to_be16(match.key->vlan_id &
VLAN_VID_MASK);
} else {
NL_SET_ERR_MSG_MOD(fltr->extack, "Bad VLAN mask");
return -EINVAL;
}
}
headers->vlan_hdr.vlan_id =
cpu_to_be16(match.key->vlan_id & VLAN_VID_MASK);
if (match.mask->vlan_priority)
headers->vlan_hdr.vlan_prio = match.key->vlan_priority;
if (match.mask->vlan_priority) {
fltr->flags |= ICE_TC_FLWR_FIELD_VLAN_PRIO;
headers->vlan_hdr.vlan_prio =
cpu_to_be16((match.key->vlan_priority <<
VLAN_PRIO_SHIFT) & VLAN_PRIO_MASK);
}
if (match.mask->vlan_tpid)
headers->vlan_hdr.vlan_tpid = match.key->vlan_tpid;
}
......@@ -1307,6 +1343,9 @@ ice_parse_cls_flower(struct net_device *filter_dev, struct ice_vsi *vsi,
if (match.mask->vlan_id) {
if (match.mask->vlan_id == VLAN_VID_MASK) {
fltr->flags |= ICE_TC_FLWR_FIELD_CVLAN;
headers->cvlan_hdr.vlan_id =
cpu_to_be16(match.key->vlan_id &
VLAN_VID_MASK);
} else {
NL_SET_ERR_MSG_MOD(fltr->extack,
"Bad CVLAN mask");
......@@ -1314,10 +1353,12 @@ ice_parse_cls_flower(struct net_device *filter_dev, struct ice_vsi *vsi,
}
}
headers->cvlan_hdr.vlan_id =
cpu_to_be16(match.key->vlan_id & VLAN_VID_MASK);
if (match.mask->vlan_priority)
headers->cvlan_hdr.vlan_prio = match.key->vlan_priority;
if (match.mask->vlan_priority) {
fltr->flags |= ICE_TC_FLWR_FIELD_CVLAN_PRIO;
headers->cvlan_hdr.vlan_prio =
cpu_to_be16((match.key->vlan_priority <<
VLAN_PRIO_SHIFT) & VLAN_PRIO_MASK);
}
}
if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PPPOE)) {
......
drivers/net/ethernet/intel/ice/ice_tc_lib.h
View file @ d742ea6b
......@@ -31,6 +31,8 @@
#define ICE_TC_FLWR_FIELD_ENC_IP_TOS BIT(24)
#define ICE_TC_FLWR_FIELD_ENC_IP_TTL BIT(25)
#define ICE_TC_FLWR_FIELD_L2TPV3_SESSID BIT(26)
#define ICE_TC_FLWR_FIELD_VLAN_PRIO BIT(27)
#define ICE_TC_FLWR_FIELD_CVLAN_PRIO BIT(28)
#define ICE_TC_FLOWER_MASK_32 0xFFFFFFFF
......@@ -49,7 +51,7 @@ struct ice_tc_flower_action {
struct ice_tc_vlan_hdr {
__be16 vlan_id; /* Only last 12 bits valid */
u16 vlan_prio; /* Only last 3 bits valid (valid values: 0..7) */
__be16 vlan_prio; /* Only last 3 bits valid (valid values: 0..7) */
__be16 vlan_tpid;
};
......
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