Commit d85da227 authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Maxime Ripard

clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM

The PRCM takes PLL_PERIPH0 as one of its parents for the AR100 clock.
As such we need to be able to describe this relationship in the device
tree.

Export the PLL_PERIPH0 clock so we can reference it in the PRCM node.
Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent c4be8c68
...@@ -31,7 +31,9 @@ ...@@ -31,7 +31,9 @@
#define CLK_PLL_VIDEO0_2X 8 #define CLK_PLL_VIDEO0_2X 8
#define CLK_PLL_VE 9 #define CLK_PLL_VE 9
#define CLK_PLL_DDR0 10 #define CLK_PLL_DDR0 10
#define CLK_PLL_PERIPH0 11
/* PLL_PERIPH0 exported for PRCM */
#define CLK_PLL_PERIPH0_2X 12 #define CLK_PLL_PERIPH0_2X 12
#define CLK_PLL_PERIPH1 13 #define CLK_PLL_PERIPH1 13
#define CLK_PLL_PERIPH1_2X 14 #define CLK_PLL_PERIPH1_2X 14
......
...@@ -43,6 +43,8 @@ ...@@ -43,6 +43,8 @@
#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_ #ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_
#define _DT_BINDINGS_CLK_SUN50I_A64_H_ #define _DT_BINDINGS_CLK_SUN50I_A64_H_
#define CLK_PLL_PERIPH0 11
#define CLK_BUS_MIPI_DSI 28 #define CLK_BUS_MIPI_DSI 28
#define CLK_BUS_CE 29 #define CLK_BUS_CE 29
#define CLK_BUS_DMA 30 #define CLK_BUS_DMA 30
......
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