Commit d85dc696 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson

dt-bindings: clk: qcom,dispcc-sm8x50: describe additional DP clocks

On the affected Qualcomm platforms the display clock controller has
additional DP input clocks, describe them in DT schema.
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240512-typec-fix-sm8250-v4-1-ad153c747a97@linaro.orgSigned-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 65424b99
......@@ -27,6 +27,7 @@ properties:
- qcom,sm8350-dispcc
clocks:
minItems: 7
items:
- description: Board XO source
- description: Byte clock from DSI PHY0
......@@ -35,8 +36,15 @@ properties:
- description: Pixel clock from DSI PHY1
- description: Link clock from DP PHY
- description: VCO DIV clock from DP PHY
- description: Link clock from eDP PHY
- description: VCO DIV clock from eDP PHY
- description: Link clock from DP1 PHY
- description: VCO DIV clock from DP1 PHY
- description: Link clock from DP2 PHY
- description: VCO DIV clock from DP2 PHY
clock-names:
minItems: 7
items:
- const: bi_tcxo
- const: dsi0_phy_pll_out_byteclk
......@@ -45,6 +53,12 @@ properties:
- const: dsi1_phy_pll_out_dsiclk
- const: dp_phy_pll_link_clk
- const: dp_phy_pll_vco_div_clk
- const: edp_phy_pll_link_clk
- const: edp_phy_pll_vco_div_clk
- const: dptx1_phy_pll_link_clk
- const: dptx1_phy_pll_vco_div_clk
- const: dptx2_phy_pll_link_clk
- const: dptx2_phy_pll_vco_div_clk
'#clock-cells':
const: 1
......@@ -77,6 +91,20 @@ required:
- '#reset-cells'
- '#power-domain-cells'
allOf:
- if:
not:
properties:
compatible:
contains:
const: qcom,sc8180x-dispcc
then:
properties:
clocks:
maxItems: 7
clock-names:
maxItems: 7
additionalProperties: false
examples:
......
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