Commit d86369e9 authored by Chia-Yuan Li's avatar Chia-Yuan Li Committed by Kalle Valo

rtw89: ser: configure C-MAC interrupt mask

Similarly, create functions to set specific C-MAC masks for firmware
recovery.
Signed-off-by: default avatarChia-Yuan Li <leo.li@realtek.com>
Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220408001353.17188-4-pkshih@realtek.com
parent eeadcd2a
...@@ -2319,6 +2319,23 @@ struct rtw89_imr_info { ...@@ -2319,6 +2319,23 @@ struct rtw89_imr_info {
u32 bbrpt_chinfo_err_imr_reg; u32 bbrpt_chinfo_err_imr_reg;
u32 bbrpt_err_imr_set; u32 bbrpt_err_imr_set;
u32 bbrpt_dfs_err_imr_reg; u32 bbrpt_dfs_err_imr_reg;
u32 ptcl_imr_clr;
u32 ptcl_imr_set;
u32 cdma_imr_0_reg;
u32 cdma_imr_0_clr;
u32 cdma_imr_0_set;
u32 cdma_imr_1_reg;
u32 cdma_imr_1_clr;
u32 cdma_imr_1_set;
u32 phy_intf_imr_reg;
u32 phy_intf_imr_clr;
u32 phy_intf_imr_set;
u32 rmac_imr_reg;
u32 rmac_imr_clr;
u32 rmac_imr_set;
u32 tmac_imr_reg;
u32 tmac_imr_clr;
u32 tmac_imr_set;
}; };
struct rtw89_chip_info { struct rtw89_chip_info {
......
...@@ -2737,10 +2737,76 @@ static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) ...@@ -2737,10 +2737,76 @@ static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev)
rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR);
} }
static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
{
u32 reg;
reg = rtw89_mac_reg_by_idx(R_AX_SCHEDULE_ERR_IMR, mac_idx);
rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN |
B_AX_FSM_TIMEOUT_ERR_INT_EN);
rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN);
}
static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
{
const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
u32 reg;
reg = rtw89_mac_reg_by_idx(R_AX_PTCL_IMR0, mac_idx);
rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr);
rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set);
}
static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
{
const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
u32 reg;
reg = rtw89_mac_reg_by_idx(imr->cdma_imr_0_reg, mac_idx);
rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr);
rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set);
if (chip_id == RTL8852C) {
reg = rtw89_mac_reg_by_idx(imr->cdma_imr_1_reg, mac_idx);
rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr);
rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set);
}
}
static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
{
const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
u32 reg;
reg = rtw89_mac_reg_by_idx(imr->phy_intf_imr_reg, mac_idx);
rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr);
rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set);
}
static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
{
const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
u32 reg;
reg = rtw89_mac_reg_by_idx(imr->rmac_imr_reg, mac_idx);
rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr);
rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set);
}
static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
{
const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
u32 reg;
reg = rtw89_mac_reg_by_idx(imr->tmac_imr_reg, mac_idx);
rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr);
rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set);
}
static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx, static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx,
enum rtw89_mac_hwmod_sel sel) enum rtw89_mac_hwmod_sel sel)
{ {
u32 reg, val;
int ret; int ret;
ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel);
...@@ -2763,40 +2829,12 @@ static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx, ...@@ -2763,40 +2829,12 @@ static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx,
rtw89_cpuio_imr_enable(rtwdev); rtw89_cpuio_imr_enable(rtwdev);
rtw89_bbrpt_imr_enable(rtwdev); rtw89_bbrpt_imr_enable(rtwdev);
} else if (sel == RTW89_CMAC_SEL) { } else if (sel == RTW89_CMAC_SEL) {
reg = rtw89_mac_reg_by_idx(R_AX_SCHEDULE_ERR_IMR, mac_idx); rtw89_scheduler_imr_enable(rtwdev, mac_idx);
rtw89_write32_clr(rtwdev, reg, rtw89_ptcl_imr_enable(rtwdev, mac_idx);
B_AX_SORT_NON_IDLE_ERR_INT_EN); rtw89_cdma_imr_enable(rtwdev, mac_idx);
rtw89_phy_intf_imr_enable(rtwdev, mac_idx);
reg = rtw89_mac_reg_by_idx(R_AX_DLE_CTRL, mac_idx); rtw89_rmac_imr_enable(rtwdev, mac_idx);
rtw89_write32_clr(rtwdev, reg, rtw89_tmac_imr_enable(rtwdev, mac_idx);
B_AX_NO_RESERVE_PAGE_ERR_IMR |
B_AX_RXDATA_FSM_HANG_ERROR_IMR);
reg = rtw89_mac_reg_by_idx(R_AX_PTCL_IMR0, mac_idx);
val = B_AX_F2PCMD_USER_ALLC_ERR_INT_EN |
B_AX_TX_RECORD_PKTID_ERR_INT_EN |
B_AX_FSM_TIMEOUT_ERR_INT_EN;
rtw89_write32(rtwdev, reg, val);
reg = rtw89_mac_reg_by_idx(R_AX_PHYINFO_ERR_IMR, mac_idx);
rtw89_write32_set(rtwdev, reg,
B_AX_PHY_TXON_TIMEOUT_INT_EN |
B_AX_CCK_CCA_TIMEOUT_INT_EN |
B_AX_OFDM_CCA_TIMEOUT_INT_EN |
B_AX_DATA_ON_TIMEOUT_INT_EN |
B_AX_STS_ON_TIMEOUT_INT_EN |
B_AX_CSI_ON_TIMEOUT_INT_EN);
reg = rtw89_mac_reg_by_idx(R_AX_RMAC_ERR_ISR, mac_idx);
val = rtw89_read32(rtwdev, reg);
val |= (B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN |
B_AX_RMAC_RX_TIMEOUT_INT_EN |
B_AX_RMAC_CSI_TIMEOUT_INT_EN);
val &= ~(B_AX_RMAC_CCA_TO_IDLE_TIMEOUT_INT_EN |
B_AX_RMAC_DATA_ON_TO_IDLE_TIMEOUT_INT_EN |
B_AX_RMAC_CCA_TIMEOUT_INT_EN |
B_AX_RMAC_DATA_ON_TIMEOUT_INT_EN);
rtw89_write32(rtwdev, reg, val);
} else { } else {
return -EINVAL; return -EINVAL;
} }
......
This diff is collapsed.
...@@ -434,6 +434,23 @@ static const struct rtw89_imr_info rtw8852a_imr_info = { ...@@ -434,6 +434,23 @@ static const struct rtw89_imr_info rtw8852a_imr_info = {
.bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR, .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR,
.bbrpt_err_imr_set = 0, .bbrpt_err_imr_set = 0,
.bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR, .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR,
.ptcl_imr_clr = B_AX_PTCL_IMR_CLR,
.ptcl_imr_set = B_AX_PTCL_IMR_SET,
.cdma_imr_0_reg = R_AX_DLE_CTRL,
.cdma_imr_0_clr = B_AX_DLE_IMR_CLR,
.cdma_imr_0_set = B_AX_DLE_IMR_SET,
.cdma_imr_1_reg = 0,
.cdma_imr_1_clr = 0,
.cdma_imr_1_set = 0,
.phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR,
.phy_intf_imr_clr = 0,
.phy_intf_imr_set = 0,
.rmac_imr_reg = R_AX_RMAC_ERR_ISR,
.rmac_imr_clr = B_AX_RMAC_IMR_CLR,
.rmac_imr_set = B_AX_RMAC_IMR_SET,
.tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR,
.tmac_imr_clr = B_AX_TMAC_IMR_CLR,
.tmac_imr_set = B_AX_TMAC_IMR_SET,
}; };
static void rtw8852ae_efuse_parsing(struct rtw89_efuse *efuse, static void rtw8852ae_efuse_parsing(struct rtw89_efuse *efuse,
......
...@@ -77,6 +77,23 @@ static const struct rtw89_imr_info rtw8852c_imr_info = { ...@@ -77,6 +77,23 @@ static const struct rtw89_imr_info rtw8852c_imr_info = {
.bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR, .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR,
.bbrpt_err_imr_set = R_AX_BBRPT_CHINFO_IMR_SET_V1, .bbrpt_err_imr_set = R_AX_BBRPT_CHINFO_IMR_SET_V1,
.bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR, .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR,
.ptcl_imr_clr = B_AX_PTCL_IMR_CLR_V1,
.ptcl_imr_set = B_AX_PTCL_IMR_SET_V1,
.cdma_imr_0_reg = R_AX_RX_ERR_FLAG_IMR,
.cdma_imr_0_clr = B_AX_RX_ERR_IMR_CLR_V1,
.cdma_imr_0_set = B_AX_RX_ERR_IMR_SET_V1,
.cdma_imr_1_reg = R_AX_TX_ERR_FLAG_IMR,
.cdma_imr_1_clr = B_AX_TX_ERR_IMR_CLR_V1,
.cdma_imr_1_set = B_AX_TX_ERR_IMR_SET_V1,
.phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR_V1,
.phy_intf_imr_clr = B_AX_PHYINFO_IMR_CLR_V1,
.phy_intf_imr_set = B_AX_PHYINFO_IMR_SET_V1,
.rmac_imr_reg = R_AX_RX_ERR_IMR,
.rmac_imr_clr = B_AX_RMAC_IMR_CLR_V1,
.rmac_imr_set = B_AX_RMAC_IMR_SET_V1,
.tmac_imr_reg = R_AX_TRXPTCL_ERROR_INDICA_MASK,
.tmac_imr_clr = B_AX_TMAC_IMR_CLR_V1,
.tmac_imr_set = B_AX_TMAC_IMR_SET_V1,
}; };
static int rtw8852c_pwr_on_func(struct rtw89_dev *rtwdev) static int rtw8852c_pwr_on_func(struct rtw89_dev *rtwdev)
......
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