[ARM PATCH] 2008/1: OMAP update 4/6: Include files

Patch from Tony Lindgren

This patch syncs the mainline kernel with the linux-omap tree.
The highlights of the patch are:
- DMA fixes from Samuel Ortiz
- USB low level configuration from David Brownell
- H3 support from Nishant Kamat
- TPS65010 power management interface from Dirk Behme

include/asm-arm/arch-omap/board-h2.h

@@ -31,5 +31,15 @@
 
 /* Placeholder for H2 specific defines */
 
+/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
+#define OMAP1610_ETHR_BASE		0xE8000000
+#define OMAP1610_ETHR_SIZE		SZ_4K
+#define OMAP1610_ETHR_START		0x04000000
+
+/* Intel STRATA NOR flash at CS3 */
+#define OMAP1610_NOR_FLASH_BASE		0xD8000000
+#define OMAP1610_NOR_FLASH_SIZE		SZ_32M
+#define OMAP1610_NOR_FLASH_START	0x0C000000
+
 #endif /*  __ASM_ARCH_OMAP_H2_H */
 

include/asm-arm/arch-omap/board-h3.h

 /*
  * linux/include/asm-arm/arch-omap/board-h3.h
  *
- * Hardware definitions for TI OMAP1610 H3 board.
- *
- * Initial creation by Dirk Behme <dirk.behme@de.bosch.com>
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Copyright (C) 2004 Texas Instruments, Inc.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the
@@ -25,11 +24,84 @@
  * with this program; if not, write  to the Free Software Foundation, Inc.,
  * 675 Mass Ave, Cambridge, MA 02139, USA.
  */
-
 #ifndef __ASM_ARCH_OMAP_H3_H
 #define __ASM_ARCH_OMAP_H3_H
 
-/* Placeholder for H3 specific defines */
+/* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
+#define OMAP1710_ETHR_BASE		0xE8000000
+#define OMAP1710_ETHR_SIZE		SZ_4K
+#define OMAP1710_ETHR_START		0x04000000
 
-#endif /*  __ASM_ARCH_OMAP_H3_H */
+/* Intel STRATA NOR flash at CS3 */
+#define OMAP_NOR_FLASH_BASE		0xD8000000
+#define OMAP_NOR_FLASH_SIZE		SZ_32M
+#define OMAP_NOR_FLASH_START		0x00000000
+
+#define MAXIRQNUM			(IH_BOARD_BASE)
+#define MAXFIQNUM			MAXIRQNUM
+#define MAXSWINUM			MAXIRQNUM
 
+#define NR_IRQS				(MAXIRQNUM + 1)
+
+#define OMAP_MCBSP1_BASE		OMAP1610_MCBSP1_BASE
+#define AUDIO_DRR2  (OMAP_MCBSP1_BASE + 0x00)
+#define AUDIO_DRR1  (OMAP_MCBSP1_BASE + 0x02)
+#define AUDIO_DXR2  (OMAP_MCBSP1_BASE + 0x04)
+#define AUDIO_DXR1  (OMAP_MCBSP1_BASE + 0x06)
+#define AUDIO_SPCR2 (OMAP_MCBSP1_BASE + 0x08)
+#define AUDIO_SPCR1 (OMAP_MCBSP1_BASE + 0x0a)
+#define AUDIO_RCR2  (OMAP_MCBSP1_BASE + 0x0c)
+#define AUDIO_RCR1  (OMAP_MCBSP1_BASE + 0x0e)
+#define AUDIO_XCR2  (OMAP_MCBSP1_BASE + 0x10)
+#define AUDIO_XCR1  (OMAP_MCBSP1_BASE + 0x12)
+#define AUDIO_SRGR2 (OMAP_MCBSP1_BASE + 0x14)
+#define AUDIO_SRGR1 (OMAP_MCBSP1_BASE + 0x16)
+#define AUDIO_MCR2  (OMAP_MCBSP1_BASE + 0x18)
+#define AUDIO_MCR1  (OMAP_MCBSP1_BASE + 0x1a)
+#define AUDIO_RCERA (OMAP_MCBSP1_BASE + 0x1c)
+#define AUDIO_RCERB (OMAP_MCBSP1_BASE + 0x1e)
+#define AUDIO_XCERA (OMAP_MCBSP1_BASE + 0x20)
+#define AUDIO_XCERB (OMAP_MCBSP1_BASE + 0x22)
+#define AUDIO_PCR0  (OMAP_MCBSP1_BASE + 0x24)
+
+/* UART3 Registers Maping through MPU bus */
+#define OMAP_MPU_UART3_BASE     0xFFFB9800      /* UART3 through MPU bus */
+#define UART3_RHR               (OMAP_MPU_UART3_BASE + 0)
+#define UART3_THR               (OMAP_MPU_UART3_BASE + 0)
+#define UART3_DLL               (OMAP_MPU_UART3_BASE + 0)
+#define UART3_IER               (OMAP_MPU_UART3_BASE + 4)
+#define UART3_DLH               (OMAP_MPU_UART3_BASE + 4)
+#define UART3_IIR               (OMAP_MPU_UART3_BASE + 8)
+#define UART3_FCR               (OMAP_MPU_UART3_BASE + 8)
+#define UART3_EFR               (OMAP_MPU_UART3_BASE + 8)
+#define UART3_LCR               (OMAP_MPU_UART3_BASE + 0x0C)
+#define UART3_MCR               (OMAP_MPU_UART3_BASE + 0x10)
+#define UART3_XON1_ADDR1        (OMAP_MPU_UART3_BASE + 0x10)
+#define UART3_XON2_ADDR2        (OMAP_MPU_UART3_BASE + 0x14)
+#define UART3_LSR               (OMAP_MPU_UART3_BASE + 0x14)
+#define UART3_TCR               (OMAP_MPU_UART3_BASE + 0x18)
+#define UART3_MSR               (OMAP_MPU_UART3_BASE + 0x18)
+#define UART3_XOFF1             (OMAP_MPU_UART3_BASE + 0x18)
+#define UART3_XOFF2             (OMAP_MPU_UART3_BASE + 0x1C)
+#define UART3_SPR               (OMAP_MPU_UART3_BASE + 0x1C)
+#define UART3_TLR               (OMAP_MPU_UART3_BASE + 0x1C)
+#define UART3_MDR1              (OMAP_MPU_UART3_BASE + 0x20)
+#define UART3_MDR2              (OMAP_MPU_UART3_BASE + 0x24)
+#define UART3_SFLSR             (OMAP_MPU_UART3_BASE + 0x28)
+#define UART3_TXFLL             (OMAP_MPU_UART3_BASE + 0x28)
+#define UART3_RESUME            (OMAP_MPU_UART3_BASE + 0x2C)
+#define UART3_TXFLH             (OMAP_MPU_UART3_BASE + 0x2C)
+#define UART3_SFREGL            (OMAP_MPU_UART3_BASE + 0x30)
+#define UART3_RXFLL             (OMAP_MPU_UART3_BASE + 0x30)
+#define UART3_SFREGH            (OMAP_MPU_UART3_BASE + 0x34)
+#define UART3_RXFLH             (OMAP_MPU_UART3_BASE + 0x34)
+#define UART3_BLR               (OMAP_MPU_UART3_BASE + 0x38)
+#define UART3_ACREG             (OMAP_MPU_UART3_BASE + 0x3C)
+#define UART3_DIV16             (OMAP_MPU_UART3_BASE + 0x3C)
+#define UART3_SCR               (OMAP_MPU_UART3_BASE + 0x40)
+#define UART3_SSR               (OMAP_MPU_UART3_BASE + 0x44)
+#define UART3_EBLR              (OMAP_MPU_UART3_BASE + 0x48)
+#define UART3_OSC_12M_SEL       (OMAP_MPU_UART3_BASE + 0x4C)
+#define UART3_MVR               (OMAP_MPU_UART3_BASE + 0x50)
+
+#endif /*  __ASM_ARCH_OMAP_H3_H */

include/asm-arm/arch-omap/board-innovator.h

@@ -28,92 +28,6 @@
 
 #if defined (CONFIG_ARCH_OMAP1510)
 
-/*
- * ---------------------------------------------------------------------------
- *  OMAP-1510 FPGA
- * ---------------------------------------------------------------------------
- */
-#define OMAP1510_FPGA_BASE			0xE8000000	/* Virtual */
-#define OMAP1510_FPGA_SIZE			SZ_4K
-#define OMAP1510_FPGA_START			0x08000000	/* Physical */
-
-/* Revision */
-#define OMAP1510_FPGA_REV_LOW			(OMAP1510_FPGA_BASE + 0x0)
-#define OMAP1510_FPGA_REV_HIGH			(OMAP1510_FPGA_BASE + 0x1)
-
-#define OMAP1510_FPGA_LCD_PANEL_CONTROL		(OMAP1510_FPGA_BASE + 0x2)
-#define OMAP1510_FPGA_LED_DIGIT			(OMAP1510_FPGA_BASE + 0x3)
-#define INNOVATOR_FPGA_HID_SPI			(OMAP1510_FPGA_BASE + 0x4)
-#define OMAP1510_FPGA_POWER			(OMAP1510_FPGA_BASE + 0x5)
-
-/* Interrupt status */
-#define OMAP1510_FPGA_ISR_LO			(OMAP1510_FPGA_BASE + 0x6)
-#define OMAP1510_FPGA_ISR_HI			(OMAP1510_FPGA_BASE + 0x7)
-
-/* Interrupt mask */
-#define OMAP1510_FPGA_IMR_LO			(OMAP1510_FPGA_BASE + 0x8)
-#define OMAP1510_FPGA_IMR_HI			(OMAP1510_FPGA_BASE + 0x9)
-
-/* Reset registers */
-#define OMAP1510_FPGA_HOST_RESET		(OMAP1510_FPGA_BASE + 0xa)
-#define OMAP1510_FPGA_RST			(OMAP1510_FPGA_BASE + 0xb)
-
-#define OMAP1510_FPGA_AUDIO			(OMAP1510_FPGA_BASE + 0xc)
-#define OMAP1510_FPGA_DIP			(OMAP1510_FPGA_BASE + 0xe)
-#define OMAP1510_FPGA_FPGA_IO			(OMAP1510_FPGA_BASE + 0xf)
-#define OMAP1510_FPGA_UART1			(OMAP1510_FPGA_BASE + 0x14)
-#define OMAP1510_FPGA_UART2			(OMAP1510_FPGA_BASE + 0x15)
-#define OMAP1510_FPGA_OMAP1510_STATUS		(OMAP1510_FPGA_BASE + 0x16)
-#define OMAP1510_FPGA_BOARD_REV			(OMAP1510_FPGA_BASE + 0x18)
-#define OMAP1510P1_PPT_DATA			(OMAP1510_FPGA_BASE + 0x100)
-#define OMAP1510P1_PPT_STATUS			(OMAP1510_FPGA_BASE + 0x101)
-#define OMAP1510P1_PPT_CONTROL			(OMAP1510_FPGA_BASE + 0x102)
-
-#define OMAP1510_FPGA_TOUCHSCREEN		(OMAP1510_FPGA_BASE + 0x204)
-
-#define INNOVATOR_FPGA_INFO			(OMAP1510_FPGA_BASE + 0x205)
-#define INNOVATOR_FPGA_LCD_BRIGHT_LO		(OMAP1510_FPGA_BASE + 0x206)
-#define INNOVATOR_FPGA_LCD_BRIGHT_HI		(OMAP1510_FPGA_BASE + 0x207)
-#define INNOVATOR_FPGA_LED_GRN_LO		(OMAP1510_FPGA_BASE + 0x208)
-#define INNOVATOR_FPGA_LED_GRN_HI		(OMAP1510_FPGA_BASE + 0x209)
-#define INNOVATOR_FPGA_LED_RED_LO		(OMAP1510_FPGA_BASE + 0x20a)
-#define INNOVATOR_FPGA_LED_RED_HI		(OMAP1510_FPGA_BASE + 0x20b)
-#define INNOVATOR_FPGA_CAM_USB_CONTROL		(OMAP1510_FPGA_BASE + 0x20c)
-#define INNOVATOR_FPGA_EXP_CONTROL		(OMAP1510_FPGA_BASE + 0x20d)
-#define INNOVATOR_FPGA_ISR2			(OMAP1510_FPGA_BASE + 0x20e)
-#define INNOVATOR_FPGA_IMR2			(OMAP1510_FPGA_BASE + 0x210)
-
-#define OMAP1510_FPGA_ETHR_START		(OMAP1510_FPGA_START + 0x300)
-#define OMAP1510_FPGA_ETHR_BASE			(OMAP1510_FPGA_BASE + 0x300)
-
-/*
- * Power up Giga UART driver, turn on HID clock.
- * Turn off BT power, since we're not using it and it
- * draws power.
- */
-#define OMAP1510_FPGA_RESET_VALUE		0x42
-
-#define OMAP1510_FPGA_PCR_IF_PD0		(1 << 7)
-#define OMAP1510_FPGA_PCR_COM2_EN		(1 << 6)
-#define OMAP1510_FPGA_PCR_COM1_EN		(1 << 5)
-#define OMAP1510_FPGA_PCR_EXP_PD0		(1 << 4)
-#define OMAP1510_FPGA_PCR_EXP_PD1		(1 << 3)
-#define OMAP1510_FPGA_PCR_48MHZ_CLK		(1 << 2)
-#define OMAP1510_FPGA_PCR_4MHZ_CLK		(1 << 1)
-#define OMAP1510_FPGA_PCR_RSRVD_BIT0		(1 << 0)
-
-/*
- * Innovator/OMAP1510 FPGA HID register bit definitions
- */
-#define FPGA_HID_SCLK	(1<<0)	/* output */
-#define FPGA_HID_MOSI	(1<<1)	/* output */
-#define FPGA_HID_nSS	(1<<2)	/* output 0/1 chip idle/select */
-#define FPGA_HID_nHSUS	(1<<3)	/* output 0/1 host active/suspended */
-#define FPGA_HID_MISO	(1<<4)	/* input */
-#define FPGA_HID_ATN	(1<<5)	/* input  0/1 chip idle/ATN */
-#define FPGA_HID_rsrvd	(1<<6)
-#define FPGA_HID_RESETn (1<<7)	/* output - 0/1 USAR reset/run */
-
 #ifndef OMAP_SDRAM_DEVICE
 #define OMAP_SDRAM_DEVICE			D256M_1X16_4B
 #endif
@@ -147,37 +61,8 @@
 #define OMAP_FLASH_1_START	0x01000000
 #define OMAP_FLASH_1_SIZE	SZ_16M
 
-/* The FPGA IRQ is cascaded through GPIO_13 */
-#define INT_FPGA		(IH_GPIO_BASE + 13)
-
-/* IRQ Numbers for interrupts muxed through the FPGA */
-#define IH_FPGA_BASE		IH_BOARD_BASE
-#define INT_FPGA_ATN		(IH_FPGA_BASE + 0)
-#define INT_FPGA_ACK		(IH_FPGA_BASE + 1)
-#define INT_FPGA2		(IH_FPGA_BASE + 2)
-#define INT_FPGA3		(IH_FPGA_BASE + 3)
-#define INT_FPGA4		(IH_FPGA_BASE + 4)
-#define INT_FPGA5		(IH_FPGA_BASE + 5)
-#define INT_FPGA6		(IH_FPGA_BASE + 6)
-#define INT_FPGA7		(IH_FPGA_BASE + 7)
-#define INT_FPGA8		(IH_FPGA_BASE + 8)
-#define INT_FPGA9		(IH_FPGA_BASE + 9)
-#define INT_FPGA10		(IH_FPGA_BASE + 10)
-#define INT_FPGA11		(IH_FPGA_BASE + 11)
-#define INT_FPGA12		(IH_FPGA_BASE + 12)
-#define INT_ETHER		(IH_FPGA_BASE + 13)
-#define INT_FPGAUART1		(IH_FPGA_BASE + 14)
-#define INT_FPGAUART2		(IH_FPGA_BASE + 15)
-#define INT_FPGA_TS		(IH_FPGA_BASE + 16)
-#define INT_FPGA17		(IH_FPGA_BASE + 17)
-#define INT_FPGA_CAM		(IH_FPGA_BASE + 18)
-#define INT_FPGA_RTC_A		(IH_FPGA_BASE + 19)
-#define INT_FPGA_RTC_B		(IH_FPGA_BASE + 20)
-#define INT_FPGA_CD		(IH_FPGA_BASE + 21)
-#define INT_FPGA22		(IH_FPGA_BASE + 22)
-#define INT_FPGA23		(IH_FPGA_BASE + 23)
-
-#define NR_FPGA_IRQS		 24
+#define NR_FPGA_IRQS		24
+#define NR_IRQS                 IH_BOARD_BASE + NR_FPGA_IRQS
 
 #ifndef __ASSEMBLY__
 void fpga_write(unsigned char val, int reg);

include/asm-arm/arch-omap/board-perseus2.h

@@ -2,8 +2,7 @@
  *  linux/include/asm-arm/arch-omap/board-perseus2.h
  *
  *  Copyright 2003 by Texas Instruments Incorporated
- *    OMAP730 / P2-sample additions
- *    Author: Jean Pihet
+ *    OMAP730 / Perseus2 support by Jean Pihet
  *
  * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com)
  * Author: RidgeRun, Inc.
@@ -28,46 +27,10 @@
  * with this program; if not, write to the Free Software Foundation, Inc.,
  * 675 Mass Ave, Cambridge, MA 02139, USA.
  */
-#ifndef __ASM_ARCH_OMAP_P2SAMPLE_H
-#define __ASM_ARCH_OMAP_P2SAMPLE_H
+#ifndef __ASM_ARCH_OMAP_PERSEUS2_H
+#define __ASM_ARCH_OMAP_PERSEUS2_H
 
-#if defined(CONFIG_ARCH_OMAP730) && defined (CONFIG_MACH_OMAP_PERSEUS2)
-
-/*
- * NOTE:  ALL DEFINITIONS IN THIS FILE NEED TO BE PREFIXED BY IDENTIFIER
- *	  P2SAMPLE_ since they are specific to the EVM and not the chip.
- */
-
-/* ---------------------------------------------------------------------------
- *  OMAP730 Debug Board FPGA
- * ---------------------------------------------------------------------------
- */
-
-/* maps in the FPGA registers and the ETHR registers */
-#define OMAP730_FPGA_BASE		0xE8000000	/* VA */
-#define OMAP730_FPGA_SIZE		SZ_4K		/* SIZE */
-#define OMAP730_FPGA_START		0x04000000	/* PA */
-
-#define OMAP730_FPGA_ETHR_START		OMAP730_FPGA_START
-#define OMAP730_FPGA_ETHR_BASE		OMAP730_FPGA_BASE
-#define OMAP730_FPGA_FPGA_REV		(OMAP730_FPGA_BASE + 0x10)	/* FPGA Revision */
-#define OMAP730_FPGA_BOARD_REV		(OMAP730_FPGA_BASE + 0x12)	/* Board Revision */
-#define OMAP730_FPGA_GPIO		(OMAP730_FPGA_BASE + 0x14)	/* GPIO outputs */
-#define OMAP730_FPGA_LEDS		(OMAP730_FPGA_BASE + 0x16)	/* LEDs outputs */
-#define OMAP730_FPGA_MISC_INPUTS	(OMAP730_FPGA_BASE + 0x18)	/* Misc inputs */
-#define OMAP730_FPGA_LAN_STATUS		(OMAP730_FPGA_BASE + 0x1A)	/* LAN Status line */
-#define OMAP730_FPGA_LAN_RESET		(OMAP730_FPGA_BASE + 0x1C)	/* LAN Reset line */
-
-// LEDs definition on debug board (16 LEDs)
-#define OMAP730_FPGA_LED_CLAIMRELEASE	(1 << 15)
-#define OMAP730_FPGA_LED_STARTSTOP	(1 << 14)
-#define OMAP730_FPGA_LED_HALTED		(1 << 13)
-#define OMAP730_FPGA_LED_IDLE		(1 << 12)
-#define OMAP730_FPGA_LED_TIMER		(1 << 11)
-// cpu0 load-meter LEDs
-#define OMAP730_FPGA_LOAD_METER		(1 << 0)	// A bit of fun on our board ...
-#define OMAP730_FPGA_LOAD_METER_SIZE	11
-#define OMAP730_FPGA_LOAD_METER_MASK	((1 << OMAP730_FPGA_LOAD_METER_SIZE) - 1)
+#include <asm/arch/fpga.h>
 
 #ifndef OMAP_SDRAM_DEVICE
 #define OMAP_SDRAM_DEVICE		D256M_1X16_4B
@@ -86,22 +49,10 @@
 #define OMAP_FLASH_0_START	0x00000000	/* PA */
 #define OMAP_FLASH_0_SIZE	SZ_32M
 
-/* The Ethernet Controller IRQ is cascaded to MPU_EXT_nIRQ througb the FPGA */
-#define INT_ETHER		INT_730_MPU_EXT_NIRQ
-
 #define MAXIRQNUM		IH_BOARD_BASE
 #define MAXFIQNUM		MAXIRQNUM
 #define MAXSWINUM		MAXIRQNUM
 
 #define NR_IRQS			(MAXIRQNUM + 1)
 
-#ifndef __ASSEMBLY__
-void fpga_write(unsigned char val, int reg);
-unsigned char fpga_read(int reg);
-#endif
-
-#else
-#error "Only OMAP730 Perseus2 supported!"
-#endif
-
 #endif

include/asm-arm/arch-omap/board.h

@@ -17,32 +17,69 @@
 #define OMAP_TAG_CLOCK		0x4f01
 #define OMAP_TAG_MMC		0x4f02
 #define OMAP_TAG_UART		0x4f03
+#define OMAP_TAG_USB            0x4f04
 
-struct omap_clock_info {
+struct omap_clock_config {
 	/* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */
 	u8 system_clock_type;
 };
 
-struct omap_mmc_info {
+struct omap_mmc_config {
 	u8 mmc_blocks;
 	s8 mmc1_power_pin, mmc2_power_pin;
 	s8 mmc1_switch_pin, mmc2_switch_pin;
 };
 
-struct omap_uart_info {
+struct omap_uart_config {
 	u8 console_uart;
 	u32 console_speed;
 };
 
-struct omap_board_info_entry {
+struct omap_usb_config {
+	/* Configure drivers according to the connectors on your board:
+	 *  - "A" connector (rectagular)
+	 *	... for host/OHCI use, set "register_host".
+	 *  - "B" connector (squarish) or "Mini-B"
+	 *	... for device/gadget use, set "register_dev".
+	 *  - "Mini-AB" connector (very similar to Mini-B)
+	 *	... for OTG use as device OR host, initialize "otg"
+	 */
+	unsigned	register_host:1;
+	unsigned	register_dev:1;
+	u8		otg;	/* port number, 1-based:  usb1 == 2 */
+
+	u8		hmc_mode;
+
+	/* implicitly true if otg:  host supports remote wakeup? */
+	u8		rwc;
+
+	/* signaling pins used to talk to transceiver on usbN:
+	 *  0 == usbN unused
+	 *  2 == usb0-only, using internal transceiver
+	 *  3 == 3 wire bidirectional
+	 *  4 == 4 wire bidirectional
+	 *  6 == 6 wire unidirectional (or TLL)
+	 */
+	u8		pins[3];
+};
+
+struct omap_board_config_entry {
 	u16 tag;
 	u16 len;
 	u8  data[0];
 };
 
-extern const void *__omap_get_per_info(u16 tag, size_t len);
+struct omap_board_config_kernel {
+	u16 tag;
+	const void *data;
+};
+
+extern const void *__omap_get_config(u16 tag, size_t len);
+
+#define omap_get_config(tag, type) \
+	((const type *) __omap_get_config((tag), sizeof(type)))
 
-#define omap_get_per_info(tag, type) \
-	((const type *) __omap_get_per_info((tag), sizeof(type)))
+extern struct omap_board_config_kernel *omap_board_config;
+extern int omap_board_config_size;
 
 #endif

include/asm-arm/arch-omap/fpga.h

@@ -19,8 +19,161 @@
 #ifndef __ASM_ARCH_OMAP_FPGA_H
 #define __ASM_ARCH_OMAP_FPGA_H
 
-extern void fpga_init_irq(void);
-extern unsigned char fpga_read(int reg);
-extern void fpga_write(unsigned char val, int reg);
+#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP1510)
+extern void omap1510_fpga_init_irq(void);
+#else
+#define omap1510_fpga_init_irq()	(0)
+#endif
+
+#define fpga_read(reg)			__raw_readb(reg)
+#define fpga_write(val, reg)		__raw_writeb(val, reg)
+
+/*
+ * ---------------------------------------------------------------------------
+ *  H2/P2 Debug board FPGA
+ * ---------------------------------------------------------------------------
+ */
+/* maps in the FPGA registers and the ETHR registers */
+#define H2P2_DBG_FPGA_BASE		0xE8000000	/* VA */
+#define H2P2_DBG_FPGA_SIZE		SZ_4K		/* SIZE */
+#define H2P2_DBG_FPGA_START		0x04000000	/* PA */
+
+#define H2P2_DBG_FPGA_ETHR_START	H2P2_DBG_FPGA_START
+#define H2P2_DBG_FPGA_ETHR_BASE		H2P2_DBG_FPGA_BASE
+#define H2P2_DBG_FPGA_FPGA_REV		(H2P2_DBG_FPGA_BASE + 0x10)	/* FPGA Revision */
+#define H2P2_DBG_FPGA_BOARD_REV		(H2P2_DBG_FPGA_BASE + 0x12)	/* Board Revision */
+#define H2P2_DBG_FPGA_GPIO		(H2P2_DBG_FPGA_BASE + 0x14)	/* GPIO outputs */
+#define H2P2_DBG_FPGA_LEDS		(H2P2_DBG_FPGA_BASE + 0x16)	/* LEDs outputs */
+#define H2P2_DBG_FPGA_MISC_INPUTS	(H2P2_DBG_FPGA_BASE + 0x18)	/* Misc inputs */
+#define H2P2_DBG_FPGA_LAN_STATUS	(H2P2_DBG_FPGA_BASE + 0x1A)	/* LAN Status line */
+#define H2P2_DBG_FPGA_LAN_RESET		(H2P2_DBG_FPGA_BASE + 0x1C)	/* LAN Reset line */
+
+/* LEDs definition on debug board (16 LEDs) */
+#define H2P2_DBG_FPGA_LED_CLAIMRELEASE	(1 << 15)
+#define H2P2_DBG_FPGA_LED_STARTSTOP	(1 << 14)
+#define H2P2_DBG_FPGA_LED_HALTED	(1 << 13)
+#define H2P2_DBG_FPGA_LED_IDLE		(1 << 12)
+#define H2P2_DBG_FPGA_LED_TIMER		(1 << 11)
+/*  cpu0 load-meter LEDs */
+#define H2P2_DBG_FPGA_LOAD_METER	(1 << 0)	// A bit of fun on our board ...
+#define H2P2_DBG_FPGA_LOAD_METER_SIZE	11
+#define H2P2_DBG_FPGA_LOAD_METER_MASK	((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
+
+
+/*
+ * ---------------------------------------------------------------------------
+ *  OMAP-1510 FPGA
+ * ---------------------------------------------------------------------------
+ */
+#define OMAP1510_FPGA_BASE			0xE8000000	/* Virtual */
+#define OMAP1510_FPGA_SIZE			SZ_4K
+#define OMAP1510_FPGA_START			0x08000000	/* Physical */
+
+/* Revision */
+#define OMAP1510_FPGA_REV_LOW			(OMAP1510_FPGA_BASE + 0x0)
+#define OMAP1510_FPGA_REV_HIGH			(OMAP1510_FPGA_BASE + 0x1)
+
+#define OMAP1510_FPGA_LCD_PANEL_CONTROL		(OMAP1510_FPGA_BASE + 0x2)
+#define OMAP1510_FPGA_LED_DIGIT			(OMAP1510_FPGA_BASE + 0x3)
+#define INNOVATOR_FPGA_HID_SPI			(OMAP1510_FPGA_BASE + 0x4)
+#define OMAP1510_FPGA_POWER			(OMAP1510_FPGA_BASE + 0x5)
+
+/* Interrupt status */
+#define OMAP1510_FPGA_ISR_LO			(OMAP1510_FPGA_BASE + 0x6)
+#define OMAP1510_FPGA_ISR_HI			(OMAP1510_FPGA_BASE + 0x7)
+
+/* Interrupt mask */
+#define OMAP1510_FPGA_IMR_LO			(OMAP1510_FPGA_BASE + 0x8)
+#define OMAP1510_FPGA_IMR_HI			(OMAP1510_FPGA_BASE + 0x9)
+
+/* Reset registers */
+#define OMAP1510_FPGA_HOST_RESET		(OMAP1510_FPGA_BASE + 0xa)
+#define OMAP1510_FPGA_RST			(OMAP1510_FPGA_BASE + 0xb)
+
+#define OMAP1510_FPGA_AUDIO			(OMAP1510_FPGA_BASE + 0xc)
+#define OMAP1510_FPGA_DIP			(OMAP1510_FPGA_BASE + 0xe)
+#define OMAP1510_FPGA_FPGA_IO			(OMAP1510_FPGA_BASE + 0xf)
+#define OMAP1510_FPGA_UART1			(OMAP1510_FPGA_BASE + 0x14)
+#define OMAP1510_FPGA_UART2			(OMAP1510_FPGA_BASE + 0x15)
+#define OMAP1510_FPGA_OMAP1510_STATUS		(OMAP1510_FPGA_BASE + 0x16)
+#define OMAP1510_FPGA_BOARD_REV			(OMAP1510_FPGA_BASE + 0x18)
+#define OMAP1510P1_PPT_DATA			(OMAP1510_FPGA_BASE + 0x100)
+#define OMAP1510P1_PPT_STATUS			(OMAP1510_FPGA_BASE + 0x101)
+#define OMAP1510P1_PPT_CONTROL			(OMAP1510_FPGA_BASE + 0x102)
+
+#define OMAP1510_FPGA_TOUCHSCREEN		(OMAP1510_FPGA_BASE + 0x204)
+
+#define INNOVATOR_FPGA_INFO			(OMAP1510_FPGA_BASE + 0x205)
+#define INNOVATOR_FPGA_LCD_BRIGHT_LO		(OMAP1510_FPGA_BASE + 0x206)
+#define INNOVATOR_FPGA_LCD_BRIGHT_HI		(OMAP1510_FPGA_BASE + 0x207)
+#define INNOVATOR_FPGA_LED_GRN_LO		(OMAP1510_FPGA_BASE + 0x208)
+#define INNOVATOR_FPGA_LED_GRN_HI		(OMAP1510_FPGA_BASE + 0x209)
+#define INNOVATOR_FPGA_LED_RED_LO		(OMAP1510_FPGA_BASE + 0x20a)
+#define INNOVATOR_FPGA_LED_RED_HI		(OMAP1510_FPGA_BASE + 0x20b)
+#define INNOVATOR_FPGA_CAM_USB_CONTROL		(OMAP1510_FPGA_BASE + 0x20c)
+#define INNOVATOR_FPGA_EXP_CONTROL		(OMAP1510_FPGA_BASE + 0x20d)
+#define INNOVATOR_FPGA_ISR2			(OMAP1510_FPGA_BASE + 0x20e)
+#define INNOVATOR_FPGA_IMR2			(OMAP1510_FPGA_BASE + 0x210)
+
+#define OMAP1510_FPGA_ETHR_START		(OMAP1510_FPGA_START + 0x300)
+#define OMAP1510_FPGA_ETHR_BASE			(OMAP1510_FPGA_BASE + 0x300)
+
+/*
+ * Power up Giga UART driver, turn on HID clock.
+ * Turn off BT power, since we're not using it and it
+ * draws power.
+ */
+#define OMAP1510_FPGA_RESET_VALUE		0x42
+
+#define OMAP1510_FPGA_PCR_IF_PD0		(1 << 7)
+#define OMAP1510_FPGA_PCR_COM2_EN		(1 << 6)
+#define OMAP1510_FPGA_PCR_COM1_EN		(1 << 5)
+#define OMAP1510_FPGA_PCR_EXP_PD0		(1 << 4)
+#define OMAP1510_FPGA_PCR_EXP_PD1		(1 << 3)
+#define OMAP1510_FPGA_PCR_48MHZ_CLK		(1 << 2)
+#define OMAP1510_FPGA_PCR_4MHZ_CLK		(1 << 1)
+#define OMAP1510_FPGA_PCR_RSRVD_BIT0		(1 << 0)
+
+/*
+ * Innovator/OMAP1510 FPGA HID register bit definitions
+ */
+#define OMAP1510_FPGA_HID_SCLK	(1<<0)	/* output */
+#define OMAP1510_FPGA_HID_MOSI	(1<<1)	/* output */
+#define OMAP1510_FPGA_HID_nSS	(1<<2)	/* output 0/1 chip idle/select */
+#define OMAP1510_FPGA_HID_nHSUS	(1<<3)	/* output 0/1 host active/suspended */
+#define OMAP1510_FPGA_HID_MISO	(1<<4)	/* input */
+#define OMAP1510_FPGA_HID_ATN	(1<<5)	/* input  0/1 chip idle/ATN */
+#define OMAP1510_FPGA_HID_rsrvd	(1<<6)
+#define OMAP1510_FPGA_HID_RESETn (1<<7)	/* output - 0/1 USAR reset/run */
+
+/* The FPGA IRQ is cascaded through GPIO_13 */
+#define OMAP1510_INT_FPGA		(IH_GPIO_BASE + 13)
+
+/* IRQ Numbers for interrupts muxed through the FPGA */
+#define OMAP1510_IH_FPGA_BASE		IH_BOARD_BASE
+#define OMAP1510_INT_FPGA_ATN		(OMAP1510_IH_FPGA_BASE + 0)
+#define OMAP1510_INT_FPGA_ACK		(OMAP1510_IH_FPGA_BASE + 1)
+#define OMAP1510_INT_FPGA2		(OMAP1510_IH_FPGA_BASE + 2)
+#define OMAP1510_INT_FPGA3		(OMAP1510_IH_FPGA_BASE + 3)
+#define OMAP1510_INT_FPGA4		(OMAP1510_IH_FPGA_BASE + 4)
+#define OMAP1510_INT_FPGA5		(OMAP1510_IH_FPGA_BASE + 5)
+#define OMAP1510_INT_FPGA6		(OMAP1510_IH_FPGA_BASE + 6)
+#define OMAP1510_INT_FPGA7		(OMAP1510_IH_FPGA_BASE + 7)
+#define OMAP1510_INT_FPGA8		(OMAP1510_IH_FPGA_BASE + 8)
+#define OMAP1510_INT_FPGA9		(OMAP1510_IH_FPGA_BASE + 9)
+#define OMAP1510_INT_FPGA10		(OMAP1510_IH_FPGA_BASE + 10)
+#define OMAP1510_INT_FPGA11		(OMAP1510_IH_FPGA_BASE + 11)
+#define OMAP1510_INT_FPGA12		(OMAP1510_IH_FPGA_BASE + 12)
+#define OMAP1510_INT_ETHER		(OMAP1510_IH_FPGA_BASE + 13)
+#define OMAP1510_INT_FPGAUART1		(OMAP1510_IH_FPGA_BASE + 14)
+#define OMAP1510_INT_FPGAUART2		(OMAP1510_IH_FPGA_BASE + 15)
+#define OMAP1510_INT_FPGA_TS		(OMAP1510_IH_FPGA_BASE + 16)
+#define OMAP1510_INT_FPGA17		(OMAP1510_IH_FPGA_BASE + 17)
+#define OMAP1510_INT_FPGA_CAM		(OMAP1510_IH_FPGA_BASE + 18)
+#define OMAP1510_INT_FPGA_RTC_A		(OMAP1510_IH_FPGA_BASE + 19)
+#define OMAP1510_INT_FPGA_RTC_B		(OMAP1510_IH_FPGA_BASE + 20)
+#define OMAP1510_INT_FPGA_CD		(OMAP1510_IH_FPGA_BASE + 21)
+#define OMAP1510_INT_FPGA22		(OMAP1510_IH_FPGA_BASE + 22)
+#define OMAP1510_INT_FPGA23		(OMAP1510_IH_FPGA_BASE + 23)
 
 #endif

include/asm-arm/arch-omap/hardware.h

@@ -178,6 +178,7 @@
 #define IRQ_CONTROL_REG_OFFSET	0x18
 #define IRQ_ISR_REG_OFFSET	0x9c
 #define IRQ_ILR0_REG_OFFSET	0x1c
+#define IRQ_GMR_REG_OFFSET	0xa0
 
 /*
  * ---------------------------------------------------------------------------
@@ -185,22 +186,23 @@
  * ---------------------------------------------------------------------------
  */
 #define TCMIF_BASE		0xfffecc00
-#define IMIF_PRIO		(TCMIF_BASE + 0x00)
-#define EMIFS_PRIO		(TCMIF_BASE + 0x04)
-#define EMIFF_PRIO		(TCMIF_BASE + 0x08)
-#define EMIFS_CONFIG		(TCMIF_BASE + 0x0c)
-#define EMIFS_CS0_CONFIG	(TCMIF_BASE + 0x10)
-#define EMIFS_CS1_CONFIG	(TCMIF_BASE + 0x14)
-#define EMIFS_CS2_CONFIG	(TCMIF_BASE + 0x18)
-#define EMIFS_CS3_CONFIG	(TCMIF_BASE + 0x1c)
-#define EMIFF_SDRAM_CONFIG	(TCMIF_BASE + 0x20)
-#define EMIFF_MRS		(TCMIF_BASE + 0x24)
-#define TC_TIMEOUT1		(TCMIF_BASE + 0x28)
-#define TC_TIMEOUT2		(TCMIF_BASE + 0x2c)
-#define TC_TIMEOUT3		(TCMIF_BASE + 0x30)
-#define TC_ENDIANISM		(TCMIF_BASE + 0x34)
-#define EMIFF_SDRAM_CONFIG_2	(TCMIF_BASE + 0x3c)
-#define EMIF_CFG_DYNAMIC_WS	(TCMIF_BASE + 0x40)
+#define IMIF_PRIO_REG		__REG32(TCMIF_BASE + 0x00)
+#define EMIFS_PRIO_REG		__REG32(TCMIF_BASE + 0x04)
+#define EMIFF_PRIO_REG		__REG32(TCMIF_BASE + 0x08)
+#define EMIFS_CONFIG_REG	__REG32(TCMIF_BASE + 0x0c)
+#define EMIFS_CS0_CONFIG_REG	__REG32(TCMIF_BASE + 0x10)
+#define EMIFS_CS1_CONFIG_REG	__REG32(TCMIF_BASE + 0x14)
+#define EMIFS_CS2_CONFIG_REG	__REG32(TCMIF_BASE + 0x18)
+#define EMIFS_CS3_CONFIG_REG	__REG32(TCMIF_BASE + 0x1c)
+#define EMIFF_SDRAM_CONFIG_REG	__REG32(TCMIF_BASE + 0x20)
+#define EMIFF_MRS_REG		__REG32(TCMIF_BASE + 0x24)
+#define TC_TIMEOUT1_REG		__REG32(TCMIF_BASE + 0x28)
+#define TC_TIMEOUT2_REG		__REG32(TCMIF_BASE + 0x2c)
+#define TC_TIMEOUT3_REG		__REG32(TCMIF_BASE + 0x30)
+#define TC_ENDIANISM_REG	__REG32(TCMIF_BASE + 0x34)
+#define EMIFF_SDRAM_CONFIG_2_REG __REG32(TCMIF_BASE + 0x3c)
+#define EMIF_CFG_DYNAMIC_WS_REG	__REG32(TCMIF_BASE + 0x40)
+
 /*
  * ----------------------------------------------------------------------------
  * System control registers
@@ -290,6 +292,7 @@
 #define OMAP_ID_1610		0x3576
 #define OMAP_ID_1710		0x35F7
 #define OMAP_ID_5912		0x358C
+#define OMAP_ID_1611            0x358C
 
 #ifdef CONFIG_ARCH_OMAP730
 #include "omap730.h"
@@ -307,12 +310,16 @@
 
 #ifdef CONFIG_ARCH_OMAP1610
 #include "omap1610.h"
-#define cpu_is_omap1710()       (((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_1710)
-/* Detect 1710 as 1610 for now */
-#define cpu_is_omap1610()	(((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_1610 \
-				|| cpu_is_omap1710())
+#define cpu_is_omap1610()	(((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_1610) || \
+				(((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_1611)
 #else
 #define cpu_is_omap1610()	0
+#endif
+
+#ifdef CONFIG_ARCH_OMAP1710
+#include "omap1610.h"
+#define cpu_is_omap1710()       (((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_1710)
+#else
 #define cpu_is_omap1710()	0
 #endif
 
@@ -343,7 +350,6 @@
 
 #ifdef CONFIG_MACH_OMAP_H3
 #include "board-h3.h"
-#error "Support for H3 board not yet implemented."
 #endif
 
 #ifdef CONFIG_MACH_OMAP_H4

include/asm-arm/arch-omap/memory.h

@@ -64,7 +64,7 @@
 
 #define virt_to_lbus(x)		((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET)
 #define lbus_to_virt(x)		((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET)
-#define is_lbus_device(dev)	(cpu_is_omap1510() && dev->coherent_dma_mask == 0x0fffffff)
+#define is_lbus_device(dev)	(cpu_is_omap1510() && dev && dev->coherent_dma_mask == 0x0fffffff)
 
 #define __arch_page_to_dma(dev, page)	({is_lbus_device(dev) ? \
 					(dma_addr_t)virt_to_lbus(page_address(page)) : \

include/asm-arm/arch-omap/mux.h

@@ -135,6 +135,10 @@ typedef enum {
 	UART3_CLKREQ,
 	UART3_BCLK,	/* 12MHz clock out */
 
+	/* PWT & PWL */
+	PWT,
+	PWL,
+
 	/* USB master generic */
 	R18_USB_VBUS,
 	R18_1510_USB_GPIO0,
@@ -154,6 +158,7 @@ typedef enum {
 	USB1_RCV,
 	USB1_SPEED,
 	R13_1610_USB1_SPEED,
+	R13_1710_USB1_SE0,
 
 	/* USB2 master */
 	USB2_SUSP,
@@ -169,6 +174,10 @@ typedef enum {
 	R19_1510_GPIO1,
 	M14_1510_GPIO2,
 
+	/* OMAP-1710 GPIO */
+	R18_1710_GPIO0,
+	W15_1710_GPIO40,
+
 	/* MPUIO */
 	MPUIO2,
 	MPUIO4,
@@ -225,6 +234,7 @@ typedef enum {
 	P10_1610_GPIO22,
 	V5_1610_GPIO24,
 	AA20_1610_GPIO_41,
+	W19_1610_GPIO48,
 
 	/* OMAP-1610 uWire */
 	V19_1610_UWIRE_SCLK,
@@ -242,6 +252,11 @@ typedef enum {
 	MMC_CLK,
 	MMC_DAT3,
 
+	/* OMAP-1710 MMC CMDDIR and DATDIR0 */
+	M15_1710_MMC_CLKI,
+	P19_1710_MMC_CMDDIR,
+	P20_1710_MMC_DATDIR0,
+
 	/* OMAP-1610 USB0 alternate pin configuration */
 	W9_USB0_TXEN,
 	AA9_USB0_VP,
@@ -317,6 +332,10 @@ MUX_CFG("UART3_RTS",		 5,   15,    2,	  0,  25,   0,	 NA,	 0,  0)
 MUX_CFG("UART3_CLKREQ",		 9,   27,    0,	  2,   5,   0,	 NA,	 0,  0)
 MUX_CFG("UART3_BCLK",		 A,    0,    0,	  2,   6,   0,	 NA,	 0,  0)
 
+/* PWT & PWL, conflicts with UART3 */
+MUX_CFG("PWT",		 	 6,    0,    2,	  0,  30,   0,	 NA,	 0,  0)
+MUX_CFG("PWL",		 	 6,    3,    1,	  0,  31,   1,	 NA,	 0,  0)
+
 /* USB internal master generic */
 MUX_CFG("R18_USB_VBUS",		 7,    9,    2,	  1,  11,   0,	 NA,	 0,  1)
 MUX_CFG("R18_1510_USB_GPIO0",	 7,    9,    0,	  1,  11,   1,	 NA,	 0,  1)
@@ -336,6 +355,7 @@ MUX_CFG("USB1_VM",		 A,    6,    1,	  2,   8,   0,	 NA,	 0,  1)
 MUX_CFG("USB1_RCV",		 A,    9,    1,	  2,   9,   0,	 NA,	 0,  1)
 MUX_CFG("USB1_SPEED",		 A,   12,    2,	  2,  10,   0,	 NA,	 0,  1)
 MUX_CFG("R13_1610_USB1_SPEED",	 A,   12,    5,	  2,  10,   0,	 NA,	 0,  1)
+MUX_CFG("R13_1710_USB1_SEO",	 A,   12,    5,   2,  10,   0,   NA,     0,  1)
 
 /* USB2 master */
 MUX_CFG("USB2_SUSP",		 B,    3,    1,	  2,  17,   0,	 NA,	 0,  1)
@@ -347,9 +367,13 @@ MUX_CFG("USB2_SE0",		 C,   24,    2,	  3,   2,   0,	 NA,	 0,  1)
 MUX_CFG("USB2_TXD",		 C,   27,    2,	  3,   3,   0,	 NA,	 0,  1)
 
 /* OMAP-1510 GPIO */
-MUX_CFG("R18_1510_GPIO0",	 7,    9,   0,	  1,  11,   1,	  0,	 0,  1)
-MUX_CFG("R19_1510_GPIO1",	 7,    6,   0,	  1,  10,   1,	  0,	 0,  1)
-MUX_CFG("M14_1510_GPIO2",	 7,    3,   0,	  1,   9,   1,	  0,	 0,  1)
+MUX_CFG("R18_1510_GPIO0",	 7,    9,    0,   1,  11,   1,    0,     0,  1)
+MUX_CFG("R19_1510_GPIO1",	 7,    6,    0,   1,  10,   1,    0,     0,  1)
+MUX_CFG("M14_1510_GPIO2",	 7,    3,    0,   1,   9,   1,    0,     0,  1)
+
+/* OMAP-1710 GPIO */
+MUX_CFG("R18_1710_GPIO0",	 7,    9,    0,   1,  11,   1,    1,     1,  1)
+MUX_CFG("W15_1710_GPIO40",	 9,   27,    7,   2,   5,   1,    2,     1,  1)
 
 /* MPUIO */
 MUX_CFG("MPUIO2",		 7,   18,    0,	  1,   1,   1,	 NA,	 0,  1)
@@ -408,6 +432,7 @@ MUX_CFG("N19_1610_GPIO13",	 6,   12,    0,	  1,   2,   0,	  1,	 1,  1)
 MUX_CFG("P10_1610_GPIO22",	 C,    0,    7,	  2,  26,   0,	  2,	 1,  1)
 MUX_CFG("V5_1610_GPIO24",	 B,   15,    7,	  2,  21,   0,	  2,	 1,  1)
 MUX_CFG("AA20_1610_GPIO_41",	 9,    9,    7,	  1,  31,   0,	  1,	 1,  1)
+MUX_CFG("W19_1610_GPIO48",	 8,   15,    7,   1,  23,   1,    1,     0,  1)
 
 /* OMAP-1610 uWire */
 MUX_CFG("V19_1610_UWIRE_SCLK",	 8,    6,    0,	  1,  20,   0,	  1,	 1,  1)
@@ -417,13 +442,16 @@ MUX_CFG("N14_1610_UWIRE_CS0",	 8,    9,    1,	  1,  21,   0,	  1,	 1,  1)
 MUX_CFG("P15_1610_UWIRE_CS3",	 8,   12,    1,	  1,  22,   0,	  1,	 1,  1)
 MUX_CFG("N15_1610_UWIRE_CS1",	 7,   18,    2,	  1,  14,   0,	 NA,	 0,  1)
 
-/* First MMC interface, same on 1510 and 1610 */
+/* First MMC interface, same on 1510, 1610 and 1710 */
 MUX_CFG("MMC_CMD",		 A,   27,    0,	  2,  15,   1,	  2,	 1,  1)
 MUX_CFG("MMC_DAT1",		 A,   24,    0,	  2,  14,   1,	  2,	 1,  1)
 MUX_CFG("MMC_DAT2",		 A,   18,    0,	  2,  12,   1,	  2,	 1,  1)
 MUX_CFG("MMC_DAT0",		 B,    0,    0,	  2,  16,   1,	  2,	 1,  1)
 MUX_CFG("MMC_CLK",		 A,   21,    0,	 NA,   0,   0,	 NA,	 0,  1)
 MUX_CFG("MMC_DAT3",		10,   15,    0,	  3,   8,   1,	  3,	 1,  1)
+MUX_CFG("M15_1710_MMC_CLKI",	 6,   21,    2,   0,   0,   0,   NA,     0,  1)
+MUX_CFG("P19_1710_MMC_CMDDIR",	 6,   24,    6,   0,   0,   0,   NA,     0,  1)
+MUX_CFG("P20_1710_MMC_DATDIR0",	 6,   27,    5,   0,   0,   0,   NA,     0,  1)
 
 /* OMAP-1610 USB0 alternate configuration */
 MUX_CFG("W9_USB0_TXEN",		 B,   9,     5,	  2,  19,   0,	  2,	 0,  1)

include/asm-arm/arch-omap/omap1510.h

@@ -40,16 +40,6 @@
 #define OMAP1510_SRAM_SIZE	(SZ_128K + SZ_64K)
 #define OMAP1510_SRAM_START	0x20000000
 
-#define OMAP1510_MCBSP1_BASE	0xE1011000
-#define OMAP1510_MCBSP1_SIZE	SZ_4K
-#define OMAP1510_MCBSP1_START	0xE1011000
-
-#define OMAP1510_MCBSP2_BASE	0xFFFB1000
-
-#define OMAP1510_MCBSP3_BASE	0xE1017000
-#define OMAP1510_MCBSP3_SIZE	SZ_4K
-#define OMAP1510_MCBSP3_START	0xE1017000
-
 #define OMAP1510_DSP_BASE	0xE0000000
 #define OMAP1510_DSP_SIZE	0x28000
 #define OMAP1510_DSP_START	0xE0000000
@@ -58,5 +48,14 @@
 #define OMAP1510_DSPREG_SIZE	SZ_128K
 #define OMAP1510_DSPREG_START	0xE1000000
 
+/*
+ * ----------------------------------------------------------------------------
+ * Memory used by power management
+ * ----------------------------------------------------------------------------
+ */
+
+#define OMAP1510_SRAM_IDLE_SUSPEND	(OMAP1510_SRAM_BASE + OMAP1510_SRAM_SIZE - 0x200)
+#define OMAP1510_SRAM_API_SUSPEND	(OMAP1510_SRAM_IDLE_SUSPEND + 0x100)
+
 #endif /*  __ASM_ARCH_OMAP1510_H */
 

include/asm-arm/arch-omap/omap1610.h

@@ -48,6 +48,15 @@
 #define OMAP1610_DSPREG_SIZE	SZ_128K
 #define OMAP1610_DSPREG_START	0xE1000000
 
+/*
+ * ----------------------------------------------------------------------------
+ * Memory used by power management
+ * ----------------------------------------------------------------------------
+ */
+
+#define OMAP1610_SRAM_IDLE_SUSPEND	(OMAP1610_SRAM_BASE + OMAP1610_SRAM_SIZE - 0x200)
+#define OMAP1610_SRAM_API_SUSPEND	(OMAP1610_SRAM_IDLE_SUSPEND + 0x100)
+
 /*
  * ---------------------------------------------------------------------------
  * Interrupts

include/asm-arm/arch-omap/omap5912.h

@@ -49,6 +49,15 @@
 #define OMAP5912_DSPREG_SIZE	SZ_128K
 #define OMAP5912_DSPREG_START	0xE1000000
 
+/*
+ * ----------------------------------------------------------------------------
+ * Memory used by power management
+ * ----------------------------------------------------------------------------
+ */
+
+#define OMAP5912_SRAM_IDLE_SUSPEND	(OMAP5912_SRAM_BASE + OMAP5912_SRAM_SIZE - 0x200)
+#define OMAP5912_SRAM_API_SUSPEND	(OMAP5912_SRAM_IDLE_SUSPEND + 0x100)
+
 /*
  * ---------------------------------------------------------------------------
  * Interrupts

include/asm-arm/arch-omap/omap730.h

@@ -40,12 +40,6 @@
 #define OMAP730_SRAM_SIZE	(SZ_128K + SZ_64K + SZ_8K)
 #define OMAP730_SRAM_START	0x20000000
 
-#define OMAP730_MCBSP1_BASE	0xfffb1000
-#define OMAP730_MCBSP1_SIZE	(SZ_1K * 2)
-#define OMAP730_MCBSP1_START	0xfffb1000
-
-#define OMAP730_MCBSP2_BASE	0xfffb1800
-
 #define OMAP730_DSP_BASE	0xE0000000
 #define OMAP730_DSP_SIZE	0x50000
 #define OMAP730_DSP_START	0xE0000000

include/asm-arm/arch-omap/tps65010.h

+/* linux/include/asm-arm/arch-omap/tps65010.h
+ *
+ * Functions to access TPS65010 power management device.
+ *
+ * Copyright (C) 2004 Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_TPS65010_H
+#define __ASM_ARCH_TPS65010_H
+
+/*
+ * ----------------------------------------------------------------------------
+ * Macros used by exported functions
+ * ----------------------------------------------------------------------------
+ */
+
+#define LED1  1
+#define LED2  2
+#define OFF   0
+#define ON    1
+#define BLINK 2
+#define GPIO1 1
+#define GPIO2 2
+#define GPIO3 3
+#define GPIO4 4
+#define LOW   0
+#define HIGH  1
+
+/*
+ * ----------------------------------------------------------------------------
+ * Exported functions
+ * ----------------------------------------------------------------------------
+ */
+
+/* Draw from VBUS:
+ *   0 mA -- DON'T DRAW (might supply power instead)
+ * 100 mA -- usb unit load (slowest charge rate)
+ * 500 mA -- usb high power (fast battery charge)
+ */
+extern int tps65010_set_vbus_draw(unsigned mA);
+
+/* tps65010_set_gpio_out_value parameter:
+ * gpio:  GPIO1, GPIO2, GPIO3 or GPIO4
+ * value: LOW or HIGH
+ */
+extern int tps65010_set_gpio_out_value(unsigned gpio, unsigned value);
+
+/* tps65010_set_led parameter:
+ * led:  LED1 or LED2
+ * mode: ON, OFF or BLINK
+ */
+extern int tps65010_set_led(unsigned led, unsigned mode);
+
+/* tps65010_set_low_pwr parameter:
+ * mode: ON or OFF
+ */
+extern int tps65010_set_low_pwr(unsigned mode);
+
+#endif /*  __ASM_ARCH_TPS65010_H */
+

include/asm-arm/arch-omap/usb.h

+// include/asm-arm/mach-omap/usb.h
+
+#ifndef	__ASM_ARCH_OMAP_USB_H
+#define	__ASM_ARCH_OMAP_USB_H
+
+#include <asm/arch/board.h>
+
+/*-------------------------------------------------------------------------*/
+
+#define OTG_BASE			0xfffb0400
+#define UDC_BASE			0xfffb4000
+#define OMAP_OHCI_BASE			0xfffba000
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * OTG and transceiver registers, for OMAPs starting with ARM926
+ */
+#define OTG_REG32(offset)		__REG32(OTG_BASE + (offset))
+#define OTG_REG16(offset)		__REG16(OTG_BASE + (offset))
+
+#define OTG_REV_REG			OTG_REG32(0x00)
+#define OTG_SYSCON_1_REG		OTG_REG32(0x04)
+#	define	 USB2_TRX_MODE(w)	(((w)>>24)&0x07)
+#	define	 USB1_TRX_MODE(w)	(((w)>>20)&0x07)
+#	define	 USB0_TRX_MODE(w)	(((w)>>16)&0x07)
+#	define	 OTG_IDLE_EN		(1 << 15)
+#	define	 HST_IDLE_EN		(1 << 14)
+#	define	 DEV_IDLE_EN		(1 << 13)
+#	define	 OTG_RESET_DONE		(1 << 2)
+#define OTG_SYSCON_2_REG		OTG_REG32(0x08)
+#	define	 OTG_EN			(1 << 31)
+#	define	 USBX_SYNCHRO		(1 << 30)
+#	define	 OTG_MST16		(1 << 29)
+#	define	 SRP_GPDATA		(1 << 28)
+#	define	 SRP_GPDVBUS		(1 << 27)
+#	define	 SRP_GPUVBUS(w)		(((w)>>24)&0x07)
+#	define	 A_WAIT_VRISE(w)	(((w)>>20)&0x07)
+#	define	 B_ASE_BRST(w)		(((w)>>16)&0x07)
+#	define	 SRP_DPW		(1 << 14)
+#	define	 SRP_DATA		(1 << 13)
+#	define	 SRP_VBUS		(1 << 12)
+#	define	 OTG_PADEN		(1 << 10)
+#	define	 HMC_PADEN		(1 << 9)
+#	define	 UHOST_EN		(1 << 8)
+#	define	 HMC_TLLSPEED		(1 << 7)
+#	define	 HMC_TLLATTACH		(1 << 6)
+#	define	 OTG_HMC(w)		(((w)>>0)&0x3f)
+#define OTG_CTRL_REG			OTG_REG32(0x0c)
+#	define	 OTG_ASESSVLD		(1 << 20)
+#	define	 OTG_BSESSEND		(1 << 19)
+#	define	 OTG_BSESSVLD		(1 << 18)
+#	define	 OTG_VBUSVLD		(1 << 17)
+#	define	 OTG_ID			(1 << 16)
+#	define	 OTG_DRIVER_SEL		(1 << 15)
+#	define	 OTG_A_SETB_HNPEN	(1 << 12)
+#	define	 OTG_A_BUSREQ		(1 << 11)
+#	define	 OTG_B_HNPEN		(1 << 9)
+#	define	 OTG_B_BUSREQ		(1 << 8)
+#	define	 OTG_BUSDROP		(1 << 7)
+#	define	 OTG_PULLDOWN		(1 << 5)
+#	define	 OTG_PULLUP		(1 << 4)
+#	define	 OTG_DRV_VBUS		(1 << 3)
+#	define	 OTG_PD_VBUS		(1 << 2)
+#	define	 OTG_PU_VBUS		(1 << 1)
+#	define	 OTG_PU_ID		(1 << 0)
+#define OTG_IRQ_EN_REG			OTG_REG16(0x10)
+#	define	 DRIVER_SWITCH		(1 << 15)
+#	define	 A_VBUS_ERR		(1 << 13)
+#	define	 A_REQ_TMROUT		(1 << 12)
+#	define	 A_SRP_DETECT		(1 << 11)
+#	define	 B_HNP_FAIL		(1 << 10)
+#	define	 B_SRP_TMROUT		(1 << 9)
+#	define	 B_SRP_DONE		(1 << 8)
+#	define	 B_SRP_STARTED		(1 << 7)
+#	define	 OPRT_CHG		(1 << 0)
+#define OTG_IRQ_SRC_REG			OTG_REG16(0x14)
+	// same bits as in IRQ_EN
+#define OTG_OUTCTRL_REG			OTG_REG16(0x18)
+#	define	 OTGVPD			(1 << 14)
+#	define	 OTGVPU			(1 << 13)
+#	define	 OTGPUID		(1 << 12)
+#	define	 USB2VDR		(1 << 10)
+#	define	 USB2PDEN		(1 << 9)
+#	define	 USB2PUEN		(1 << 8)
+#	define	 USB1VDR		(1 << 6)
+#	define	 USB1PDEN		(1 << 5)
+#	define	 USB1PUEN		(1 << 4)
+#	define	 USB0VDR		(1 << 2)
+#	define	 USB0PDEN		(1 << 1)
+#	define	 USB0PUEN		(1 << 0)
+#define OTG_TEST_REG			OTG_REG16(0x20)
+#define OTG_VENDOR_CODE_REG		OTG_REG32(0xfc)
+
+/*-------------------------------------------------------------------------*/
+
+#define	USB_TRANSCEIVER_CTRL_REG	__REG32(0xfffe1000 + 0x0064)
+#	define	CONF_USB2_UNI_R		(1 << 8)
+#	define	CONF_USB1_UNI_R		(1 << 7)
+#	define	CONF_USB_PORT0_R(x)	(((x)>>4)&0x7)
+#	define	CONF_USB0_ISOLATE_R	(1 << 3)
+#	define	CONF_USB_PWRDN_DM_R	(1 << 2)
+#	define	CONF_USB_PWRDN_DP_R	(1 << 1)
+
+
+
+
+#endif	/* __ASM_ARCH_OMAP_USB_H */