Commit d93e1ac4 authored by Damien Le Moal's avatar Damien Le Moal Committed by Martin K. Petersen

scsi: pm8001: Remove pm80xx_chip_intx_interrupt_enable/disable()

Remove the functions pm80xx_chip_intx_interrupt_enable() and
pm80xx_chip_intx_interrupt_disable() and open code them respectively in
pm80xx_chip_interrupt_enable() and pm80xx_chip_interrupt_disable().
Signed-off-by: default avatarDamien Le Moal <dlemoal@kernel.org>
Link: https://lore.kernel.org/r/20230911232745.325149-8-dlemoal@kernel.orgAcked-by: default avatarJack Wang <jinpu.wang@ionos.com>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent d6f2f6c6
...@@ -1714,27 +1714,6 @@ static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha) ...@@ -1714,27 +1714,6 @@ static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n"); pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n");
} }
/**
* pm80xx_chip_intx_interrupt_enable - enable PM8001 chip interrupt
* @pm8001_ha: our hba card information
*/
static void
pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
{
pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
}
/**
* pm80xx_chip_intx_interrupt_disable - disable PM8001 chip interrupt
* @pm8001_ha: our hba card information
*/
static void
pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
{
pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
}
/** /**
* pm80xx_chip_interrupt_enable - enable PM8001 chip interrupt * pm80xx_chip_interrupt_enable - enable PM8001 chip interrupt
* @pm8001_ha: our hba card information * @pm8001_ha: our hba card information
...@@ -1749,10 +1728,10 @@ pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec) ...@@ -1749,10 +1728,10 @@ pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
else else
pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U, pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U,
1U << (vec - 32)); 1U << (vec - 32));
return; #else
pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
#endif #endif
pm80xx_chip_intx_interrupt_enable(pm8001_ha);
} }
/** /**
...@@ -1773,9 +1752,9 @@ pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec) ...@@ -1773,9 +1752,9 @@ pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
else else
pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U,
1U << (vec - 32)); 1U << (vec - 32));
return; #else
pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
#endif #endif
pm80xx_chip_intx_interrupt_disable(pm8001_ha);
} }
/** /**
......
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