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Kirill Smelkov
linux
Commits
d9b5f261
Commit
d9b5f261
authored
Sep 08, 2014
by
Ben Skeggs
Browse files
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Email Patches
Plain Diff
drm/nouveau/bios: parse freq ranges and timing id into ramcfg struct
Signed-off-by:
Ben Skeggs
<
bskeggs@redhat.com
>
parent
595d373f
Changes
7
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7 changed files
with
47 additions
and
26 deletions
+47
-26
drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h
drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h
+9
-0
drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h
drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h
+3
-2
drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c
drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c
+23
-16
drivers/gpu/drm/nouveau/core/subdev/bios/timing.c
drivers/gpu/drm/nouveau/core/subdev/bios/timing.c
+2
-0
drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c
drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c
+2
-1
drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c
drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c
+2
-1
drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
+6
-6
No files found.
drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h
View file @
d9b5f261
...
...
@@ -4,11 +4,18 @@
struct
nouveau_bios
;
struct
nvbios_ramcfg
{
unsigned
rammap_ver
;
unsigned
rammap_hdr
;
unsigned
rammap_min
;
unsigned
rammap_max
;
unsigned
rammap_11_08_01
:
1
;
unsigned
rammap_11_08_0c
:
2
;
unsigned
rammap_11_08_10
:
1
;
unsigned
rammap_11_11_0c
:
2
;
unsigned
ramcfg_ver
;
unsigned
ramcfg_hdr
;
unsigned
ramcfg_timing
;
unsigned
ramcfg_11_01_01
:
1
;
unsigned
ramcfg_11_01_02
:
1
;
unsigned
ramcfg_11_01_04
:
1
;
...
...
@@ -43,6 +50,8 @@ struct nvbios_ramcfg {
unsigned
ramcfg_11_08_20
:
1
;
unsigned
ramcfg_11_09
:
8
;
unsigned
timing_ver
;
unsigned
timing_hdr
;
unsigned
timing
[
11
];
unsigned
timing_20_2e_03
:
2
;
unsigned
timing_20_2e_30
:
2
;
...
...
drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h
View file @
d9b5f261
...
...
@@ -8,9 +8,10 @@ u32 nvbios_rammapTe(struct nouveau_bios *, u8 *ver, u8 *hdr,
u32
nvbios_rammapEe
(
struct
nouveau_bios
*
,
int
idx
,
u8
*
ver
,
u8
*
hdr
,
u8
*
cnt
,
u8
*
len
);
u32
nvbios_rammapEp
(
struct
nouveau_bios
*
,
int
idx
,
u8
*
ver
,
u8
*
hdr
,
u8
*
cnt
,
u8
*
len
,
struct
nvbios_ramcfg
*
);
u32
nvbios_rammapEm
(
struct
nouveau_bios
*
,
u16
mhz
,
u8
*
ver
,
u8
*
hdr
,
u8
*
cnt
,
u8
*
len
);
u32
nvbios_rammapEp
(
struct
nouveau_bios
*
,
u16
mhz
,
u8
*
ver
,
u8
*
hdr
,
u8
*
cnt
,
u8
*
len
,
struct
nvbios_ramcfg
*
);
...
...
drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c
View file @
d9b5f261
...
...
@@ -75,28 +75,18 @@ nvbios_rammapEe(struct nouveau_bios *bios, int idx,
}
u32
nvbios_rammapEm
(
struct
nouveau_bios
*
bios
,
u16
khz
,
u8
*
ver
,
u8
*
hdr
,
u8
*
cnt
,
u8
*
len
)
{
int
idx
=
0
;
u32
data
;
while
((
data
=
nvbios_rammapEe
(
bios
,
idx
++
,
ver
,
hdr
,
cnt
,
len
)))
{
if
(
khz
>=
nv_ro16
(
bios
,
data
+
0x00
)
&&
khz
<=
nv_ro16
(
bios
,
data
+
0x02
))
break
;
}
return
data
;
}
u32
nvbios_rammapEp
(
struct
nouveau_bios
*
bios
,
u16
khz
,
nvbios_rammapEp
(
struct
nouveau_bios
*
bios
,
int
idx
,
u8
*
ver
,
u8
*
hdr
,
u8
*
cnt
,
u8
*
len
,
struct
nvbios_ramcfg
*
p
)
{
u32
data
=
nvbios_rammapE
m
(
bios
,
khz
,
ver
,
hdr
,
cnt
,
len
);
u32
data
=
nvbios_rammapE
e
(
bios
,
idx
,
ver
,
hdr
,
cnt
,
len
);
memset
(
p
,
0x00
,
sizeof
(
*
p
));
p
->
rammap_ver
=
*
ver
;
p
->
rammap_hdr
=
*
hdr
;
switch
(
!!
data
*
*
ver
)
{
case
0x11
:
p
->
rammap_min
=
nv_ro16
(
bios
,
data
+
0x00
);
p
->
rammap_max
=
nv_ro16
(
bios
,
data
+
0x02
);
p
->
rammap_11_08_01
=
(
nv_ro08
(
bios
,
data
+
0x08
)
&
0x01
)
>>
0
;
p
->
rammap_11_08_0c
=
(
nv_ro08
(
bios
,
data
+
0x08
)
&
0x0c
)
>>
2
;
p
->
rammap_11_08_10
=
(
nv_ro08
(
bios
,
data
+
0x08
)
&
0x10
)
>>
4
;
...
...
@@ -109,6 +99,20 @@ nvbios_rammapEp(struct nouveau_bios *bios, u16 khz,
return
data
;
}
u32
nvbios_rammapEm
(
struct
nouveau_bios
*
bios
,
u16
mhz
,
u8
*
ver
,
u8
*
hdr
,
u8
*
cnt
,
u8
*
len
,
struct
nvbios_ramcfg
*
info
)
{
int
idx
=
0
;
u32
data
;
while
((
data
=
nvbios_rammapEp
(
bios
,
idx
++
,
ver
,
hdr
,
cnt
,
len
,
info
)))
{
if
(
mhz
>=
info
->
rammap_min
&&
mhz
<=
info
->
rammap_max
)
break
;
}
return
data
;
}
u32
nvbios_rammapSe
(
struct
nouveau_bios
*
bios
,
u32
data
,
u8
ever
,
u8
ehdr
,
u8
ecnt
,
u8
elen
,
int
idx
,
...
...
@@ -129,8 +133,11 @@ nvbios_rammapSp(struct nouveau_bios *bios, u32 data,
u8
*
ver
,
u8
*
hdr
,
struct
nvbios_ramcfg
*
p
)
{
data
=
nvbios_rammapSe
(
bios
,
data
,
ever
,
ehdr
,
ecnt
,
elen
,
idx
,
ver
,
hdr
);
p
->
ramcfg_ver
=
*
ver
;
p
->
ramcfg_hdr
=
*
hdr
;
switch
(
!!
data
*
*
ver
)
{
case
0x11
:
p
->
ramcfg_timing
=
nv_ro08
(
bios
,
data
+
0x00
);
p
->
ramcfg_11_01_01
=
(
nv_ro08
(
bios
,
data
+
0x01
)
&
0x01
)
>>
0
;
p
->
ramcfg_11_01_02
=
(
nv_ro08
(
bios
,
data
+
0x01
)
&
0x02
)
>>
1
;
p
->
ramcfg_11_01_04
=
(
nv_ro08
(
bios
,
data
+
0x01
)
&
0x04
)
>>
2
;
...
...
drivers/gpu/drm/nouveau/core/subdev/bios/timing.c
View file @
d9b5f261
...
...
@@ -89,6 +89,8 @@ nvbios_timingEp(struct nouveau_bios *bios, int idx,
struct
nvbios_ramcfg
*
p
)
{
u16
data
=
nvbios_timingEe
(
bios
,
idx
,
ver
,
hdr
,
cnt
,
len
),
temp
;
p
->
timing_ver
=
*
ver
;
p
->
timing_hdr
=
*
hdr
;
switch
(
!!
data
*
*
ver
)
{
case
0x20
:
p
->
timing
[
0
]
=
nv_ro32
(
bios
,
data
+
0x00
);
...
...
drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c
View file @
d9b5f261
...
...
@@ -79,6 +79,7 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
struct
nva3_ram
*
ram
=
(
void
*
)
pfb
->
ram
;
struct
nva3_ramfuc
*
fuc
=
&
ram
->
fuc
;
struct
nva3_clock_info
mclk
;
struct
nvbios_ramcfg
cfg
;
u8
ver
,
cnt
,
len
,
strap
;
u32
data
;
struct
{
...
...
@@ -91,7 +92,7 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
/* lookup memory config data relevant to the target frequency */
rammap
.
data
=
nvbios_rammapEm
(
bios
,
freq
/
1000
,
&
ver
,
&
rammap
.
size
,
&
cnt
,
&
ramcfg
.
size
);
&
cnt
,
&
ramcfg
.
size
,
&
cfg
);
if
(
!
rammap
.
data
||
ver
!=
0x10
||
rammap
.
size
<
0x0e
)
{
nv_error
(
pfb
,
"invalid/missing rammap entry
\n
"
);
return
-
EINVAL
;
...
...
drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c
View file @
d9b5f261
...
...
@@ -133,6 +133,7 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq)
struct
nouveau_bios
*
bios
=
nouveau_bios
(
pfb
);
struct
nvc0_ram
*
ram
=
(
void
*
)
pfb
->
ram
;
struct
nvc0_ramfuc
*
fuc
=
&
ram
->
fuc
;
struct
nvbios_ramcfg
cfg
;
u8
ver
,
cnt
,
len
,
strap
;
struct
{
u32
data
;
...
...
@@ -145,7 +146,7 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq)
/* lookup memory config data relevant to the target frequency */
rammap
.
data
=
nvbios_rammapEm
(
bios
,
freq
/
1000
,
&
ver
,
&
rammap
.
size
,
&
cnt
,
&
ramcfg
.
size
);
&
cnt
,
&
ramcfg
.
size
,
&
cfg
);
if
(
!
rammap
.
data
||
ver
!=
0x10
||
rammap
.
size
<
0x0e
)
{
nv_error
(
pfb
,
"invalid/missing rammap entry
\n
"
);
return
-
EINVAL
;
...
...
drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
View file @
d9b5f261
...
...
@@ -942,7 +942,7 @@ nve0_ram_calc_data(struct nouveau_fb *pfb, u32 freq,
u8
strap
,
cnt
,
len
;
/* lookup memory config data relevant to the target frequency */
ram
->
base
.
rammap
.
data
=
nvbios_rammapE
p
(
bios
,
freq
/
1000
,
ram
->
base
.
rammap
.
data
=
nvbios_rammapE
m
(
bios
,
freq
/
1000
,
&
ram
->
base
.
rammap
.
version
,
&
ram
->
base
.
rammap
.
size
,
&
cnt
,
&
len
,
&
data
->
bios
);
...
...
@@ -968,12 +968,12 @@ nve0_ram_calc_data(struct nouveau_fb *pfb, u32 freq,
}
/* lookup memory timings, if bios says they're present */
strap
=
nv_ro08
(
bios
,
ram
->
base
.
ramcfg
.
data
+
0x00
);
if
(
strap
!=
0xff
)
{
if
(
data
->
bios
.
ramcfg_timing
!=
0xff
)
{
ram
->
base
.
timing
.
data
=
nvbios_timingEp
(
bios
,
strap
,
&
ram
->
base
.
timing
.
version
,
&
ram
->
base
.
timing
.
size
,
&
cnt
,
&
len
,
&
data
->
bios
);
nvbios_timingEp
(
bios
,
data
->
bios
.
ramcfg_timing
,
&
ram
->
base
.
timing
.
version
,
&
ram
->
base
.
timing
.
size
,
&
cnt
,
&
len
,
&
data
->
bios
);
if
(
!
ram
->
base
.
timing
.
data
||
ram
->
base
.
timing
.
version
!=
0x20
||
ram
->
base
.
timing
.
size
<
0x33
)
{
...
...
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