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Commit d9eb8fea authored by Wenjing Liu's avatar Wenjing Liu Committed by Alex Deucher
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drm/amd/display: Drop DCN for DP2.x logic 

[Why & How]
DCN guard is not necessary for DP2.x relevant logic.
Drop them.

v2: squash in fix for misplaced #endif (Alex)
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Reviewed-by: default avatarJerry Zuo <Jerry.Zuo@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarWenjing Liu <wenjing.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 31d64b82
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Showing with 83 additions and 748 deletions
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
View file @ d9eb8fea
...@@ -797,16 +797,12 @@ void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream) ...@@ -797,16 +797,12 @@ void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream)
sizeof(new_downspread)); sizeof(new_downspread));
} }
#if defined(CONFIG_DRM_AMD_DC_DCN)
void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz) void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz)
{ {
// FPGA programming for this clock in diags framework that // TODO
// needs to go through dm layer, therefore leave dummy interace here
} }
void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable) void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable)
{ {
/* TODO: add peridic detection implementation */ /* TODO: add peridic detection implementation */
} }
#endif
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
View file @ d9eb8fea
...@@ -1692,7 +1692,6 @@ static enum bp_result bios_parser_get_encoder_cap_info( ...@@ -1692,7 +1692,6 @@ static enum bp_result bios_parser_get_encoder_cap_info(
ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0; ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0;
info->HDMI_6GB_EN = (record->encodercaps & info->HDMI_6GB_EN = (record->encodercaps &
ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0; ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0;
#if defined(CONFIG_DRM_AMD_DC_DCN)
info->IS_DP2_CAPABLE = (record->encodercaps & info->IS_DP2_CAPABLE = (record->encodercaps &
ATOM_ENCODER_CAP_RECORD_DP2) ? 1 : 0; ATOM_ENCODER_CAP_RECORD_DP2) ? 1 : 0;
info->DP_UHBR10_EN = (record->encodercaps & info->DP_UHBR10_EN = (record->encodercaps &
...@@ -1701,7 +1700,6 @@ static enum bp_result bios_parser_get_encoder_cap_info( ...@@ -1701,7 +1700,6 @@ static enum bp_result bios_parser_get_encoder_cap_info(
ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN) ? 1 : 0; ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN) ? 1 : 0;
info->DP_UHBR20_EN = (record->encodercaps & info->DP_UHBR20_EN = (record->encodercaps &
ATOM_ENCODER_CAP_RECORD_UHBR20_EN) ? 1 : 0; ATOM_ENCODER_CAP_RECORD_UHBR20_EN) ? 1 : 0;
#endif
info->DP_IS_USB_C = (record->encodercaps & info->DP_IS_USB_C = (record->encodercaps &
ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0; ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0;
......
drivers/gpu/drm/amd/display/dc/bios/command_table2.c
View file @ d9eb8fea
...@@ -338,12 +338,10 @@ static enum bp_result transmitter_control_v1_7( ...@@ -338,12 +338,10 @@ static enum bp_result transmitter_control_v1_7(
const struct command_table_helper *cmd = bp->cmd_helper; const struct command_table_helper *cmd = bp->cmd_helper;
struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7 = {0}; struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7 = {0};
#if defined(CONFIG_DRM_AMD_DC_DCN)
uint8_t hpo_instance = (uint8_t)cntl->hpo_engine_id - ENGINE_ID_HPO_0; uint8_t hpo_instance = (uint8_t)cntl->hpo_engine_id - ENGINE_ID_HPO_0;
if (dc_is_dp_signal(cntl->signal)) if (dc_is_dp_signal(cntl->signal))
hpo_instance = (uint8_t)cntl->hpo_engine_id - ENGINE_ID_HPO_DP_0; hpo_instance = (uint8_t)cntl->hpo_engine_id - ENGINE_ID_HPO_DP_0;
#endif
dig_v1_7.phyid = cmd->phy_id_to_atom(cntl->transmitter); dig_v1_7.phyid = cmd->phy_id_to_atom(cntl->transmitter);
dig_v1_7.action = (uint8_t)cntl->action; dig_v1_7.action = (uint8_t)cntl->action;
...@@ -358,9 +356,7 @@ static enum bp_result transmitter_control_v1_7( ...@@ -358,9 +356,7 @@ static enum bp_result transmitter_control_v1_7(
dig_v1_7.hpdsel = cmd->hpd_sel_to_atom(cntl->hpd_sel); dig_v1_7.hpdsel = cmd->hpd_sel_to_atom(cntl->hpd_sel);
dig_v1_7.digfe_sel = cmd->dig_encoder_sel_to_atom(cntl->engine_id); dig_v1_7.digfe_sel = cmd->dig_encoder_sel_to_atom(cntl->engine_id);
dig_v1_7.connobj_id = (uint8_t)cntl->connector_obj_id.id; dig_v1_7.connobj_id = (uint8_t)cntl->connector_obj_id.id;
#if defined(CONFIG_DRM_AMD_DC_DCN)
dig_v1_7.HPO_instance = hpo_instance; dig_v1_7.HPO_instance = hpo_instance;
#endif
dig_v1_7.symclk_units.symclk_10khz = cntl->pixel_clock/10; dig_v1_7.symclk_units.symclk_10khz = cntl->pixel_clock/10;
if (cntl->action == TRANSMITTER_CONTROL_ENABLE || if (cntl->action == TRANSMITTER_CONTROL_ENABLE ||
......
drivers/gpu/drm/amd/display/dc/core/dc.c
View file @ d9eb8fea
...@@ -2370,10 +2370,8 @@ static enum surface_update_type check_update_surfaces_for_stream( ...@@ -2370,10 +2370,8 @@ static enum surface_update_type check_update_surfaces_for_stream(
if (stream_update->dsc_config) if (stream_update->dsc_config)
su_flags->bits.dsc_changed = 1; su_flags->bits.dsc_changed = 1;
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (stream_update->mst_bw_update) if (stream_update->mst_bw_update)
su_flags->bits.mst_bw = 1; su_flags->bits.mst_bw = 1;
#endif
if (su_flags->raw != 0) if (su_flags->raw != 0)
overall_type = UPDATE_TYPE_FULL; overall_type = UPDATE_TYPE_FULL;
...@@ -2752,14 +2750,12 @@ static void commit_planes_do_stream_update(struct dc *dc, ...@@ -2752,14 +2750,12 @@ static void commit_planes_do_stream_update(struct dc *dc,
if (stream_update->dsc_config) if (stream_update->dsc_config)
dp_update_dsc_config(pipe_ctx); dp_update_dsc_config(pipe_ctx);
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (stream_update->mst_bw_update) { if (stream_update->mst_bw_update) {
if (stream_update->mst_bw_update->is_increase) if (stream_update->mst_bw_update->is_increase)
dc_link_increase_mst_payload(pipe_ctx, stream_update->mst_bw_update->mst_stream_bw); dc_link_increase_mst_payload(pipe_ctx, stream_update->mst_bw_update->mst_stream_bw);
else else
dc_link_reduce_mst_payload(pipe_ctx, stream_update->mst_bw_update->mst_stream_bw); dc_link_reduce_mst_payload(pipe_ctx, stream_update->mst_bw_update->mst_stream_bw);
} }
#endif
if (stream_update->pending_test_pattern) { if (stream_update->pending_test_pattern) {
dc_link_dp_set_test_pattern(stream->link, dc_link_dp_set_test_pattern(stream->link,
......
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
View file @ d9eb8fea
...@@ -120,49 +120,32 @@ void dp_enable_link_phy( ...@@ -120,49 +120,32 @@ void dp_enable_link_phy(
link->cur_link_settings = *link_settings; link->cur_link_settings = *link_settings;
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (dp_get_link_encoding_format(link_settings) == DP_128b_132b_ENCODING) { if (dp_get_link_encoding_format(link_settings) == DP_128b_132b_ENCODING) {
/* TODO - DP2.0 HW: notify link rate change here */ /* TODO - DP2.0 HW: notify link rate change here */
} else if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING) { } else if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING) {
if (dc->clk_mgr->funcs->notify_link_rate_change) if (dc->clk_mgr->funcs->notify_link_rate_change)
dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link); dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link);
} }
#else
if (dc->clk_mgr->funcs->notify_link_rate_change)
dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link);
#endif
if (dmcu != NULL && dmcu->funcs->lock_phy) if (dmcu != NULL && dmcu->funcs->lock_phy)
dmcu->funcs->lock_phy(dmcu); dmcu->funcs->lock_phy(dmcu);
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (dp_get_link_encoding_format(link_settings) == DP_128b_132b_ENCODING) { if (dp_get_link_encoding_format(link_settings) == DP_128b_132b_ENCODING) {
enable_dp_hpo_output(link, link_res, link_settings); enable_dp_hpo_output(link, link_res, link_settings);
} else if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING) { } else if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING) {
if (dc_is_dp_sst_signal(signal)) { if (dc_is_dp_sst_signal(signal)) {
link_enc->funcs->enable_dp_output( link_enc->funcs->enable_dp_output(
link_enc, link_enc,
link_settings, link_settings,
clock_source); clock_source);
} else { } else {
link_enc->funcs->enable_dp_mst_output( link_enc->funcs->enable_dp_mst_output(
link_enc, link_enc,
link_settings, link_settings,
clock_source); clock_source);
} }
} }
#else
if (dc_is_dp_sst_signal(signal)) {
link_enc->funcs->enable_dp_output(
link_enc,
link_settings,
clock_source);
} else {
link_enc->funcs->enable_dp_mst_output(
link_enc,
link_settings,
clock_source);
}
#endif
if (dmcu != NULL && dmcu->funcs->unlock_phy) if (dmcu != NULL && dmcu->funcs->unlock_phy)
dmcu->funcs->unlock_phy(dmcu); dmcu->funcs->unlock_phy(dmcu);
...@@ -242,9 +225,7 @@ void dp_disable_link_phy(struct dc_link *link, const struct link_resource *link_ ...@@ -242,9 +225,7 @@ void dp_disable_link_phy(struct dc_link *link, const struct link_resource *link_
{ {
struct dc *dc = link->ctx->dc; struct dc *dc = link->ctx->dc;
struct dmcu *dmcu = dc->res_pool->dmcu; struct dmcu *dmcu = dc->res_pool->dmcu;
#if defined(CONFIG_DRM_AMD_DC_DCN)
struct hpo_dp_link_encoder *hpo_link_enc = link_res->hpo_dp_link_enc; struct hpo_dp_link_encoder *hpo_link_enc = link_res->hpo_dp_link_enc;
#endif
struct link_encoder *link_enc; struct link_encoder *link_enc;
/* Link should always be assigned encoder when en-/disabling. */ /* Link should always be assigned encoder when en-/disabling. */
...@@ -260,28 +241,22 @@ void dp_disable_link_phy(struct dc_link *link, const struct link_resource *link_ ...@@ -260,28 +241,22 @@ void dp_disable_link_phy(struct dc_link *link, const struct link_resource *link_
if (signal == SIGNAL_TYPE_EDP) { if (signal == SIGNAL_TYPE_EDP) {
if (link->dc->hwss.edp_backlight_control) if (link->dc->hwss.edp_backlight_control)
link->dc->hwss.edp_backlight_control(link, false); link->dc->hwss.edp_backlight_control(link, false);
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (dp_get_link_encoding_format(&link->cur_link_settings) == DP_128b_132b_ENCODING) if (dp_get_link_encoding_format(&link->cur_link_settings) == DP_128b_132b_ENCODING)
disable_dp_hpo_output(link, link_res, signal); disable_dp_hpo_output(link, link_res, signal);
else else
link_enc->funcs->disable_output(link_enc, signal); link_enc->funcs->disable_output(link_enc, signal);
#else
link_enc->funcs->disable_output(link_enc, signal);
#endif
link->dc->hwss.edp_power_control(link, false); link->dc->hwss.edp_power_control(link, false);
} else { } else {
if (dmcu != NULL && dmcu->funcs->lock_phy) if (dmcu != NULL && dmcu->funcs->lock_phy)
dmcu->funcs->lock_phy(dmcu); dmcu->funcs->lock_phy(dmcu);
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (dp_get_link_encoding_format(&link->cur_link_settings) == DP_128b_132b_ENCODING && if (dp_get_link_encoding_format(&link->cur_link_settings) == DP_128b_132b_ENCODING &&
hpo_link_enc) hpo_link_enc)
disable_dp_hpo_output(link, link_res, signal); disable_dp_hpo_output(link, link_res, signal);
else else
link_enc->funcs->disable_output(link_enc, signal); link_enc->funcs->disable_output(link_enc, signal);
#else
link_enc->funcs->disable_output(link_enc, signal);
#endif
if (dmcu != NULL && dmcu->funcs->unlock_phy) if (dmcu != NULL && dmcu->funcs->unlock_phy)
dmcu->funcs->unlock_phy(dmcu); dmcu->funcs->unlock_phy(dmcu);
} }
...@@ -330,14 +305,12 @@ bool dp_set_hw_training_pattern( ...@@ -330,14 +305,12 @@ bool dp_set_hw_training_pattern(
case DP_TRAINING_PATTERN_SEQUENCE_4: case DP_TRAINING_PATTERN_SEQUENCE_4:
test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4; test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
break; break;
#if defined(CONFIG_DRM_AMD_DC_DCN)
case DP_128b_132b_TPS1: case DP_128b_132b_TPS1:
test_pattern = DP_TEST_PATTERN_128b_132b_TPS1_TRAINING_MODE; test_pattern = DP_TEST_PATTERN_128b_132b_TPS1_TRAINING_MODE;
break; break;
case DP_128b_132b_TPS2: case DP_128b_132b_TPS2:
test_pattern = DP_TEST_PATTERN_128b_132b_TPS2_TRAINING_MODE; test_pattern = DP_TEST_PATTERN_128b_132b_TPS2_TRAINING_MODE;
break; break;
#endif
default: default:
break; break;
} }
...@@ -347,10 +320,8 @@ bool dp_set_hw_training_pattern( ...@@ -347,10 +320,8 @@ bool dp_set_hw_training_pattern(
return true; return true;
} }
#if defined(CONFIG_DRM_AMD_DC_DCN)
#define DC_LOGGER \ #define DC_LOGGER \
link->ctx->logger link->ctx->logger
#endif
void dp_set_hw_lane_settings( void dp_set_hw_lane_settings(
struct dc_link *link, struct dc_link *link,
const struct link_resource *link_res, const struct link_resource *link_res,
...@@ -363,7 +334,6 @@ void dp_set_hw_lane_settings( ...@@ -363,7 +334,6 @@ void dp_set_hw_lane_settings(
return; return;
/* call Encoder to set lane settings */ /* call Encoder to set lane settings */
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (dp_get_link_encoding_format(&link_settings->link_settings) == if (dp_get_link_encoding_format(&link_settings->link_settings) ==
DP_128b_132b_ENCODING) { DP_128b_132b_ENCODING) {
link_res->hpo_dp_link_enc->funcs->set_ffe( link_res->hpo_dp_link_enc->funcs->set_ffe(
...@@ -374,9 +344,6 @@ void dp_set_hw_lane_settings( ...@@ -374,9 +344,6 @@ void dp_set_hw_lane_settings(
== DP_8b_10b_ENCODING) { == DP_8b_10b_ENCODING) {
encoder->funcs->dp_set_lane_settings(encoder, link_settings); encoder->funcs->dp_set_lane_settings(encoder, link_settings);
} }
#else
encoder->funcs->dp_set_lane_settings(encoder, link_settings);
#endif
memmove(link->cur_lane_setting, memmove(link->cur_lane_setting,
link_settings->lane_settings, link_settings->lane_settings,
sizeof(link->cur_lane_setting)); sizeof(link->cur_lane_setting));
...@@ -391,9 +358,7 @@ void dp_set_hw_test_pattern( ...@@ -391,9 +358,7 @@ void dp_set_hw_test_pattern(
{ {
struct encoder_set_dp_phy_pattern_param pattern_param = {0}; struct encoder_set_dp_phy_pattern_param pattern_param = {0};
struct link_encoder *encoder; struct link_encoder *encoder;
#if defined(CONFIG_DRM_AMD_DC_DCN)
enum dp_link_encoding link_encoding_format = dp_get_link_encoding_format(&link->cur_link_settings); enum dp_link_encoding link_encoding_format = dp_get_link_encoding_format(&link->cur_link_settings);
#endif
/* Access link encoder based on whether it is statically /* Access link encoder based on whether it is statically
* or dynamically assigned to a link. * or dynamically assigned to a link.
...@@ -409,7 +374,6 @@ void dp_set_hw_test_pattern( ...@@ -409,7 +374,6 @@ void dp_set_hw_test_pattern(
pattern_param.custom_pattern_size = custom_pattern_size; pattern_param.custom_pattern_size = custom_pattern_size;
pattern_param.dp_panel_mode = dp_get_panel_mode(link); pattern_param.dp_panel_mode = dp_get_panel_mode(link);
#if defined(CONFIG_DRM_AMD_DC_DCN)
switch (link_encoding_format) { switch (link_encoding_format) {
case DP_128b_132b_ENCODING: case DP_128b_132b_ENCODING:
link_res->hpo_dp_link_enc->funcs->set_link_test_pattern( link_res->hpo_dp_link_enc->funcs->set_link_test_pattern(
...@@ -423,14 +387,10 @@ void dp_set_hw_test_pattern( ...@@ -423,14 +387,10 @@ void dp_set_hw_test_pattern(
DC_LOG_ERROR("%s: Unknown link encoding format.", __func__); DC_LOG_ERROR("%s: Unknown link encoding format.", __func__);
break; break;
} }
#else
encoder->funcs->dp_set_phy_pattern(encoder, &pattern_param);
#endif
dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN); dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN);
} }
#if defined(CONFIG_DRM_AMD_DC_DCN)
#undef DC_LOGGER #undef DC_LOGGER
#endif
void dp_retrain_link_dp_test(struct dc_link *link, void dp_retrain_link_dp_test(struct dc_link *link,
struct dc_link_settings *link_setting, struct dc_link_settings *link_setting,
...@@ -579,12 +539,8 @@ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) ...@@ -579,12 +539,8 @@ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
/* Enable DSC in encoder */ /* Enable DSC in encoder */
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)
&& !is_dp_128b_132b_signal(pipe_ctx)) { && !is_dp_128b_132b_signal(pipe_ctx)) {
#else
if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
#endif
DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id); DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id);
dsc_optc_config_log(dsc, &dsc_optc_cfg); dsc_optc_config_log(dsc, &dsc_optc_cfg);
pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc, pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc,
...@@ -610,17 +566,13 @@ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) ...@@ -610,17 +566,13 @@ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
/* disable DSC in stream encoder */ /* disable DSC in stream encoder */
if (dc_is_dp_signal(stream->signal)) { if (dc_is_dp_signal(stream->signal)) {
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (is_dp_128b_132b_signal(pipe_ctx)) if (is_dp_128b_132b_signal(pipe_ctx))
pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet(
pipe_ctx->stream_res.hpo_dp_stream_enc, pipe_ctx->stream_res.hpo_dp_stream_enc,
false, false,
NULL, NULL,
true); true);
else else if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
#endif
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config( pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(
pipe_ctx->stream_res.stream_enc, pipe_ctx->stream_res.stream_enc,
OPTC_DSC_DISABLED, 0, 0); OPTC_DSC_DISABLED, 0, 0);
...@@ -696,7 +648,6 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_u ...@@ -696,7 +648,6 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_u
dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]);
if (dc_is_dp_signal(stream->signal)) { if (dc_is_dp_signal(stream->signal)) {
DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id); DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id);
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (is_dp_128b_132b_signal(pipe_ctx)) if (is_dp_128b_132b_signal(pipe_ctx))
pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet(
pipe_ctx->stream_res.hpo_dp_stream_enc, pipe_ctx->stream_res.hpo_dp_stream_enc,
...@@ -704,7 +655,6 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_u ...@@ -704,7 +655,6 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_u
&dsc_packed_pps[0], &dsc_packed_pps[0],
immediate_update); immediate_update);
else else
#endif
pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
pipe_ctx->stream_res.stream_enc, pipe_ctx->stream_res.stream_enc,
true, true,
...@@ -714,7 +664,6 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_u ...@@ -714,7 +664,6 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_u
} else { } else {
/* disable DSC PPS in stream encoder */ /* disable DSC PPS in stream encoder */
if (dc_is_dp_signal(stream->signal)) { if (dc_is_dp_signal(stream->signal)) {
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (is_dp_128b_132b_signal(pipe_ctx)) if (is_dp_128b_132b_signal(pipe_ctx))
pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet(
pipe_ctx->stream_res.hpo_dp_stream_enc, pipe_ctx->stream_res.hpo_dp_stream_enc,
...@@ -722,7 +671,6 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_u ...@@ -722,7 +671,6 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_u
NULL, NULL,
true); true);
else else
#endif
pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
pipe_ctx->stream_res.stream_enc, false, NULL, true); pipe_ctx->stream_res.stream_enc, false, NULL, true);
} }
...@@ -746,7 +694,6 @@ bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx) ...@@ -746,7 +694,6 @@ bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx)
return true; return true;
} }
#if defined(CONFIG_DRM_AMD_DC_DCN)
#undef DC_LOGGER #undef DC_LOGGER
#define DC_LOGGER \ #define DC_LOGGER \
link->ctx->logger link->ctx->logger
...@@ -898,4 +845,3 @@ void setup_dp_hpo_stream(struct pipe_ctx *pipe_ctx, bool enable) ...@@ -898,4 +845,3 @@ void setup_dp_hpo_stream(struct pipe_ctx *pipe_ctx, bool enable)
} }
#undef DC_LOGGER #undef DC_LOGGER
#endif
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
View file @ d9eb8fea
...@@ -356,7 +356,6 @@ bool resource_construct( ...@@ -356,7 +356,6 @@ bool resource_construct(
} }
} }
#if defined(CONFIG_DRM_AMD_DC_DCN)
pool->hpo_dp_stream_enc_count = 0; pool->hpo_dp_stream_enc_count = 0;
if (create_funcs->create_hpo_dp_stream_encoder) { if (create_funcs->create_hpo_dp_stream_encoder) {
for (i = 0; i < caps->num_hpo_dp_stream_encoder; i++) { for (i = 0; i < caps->num_hpo_dp_stream_encoder; i++) {
...@@ -377,7 +376,6 @@ bool resource_construct( ...@@ -377,7 +376,6 @@ bool resource_construct(
pool->hpo_dp_link_enc_count++; pool->hpo_dp_link_enc_count++;
} }
} }
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN) #if defined(CONFIG_DRM_AMD_DC_DCN)
for (i = 0; i < caps->num_mpc_3dlut; i++) { for (i = 0; i < caps->num_mpc_3dlut; i++) {
...@@ -1713,7 +1711,6 @@ static void update_stream_engine_usage( ...@@ -1713,7 +1711,6 @@ static void update_stream_engine_usage(
} }
} }
#if defined(CONFIG_DRM_AMD_DC_DCN)
static void update_hpo_dp_stream_engine_usage( static void update_hpo_dp_stream_engine_usage(
struct resource_context *res_ctx, struct resource_context *res_ctx,
const struct resource_pool *pool, const struct resource_pool *pool,
...@@ -1815,7 +1812,6 @@ static void remove_hpo_dp_link_enc_from_ctx(struct resource_context *res_ctx, ...@@ -1815,7 +1812,6 @@ static void remove_hpo_dp_link_enc_from_ctx(struct resource_context *res_ctx,
pipe_ctx->link_res.hpo_dp_link_enc = NULL; pipe_ctx->link_res.hpo_dp_link_enc = NULL;
} }
} }
#endif
/* TODO: release audio object */ /* TODO: release audio object */
void update_audio_usage( void update_audio_usage(
...@@ -1861,7 +1857,6 @@ static int acquire_first_free_pipe( ...@@ -1861,7 +1857,6 @@ static int acquire_first_free_pipe(
return -1; return -1;
} }
#if defined(CONFIG_DRM_AMD_DC_DCN)
static struct hpo_dp_stream_encoder *find_first_free_match_hpo_dp_stream_enc_for_link( static struct hpo_dp_stream_encoder *find_first_free_match_hpo_dp_stream_enc_for_link(
struct resource_context *res_ctx, struct resource_context *res_ctx,
const struct resource_pool *pool, const struct resource_pool *pool,
...@@ -1879,7 +1874,6 @@ static struct hpo_dp_stream_encoder *find_first_free_match_hpo_dp_stream_enc_for ...@@ -1879,7 +1874,6 @@ static struct hpo_dp_stream_encoder *find_first_free_match_hpo_dp_stream_enc_for
return NULL; return NULL;
} }
#endif
static struct audio *find_first_free_audio( static struct audio *find_first_free_audio(
struct resource_context *res_ctx, struct resource_context *res_ctx,
...@@ -1971,7 +1965,6 @@ enum dc_status dc_remove_stream_from_ctx( ...@@ -1971,7 +1965,6 @@ enum dc_status dc_remove_stream_from_ctx(
if (dc->res_pool->funcs->link_enc_unassign) if (dc->res_pool->funcs->link_enc_unassign)
dc->res_pool->funcs->link_enc_unassign(new_ctx, del_pipe->stream); dc->res_pool->funcs->link_enc_unassign(new_ctx, del_pipe->stream);
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (is_dp_128b_132b_signal(del_pipe)) { if (is_dp_128b_132b_signal(del_pipe)) {
update_hpo_dp_stream_engine_usage( update_hpo_dp_stream_engine_usage(
&new_ctx->res_ctx, dc->res_pool, &new_ctx->res_ctx, dc->res_pool,
...@@ -1979,7 +1972,6 @@ enum dc_status dc_remove_stream_from_ctx( ...@@ -1979,7 +1972,6 @@ enum dc_status dc_remove_stream_from_ctx(
false); false);
remove_hpo_dp_link_enc_from_ctx(&new_ctx->res_ctx, del_pipe, del_pipe->stream); remove_hpo_dp_link_enc_from_ctx(&new_ctx->res_ctx, del_pipe, del_pipe->stream);
} }
#endif
if (del_pipe->stream_res.audio) if (del_pipe->stream_res.audio)
update_audio_usage( update_audio_usage(
...@@ -2232,7 +2224,6 @@ enum dc_status resource_map_pool_resources( ...@@ -2232,7 +2224,6 @@ enum dc_status resource_map_pool_resources(
pipe_ctx->stream_res.stream_enc, pipe_ctx->stream_res.stream_enc,
true); true);
#if defined(CONFIG_DRM_AMD_DC_DCN)
/* Allocate DP HPO Stream Encoder based on signal, hw capabilities /* Allocate DP HPO Stream Encoder based on signal, hw capabilities
* and link settings * and link settings
*/ */
...@@ -2257,7 +2248,6 @@ enum dc_status resource_map_pool_resources( ...@@ -2257,7 +2248,6 @@ enum dc_status resource_map_pool_resources(
return DC_NO_LINK_ENC_RESOURCE; return DC_NO_LINK_ENC_RESOURCE;
} }
} }
#endif
/* TODO: Add check if ASIC support and EDID audio */ /* TODO: Add check if ASIC support and EDID audio */
if (!stream->converter_disable_audio && if (!stream->converter_disable_audio &&
...@@ -2927,12 +2917,10 @@ bool pipe_need_reprogram( ...@@ -2927,12 +2917,10 @@ bool pipe_need_reprogram(
if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc) if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc)
return true; return true;
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (pipe_ctx_old->stream_res.hpo_dp_stream_enc != pipe_ctx->stream_res.hpo_dp_stream_enc) if (pipe_ctx_old->stream_res.hpo_dp_stream_enc != pipe_ctx->stream_res.hpo_dp_stream_enc)
return true; return true;
if (pipe_ctx_old->link_res.hpo_dp_link_enc != pipe_ctx->link_res.hpo_dp_link_enc) if (pipe_ctx_old->link_res.hpo_dp_link_enc != pipe_ctx->link_res.hpo_dp_link_enc)
return true; return true;
#endif
/* DIG link encoder resource assignment for stream changed. */ /* DIG link encoder resource assignment for stream changed. */
if (pipe_ctx_old->stream->ctx->dc->res_pool->funcs->link_encs_assign) { if (pipe_ctx_old->stream->ctx->dc->res_pool->funcs->link_encs_assign) {
...@@ -3199,7 +3187,6 @@ void get_audio_check(struct audio_info *aud_modes, ...@@ -3199,7 +3187,6 @@ void get_audio_check(struct audio_info *aud_modes,
} }
} }
#if defined(CONFIG_DRM_AMD_DC_DCN)
struct hpo_dp_link_encoder *resource_get_hpo_dp_link_enc_for_det_lt( struct hpo_dp_link_encoder *resource_get_hpo_dp_link_enc_for_det_lt(
const struct resource_context *res_ctx, const struct resource_context *res_ctx,
const struct resource_pool *pool, const struct resource_pool *pool,
...@@ -3218,7 +3205,6 @@ struct hpo_dp_link_encoder *resource_get_hpo_dp_link_enc_for_det_lt( ...@@ -3218,7 +3205,6 @@ struct hpo_dp_link_encoder *resource_get_hpo_dp_link_enc_for_det_lt(
return hpo_dp_link_enc; return hpo_dp_link_enc;
} }
#endif
void reset_syncd_pipes_from_disabled_pipes(struct dc *dc, void reset_syncd_pipes_from_disabled_pipes(struct dc *dc,
struct dc_state *context) struct dc_state *context)
......
drivers/gpu/drm/amd/display/dc/dc.h
View file @ d9eb8fea
...@@ -195,10 +195,8 @@ struct dc_caps { ...@@ -195,10 +195,8 @@ struct dc_caps {
unsigned int cursor_cache_size; unsigned int cursor_cache_size;
struct dc_plane_cap planes[MAX_PLANES]; struct dc_plane_cap planes[MAX_PLANES];
struct dc_color_caps color; struct dc_color_caps color;
#if defined(CONFIG_DRM_AMD_DC_DCN)
bool dp_hpo; bool dp_hpo;
bool hdmi_frl_pcon_support; bool hdmi_frl_pcon_support;
#endif
bool edp_dsc_support; bool edp_dsc_support;
bool vbios_lttpr_aware; bool vbios_lttpr_aware;
bool vbios_lttpr_enable; bool vbios_lttpr_enable;
...@@ -306,7 +304,6 @@ struct dc_cap_funcs { ...@@ -306,7 +304,6 @@ struct dc_cap_funcs {
struct link_training_settings; struct link_training_settings;
#if defined(CONFIG_DRM_AMD_DC_DCN)
union allow_lttpr_non_transparent_mode { union allow_lttpr_non_transparent_mode {
struct { struct {
bool DP1_4A : 1; bool DP1_4A : 1;
...@@ -314,7 +311,7 @@ union allow_lttpr_non_transparent_mode { ...@@ -314,7 +311,7 @@ union allow_lttpr_non_transparent_mode {
} bits; } bits;
unsigned char raw; unsigned char raw;
}; };
#endif
/* Structure to hold configuration flags set by dm at dc creation. */ /* Structure to hold configuration flags set by dm at dc creation. */
struct dc_config { struct dc_config {
bool gpu_vm_support; bool gpu_vm_support;
...@@ -327,11 +324,7 @@ struct dc_config { ...@@ -327,11 +324,7 @@ struct dc_config {
bool edp_no_power_sequencing; bool edp_no_power_sequencing;
bool force_enum_edp; bool force_enum_edp;
bool forced_clocks; bool forced_clocks;
#if defined(CONFIG_DRM_AMD_DC_DCN)
union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode;
#else
bool allow_lttpr_non_transparent_mode;
#endif
bool multi_mon_pp_mclk_switch; bool multi_mon_pp_mclk_switch;
bool disable_dmcu; bool disable_dmcu;
bool enable_4to1MPC; bool enable_4to1MPC;
...@@ -689,13 +682,11 @@ struct dc_debug_options { ...@@ -689,13 +682,11 @@ struct dc_debug_options {
bool disable_dsc_edp; bool disable_dsc_edp;
unsigned int force_dsc_edp_policy; unsigned int force_dsc_edp_policy;
bool enable_dram_clock_change_one_display_vactive; bool enable_dram_clock_change_one_display_vactive;
#if defined(CONFIG_DRM_AMD_DC_DCN)
/* TODO - remove once tested */ /* TODO - remove once tested */
bool legacy_dp2_lt; bool legacy_dp2_lt;
bool set_mst_en_for_sst; bool set_mst_en_for_sst;
bool disable_uhbr; bool disable_uhbr;
bool force_dp2_lt_fallback_method; bool force_dp2_lt_fallback_method;
#endif
union mem_low_power_enable_options enable_mem_low_power; union mem_low_power_enable_options enable_mem_low_power;
union root_clock_optimization_options root_clock_optimization; union root_clock_optimization_options root_clock_optimization;
bool hpo_optimization; bool hpo_optimization;
...@@ -1239,12 +1230,10 @@ struct dpcd_caps { ...@@ -1239,12 +1230,10 @@ struct dpcd_caps {
struct psr_caps psr_caps; struct psr_caps psr_caps;
struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info; struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info;
#if defined(CONFIG_DRM_AMD_DC_DCN)
union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates; union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates;
union dp_main_line_channel_coding_cap channel_coding_cap; union dp_main_line_channel_coding_cap channel_coding_cap;
union dp_sink_video_fallback_formats fallback_formats; union dp_sink_video_fallback_formats fallback_formats;
union dp_fec_capability1 fec_cap1; union dp_fec_capability1 fec_cap1;
#endif
}; };
union dpcd_sink_ext_caps { union dpcd_sink_ext_caps {
......
drivers/gpu/drm/amd/display/dc/dc_dp_types.h
View file @ d9eb8fea
...@@ -53,7 +53,6 @@ enum dc_link_rate { ...@@ -53,7 +53,6 @@ enum dc_link_rate {
LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2)- 3.24 Gbps/Lane LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2)- 3.24 Gbps/Lane
LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane
LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2)- 5.40 Gbps/Lane LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2)- 5.40 Gbps/Lane
#if defined(CONFIG_DRM_AMD_DC_DCN)
LINK_RATE_HIGH3 = 0x1E, // Rate_8 (HBR3)- 8.10 Gbps/Lane LINK_RATE_HIGH3 = 0x1E, // Rate_8 (HBR3)- 8.10 Gbps/Lane
/* Starting from DP2.0 link rate enum directly represents actual /* Starting from DP2.0 link rate enum directly represents actual
* link rate value in unit of 10 mbps * link rate value in unit of 10 mbps
...@@ -61,9 +60,6 @@ enum dc_link_rate { ...@@ -61,9 +60,6 @@ enum dc_link_rate {
LINK_RATE_UHBR10 = 1000, // UHBR10 - 10.0 Gbps/Lane LINK_RATE_UHBR10 = 1000, // UHBR10 - 10.0 Gbps/Lane
LINK_RATE_UHBR13_5 = 1350, // UHBR13.5 - 13.5 Gbps/Lane LINK_RATE_UHBR13_5 = 1350, // UHBR13.5 - 13.5 Gbps/Lane
LINK_RATE_UHBR20 = 2000, // UHBR10 - 20.0 Gbps/Lane LINK_RATE_UHBR20 = 2000, // UHBR10 - 20.0 Gbps/Lane
#else
LINK_RATE_HIGH3 = 0x1E // Rate_8 (HBR3)- 8.10 Gbps/Lane
#endif
}; };
enum dc_link_spread { enum dc_link_spread {
...@@ -100,7 +96,6 @@ enum dc_post_cursor2 { ...@@ -100,7 +96,6 @@ enum dc_post_cursor2 {
POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3, POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3,
}; };
#if defined(CONFIG_DRM_AMD_DC_DCN)
enum dc_dp_ffe_preset_level { enum dc_dp_ffe_preset_level {
DP_FFE_PRESET_LEVEL0 = 0, DP_FFE_PRESET_LEVEL0 = 0,
DP_FFE_PRESET_LEVEL1, DP_FFE_PRESET_LEVEL1,
...@@ -120,7 +115,6 @@ enum dc_dp_ffe_preset_level { ...@@ -120,7 +115,6 @@ enum dc_dp_ffe_preset_level {
DP_FFE_PRESET_LEVEL15, DP_FFE_PRESET_LEVEL15,
DP_FFE_PRESET_MAX_LEVEL = DP_FFE_PRESET_LEVEL15, DP_FFE_PRESET_MAX_LEVEL = DP_FFE_PRESET_LEVEL15,
}; };
#endif
enum dc_dp_training_pattern { enum dc_dp_training_pattern {
DP_TRAINING_PATTERN_SEQUENCE_1 = 0, DP_TRAINING_PATTERN_SEQUENCE_1 = 0,
...@@ -128,19 +122,15 @@ enum dc_dp_training_pattern { ...@@ -128,19 +122,15 @@ enum dc_dp_training_pattern {
DP_TRAINING_PATTERN_SEQUENCE_3, DP_TRAINING_PATTERN_SEQUENCE_3,
DP_TRAINING_PATTERN_SEQUENCE_4, DP_TRAINING_PATTERN_SEQUENCE_4,
DP_TRAINING_PATTERN_VIDEOIDLE, DP_TRAINING_PATTERN_VIDEOIDLE,
#if defined(CONFIG_DRM_AMD_DC_DCN)
DP_128b_132b_TPS1, DP_128b_132b_TPS1,
DP_128b_132b_TPS2, DP_128b_132b_TPS2,
DP_128b_132b_TPS2_CDS, DP_128b_132b_TPS2_CDS,
#endif
}; };
enum dp_link_encoding { enum dp_link_encoding {
DP_UNKNOWN_ENCODING = 0, DP_UNKNOWN_ENCODING = 0,
DP_8b_10b_ENCODING = 1, DP_8b_10b_ENCODING = 1,
#if defined(CONFIG_DRM_AMD_DC_DCN)
DP_128b_132b_ENCODING = 2, DP_128b_132b_ENCODING = 2,
#endif
}; };
struct dc_link_settings { struct dc_link_settings {
...@@ -152,7 +142,6 @@ struct dc_link_settings { ...@@ -152,7 +142,6 @@ struct dc_link_settings {
bool dpcd_source_device_specific_field_support; bool dpcd_source_device_specific_field_support;
}; };
#if defined(CONFIG_DRM_AMD_DC_DCN)
union dc_dp_ffe_preset { union dc_dp_ffe_preset {
struct { struct {
uint8_t level : 4; uint8_t level : 4;
...@@ -163,24 +152,19 @@ union dc_dp_ffe_preset { ...@@ -163,24 +152,19 @@ union dc_dp_ffe_preset {
} settings; } settings;
uint8_t raw; uint8_t raw;
}; };
#endif
struct dc_lane_settings { struct dc_lane_settings {
enum dc_voltage_swing VOLTAGE_SWING; enum dc_voltage_swing VOLTAGE_SWING;
enum dc_pre_emphasis PRE_EMPHASIS; enum dc_pre_emphasis PRE_EMPHASIS;
enum dc_post_cursor2 POST_CURSOR2; enum dc_post_cursor2 POST_CURSOR2;
#if defined(CONFIG_DRM_AMD_DC_DCN)
union dc_dp_ffe_preset FFE_PRESET; union dc_dp_ffe_preset FFE_PRESET;
#endif
}; };
struct dc_link_training_overrides { struct dc_link_training_overrides {
enum dc_voltage_swing *voltage_swing; enum dc_voltage_swing *voltage_swing;
enum dc_pre_emphasis *pre_emphasis; enum dc_pre_emphasis *pre_emphasis;
enum dc_post_cursor2 *post_cursor2; enum dc_post_cursor2 *post_cursor2;
#if defined(CONFIG_DRM_AMD_DC_DCN)
union dc_dp_ffe_preset *ffe_preset; union dc_dp_ffe_preset *ffe_preset;
#endif
uint16_t *cr_pattern_time; uint16_t *cr_pattern_time;
uint16_t *eq_pattern_time; uint16_t *eq_pattern_time;
...@@ -194,7 +178,6 @@ struct dc_link_training_overrides { ...@@ -194,7 +178,6 @@ struct dc_link_training_overrides {
bool *fec_enable; bool *fec_enable;
}; };
#if defined(CONFIG_DRM_AMD_DC_DCN)
union payload_table_update_status { union payload_table_update_status {
struct { struct {
uint8_t VC_PAYLOAD_TABLE_UPDATED:1; uint8_t VC_PAYLOAD_TABLE_UPDATED:1;
...@@ -202,7 +185,6 @@ union payload_table_update_status { ...@@ -202,7 +185,6 @@ union payload_table_update_status {
} bits; } bits;
uint8_t raw; uint8_t raw;
}; };
#endif
union dpcd_rev { union dpcd_rev {
struct { struct {
...@@ -291,14 +273,10 @@ union lane_align_status_updated { ...@@ -291,14 +273,10 @@ union lane_align_status_updated {
struct { struct {
uint8_t INTERLANE_ALIGN_DONE:1; uint8_t INTERLANE_ALIGN_DONE:1;
uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1; uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1;
#if defined(CONFIG_DRM_AMD_DC_DCN)
uint8_t EQ_INTERLANE_ALIGN_DONE_128b_132b:1; uint8_t EQ_INTERLANE_ALIGN_DONE_128b_132b:1;
uint8_t CDS_INTERLANE_ALIGN_DONE_128b_132b:1; uint8_t CDS_INTERLANE_ALIGN_DONE_128b_132b:1;
uint8_t LT_FAILED_128b_132b:1; uint8_t LT_FAILED_128b_132b:1;
uint8_t RESERVED:1; uint8_t RESERVED:1;
#else
uint8_t RESERVED:4;
#endif
uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1; uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1;
uint8_t LINK_STATUS_UPDATED:1; uint8_t LINK_STATUS_UPDATED:1;
} bits; } bits;
...@@ -311,12 +289,10 @@ union lane_adjust { ...@@ -311,12 +289,10 @@ union lane_adjust {
uint8_t PRE_EMPHASIS_LANE:2; uint8_t PRE_EMPHASIS_LANE:2;
uint8_t RESERVED:4; uint8_t RESERVED:4;
} bits; } bits;
#if defined(CONFIG_DRM_AMD_DC_DCN)
struct { struct {
uint8_t PRESET_VALUE :4; uint8_t PRESET_VALUE :4;
uint8_t RESERVED :4; uint8_t RESERVED :4;
} tx_ffe; } tx_ffe;
#endif
uint8_t raw; uint8_t raw;
}; };
...@@ -346,12 +322,10 @@ union dpcd_training_lane { ...@@ -346,12 +322,10 @@ union dpcd_training_lane {
uint8_t MAX_PRE_EMPHASIS_REACHED:1; uint8_t MAX_PRE_EMPHASIS_REACHED:1;
uint8_t RESERVED:2; uint8_t RESERVED:2;
} bits; } bits;
#if defined(CONFIG_DRM_AMD_DC_DCN)
struct { struct {
uint8_t PRESET_VALUE :4; uint8_t PRESET_VALUE :4;
uint8_t RESERVED :4; uint8_t RESERVED :4;
} tx_ffe; } tx_ffe;
#endif
uint8_t raw; uint8_t raw;
}; };
...@@ -665,18 +639,9 @@ union test_response { ...@@ -665,18 +639,9 @@ union test_response {
union phy_test_pattern { union phy_test_pattern {
struct { struct {
#if defined(CONFIG_DRM_AMD_DC_DCN)
/* This field is 7 bits for DP2.0 */ /* This field is 7 bits for DP2.0 */
uint8_t PATTERN :7; uint8_t PATTERN :7;
uint8_t RESERVED :1; uint8_t RESERVED :1;
#else
/* DpcdPhyTestPatterns. This field is 2 bits for DP1.1
* and 3 bits for DP1.2.
*/
uint8_t PATTERN :3;
/* BY speci, bit7:2 is 0 for DP1.1. */
uint8_t RESERVED :5;
#endif
} bits; } bits;
uint8_t raw; uint8_t raw;
}; };
...@@ -754,14 +719,10 @@ union dpcd_fec_capability { ...@@ -754,14 +719,10 @@ union dpcd_fec_capability {
uint8_t UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1; uint8_t UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1;
uint8_t CORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1; uint8_t CORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1;
uint8_t BIT_ERROR_COUNT_CAPABLE:1; uint8_t BIT_ERROR_COUNT_CAPABLE:1;
#if defined(CONFIG_DRM_AMD_DC_DCN)
uint8_t PARITY_BLOCK_ERROR_COUNT_CAPABLE:1; uint8_t PARITY_BLOCK_ERROR_COUNT_CAPABLE:1;
uint8_t ARITY_BIT_ERROR_COUNT_CAPABLE:1; uint8_t ARITY_BIT_ERROR_COUNT_CAPABLE:1;
uint8_t FEC_RUNNING_INDICATOR_SUPPORTED:1; uint8_t FEC_RUNNING_INDICATOR_SUPPORTED:1;
uint8_t FEC_ERROR_REPORTING_POLICY_SUPPORTED:1; uint8_t FEC_ERROR_REPORTING_POLICY_SUPPORTED:1;
#else
uint8_t RESERVED:4;
#endif
} bits; } bits;
uint8_t raw; uint8_t raw;
}; };
...@@ -925,7 +886,6 @@ struct dpcd_usb4_dp_tunneling_info { ...@@ -925,7 +886,6 @@ struct dpcd_usb4_dp_tunneling_info {
uint8_t usb4_topology_id[DPCD_USB4_TOPOLOGY_ID_LEN]; uint8_t usb4_topology_id[DPCD_USB4_TOPOLOGY_ID_LEN];
}; };
#if defined(CONFIG_DRM_AMD_DC_DCN)
#ifndef DP_MAIN_LINK_CHANNEL_CODING_CAP #ifndef DP_MAIN_LINK_CHANNEL_CODING_CAP
#define DP_MAIN_LINK_CHANNEL_CODING_CAP 0x006 #define DP_MAIN_LINK_CHANNEL_CODING_CAP 0x006
#endif #endif
...@@ -994,8 +954,8 @@ struct dpcd_usb4_dp_tunneling_info { ...@@ -994,8 +954,8 @@ struct dpcd_usb4_dp_tunneling_info {
#endif #endif
#ifndef DP_INTRA_HOP_AUX_REPLY_INDICATION #ifndef DP_INTRA_HOP_AUX_REPLY_INDICATION
#define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) #define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3)
#endif
/* TODO - Use DRM header to replace above once available */ /* TODO - Use DRM header to replace above once available */
#endif // DP_INTRA_HOP_AUX_REPLY_INDICATION
union dp_main_line_channel_coding_cap { union dp_main_line_channel_coding_cap {
struct { struct {
...@@ -1091,6 +1051,5 @@ union dp_128b_132b_training_aux_rd_interval { ...@@ -1091,6 +1051,5 @@ union dp_128b_132b_training_aux_rd_interval {
} bits; } bits;
uint8_t raw; uint8_t raw;
}; };
#endif
#endif /* DC_DP_TYPES_H */ #endif /* DC_DP_TYPES_H */
drivers/gpu/drm/amd/display/dc/dc_link.h
View file @ d9eb8fea
...@@ -47,10 +47,8 @@ struct dc_link_status { ...@@ -47,10 +47,8 @@ struct dc_link_status {
struct link_mst_stream_allocation { struct link_mst_stream_allocation {
/* DIG front */ /* DIG front */
const struct stream_encoder *stream_enc; const struct stream_encoder *stream_enc;
#if defined(CONFIG_DRM_AMD_DC_DCN)
/* HPO DP Stream Encoder */ /* HPO DP Stream Encoder */
const struct hpo_dp_stream_encoder *hpo_dp_stream_enc; const struct hpo_dp_stream_encoder *hpo_dp_stream_enc;
#endif
/* associate DRM payload table with DC stream encoder */ /* associate DRM payload table with DC stream encoder */
uint8_t vcp_id; uint8_t vcp_id;
/* number of slots required for the DP stream in transport packet */ /* number of slots required for the DP stream in transport packet */
...@@ -318,10 +316,8 @@ enum dc_detect_reason { ...@@ -318,10 +316,8 @@ enum dc_detect_reason {
bool dc_link_detect(struct dc_link *dc_link, enum dc_detect_reason reason); bool dc_link_detect(struct dc_link *dc_link, enum dc_detect_reason reason);
bool dc_link_get_hpd_state(struct dc_link *dc_link); bool dc_link_get_hpd_state(struct dc_link *dc_link);
enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx); enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx);
#if defined(CONFIG_DRM_AMD_DC_DCN)
enum dc_status dc_link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t req_pbn); enum dc_status dc_link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t req_pbn);
enum dc_status dc_link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t req_pbn); enum dc_status dc_link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t req_pbn);
#endif
/* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt). /* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt).
* Return: * Return:
...@@ -455,10 +451,8 @@ uint32_t dc_bandwidth_in_kbps_from_timing( ...@@ -455,10 +451,8 @@ uint32_t dc_bandwidth_in_kbps_from_timing(
bool dc_link_is_fec_supported(const struct dc_link *link); bool dc_link_is_fec_supported(const struct dc_link *link);
bool dc_link_should_enable_fec(const struct dc_link *link); bool dc_link_should_enable_fec(const struct dc_link *link);
#if defined(CONFIG_DRM_AMD_DC_DCN)
uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw); uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw);
enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format(const struct dc_link *link); enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format(const struct dc_link *link);
#endif
const struct link_resource *dc_link_get_cur_link_res(const struct dc_link *link); const struct link_resource *dc_link_get_cur_link_res(const struct dc_link *link);
/* take a snapshot of current link resource allocation state */ /* take a snapshot of current link resource allocation state */
......
drivers/gpu/drm/amd/display/dc/dc_stream.h
View file @ d9eb8fea
...@@ -115,12 +115,10 @@ struct periodic_interrupt_config { ...@@ -115,12 +115,10 @@ struct periodic_interrupt_config {
int lines_offset; int lines_offset;
}; };
#if defined(CONFIG_DRM_AMD_DC_DCN)
struct dc_mst_stream_bw_update { struct dc_mst_stream_bw_update {
bool is_increase; // is bandwidth reduced or increased bool is_increase; // is bandwidth reduced or increased
uint32_t mst_stream_bw; // new mst bandwidth in kbps uint32_t mst_stream_bw; // new mst bandwidth in kbps
}; };
#endif
union stream_update_flags { union stream_update_flags {
struct { struct {
...@@ -132,9 +130,7 @@ union stream_update_flags { ...@@ -132,9 +130,7 @@ union stream_update_flags {
uint32_t gamut_remap:1; uint32_t gamut_remap:1;
uint32_t wb_update:1; uint32_t wb_update:1;
uint32_t dsc_changed : 1; uint32_t dsc_changed : 1;
#if defined(CONFIG_DRM_AMD_DC_DCN)
uint32_t mst_bw : 1; uint32_t mst_bw : 1;
#endif
} bits; } bits;
uint32_t raw; uint32_t raw;
...@@ -288,9 +284,7 @@ struct dc_stream_update { ...@@ -288,9 +284,7 @@ struct dc_stream_update {
struct dc_writeback_update *wb_update; struct dc_writeback_update *wb_update;
struct dc_dsc_config *dsc_config; struct dc_dsc_config *dsc_config;
#if defined(CONFIG_DRM_AMD_DC_DCN)
struct dc_mst_stream_bw_update *mst_bw_update; struct dc_mst_stream_bw_update *mst_bw_update;
#endif
struct dc_transfer_func *func_shaper; struct dc_transfer_func *func_shaper;
struct dc_3dlut *lut3d_func; struct dc_3dlut *lut3d_func;
......
drivers/gpu/drm/amd/display/dc/dc_types.h
View file @ d9eb8fea
...@@ -395,14 +395,11 @@ struct dc_lttpr_caps { ...@@ -395,14 +395,11 @@ struct dc_lttpr_caps {
uint8_t max_link_rate; uint8_t max_link_rate;
uint8_t phy_repeater_cnt; uint8_t phy_repeater_cnt;
uint8_t max_ext_timeout; uint8_t max_ext_timeout;
#if defined(CONFIG_DRM_AMD_DC_DCN)
union dp_main_link_channel_coding_lttpr_cap main_link_channel_coding; union dp_main_link_channel_coding_lttpr_cap main_link_channel_coding;
union dp_128b_132b_supported_lttpr_link_rates supported_128b_132b_rates; union dp_128b_132b_supported_lttpr_link_rates supported_128b_132b_rates;
#endif
uint8_t aux_rd_interval[MAX_REPEATER_CNT - 1]; uint8_t aux_rd_interval[MAX_REPEATER_CNT - 1];
}; };
#if defined(CONFIG_DRM_AMD_DC_DCN)
struct dc_dongle_dfp_cap_ext { struct dc_dongle_dfp_cap_ext {
bool supported; bool supported;
uint16_t max_pixel_rate_in_mps; uint16_t max_pixel_rate_in_mps;
...@@ -414,7 +411,6 @@ struct dc_dongle_dfp_cap_ext { ...@@ -414,7 +411,6 @@ struct dc_dongle_dfp_cap_ext {
struct dp_color_depth_caps ycbcr422_color_depth_caps; struct dp_color_depth_caps ycbcr422_color_depth_caps;
struct dp_color_depth_caps ycbcr420_color_depth_caps; struct dp_color_depth_caps ycbcr420_color_depth_caps;
}; };
#endif
struct dc_dongle_caps { struct dc_dongle_caps {
/* dongle type (DP converter, CV smart dongle) */ /* dongle type (DP converter, CV smart dongle) */
...@@ -429,10 +425,8 @@ struct dc_dongle_caps { ...@@ -429,10 +425,8 @@ struct dc_dongle_caps {
bool is_dp_hdmi_ycbcr420_converter; bool is_dp_hdmi_ycbcr420_converter;
uint32_t dp_hdmi_max_bpc; uint32_t dp_hdmi_max_bpc;
uint32_t dp_hdmi_max_pixel_clk_in_khz; uint32_t dp_hdmi_max_pixel_clk_in_khz;
#if defined(CONFIG_DRM_AMD_DC_DCN)
uint32_t dp_hdmi_frl_max_link_bw_in_kbps; uint32_t dp_hdmi_frl_max_link_bw_in_kbps;
struct dc_dongle_dfp_cap_ext dfp_cap_ext; struct dc_dongle_dfp_cap_ext dfp_cap_ext;
#endif
}; };
/* Scaling format */ /* Scaling format */
enum scaling_transformation { enum scaling_transformation {
......
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
View file @ d9eb8fea
...@@ -49,9 +49,7 @@ ...@@ -49,9 +49,7 @@
#include "link_enc_cfg.h" #include "link_enc_cfg.h"
#include "link_hwss.h" #include "link_hwss.h"
#include "dc_link_dp.h" #include "dc_link_dp.h"
#if defined(CONFIG_DRM_AMD_DC_DCN)
#include "dccg.h" #include "dccg.h"
#endif
#include "clock_source.h" #include "clock_source.h"
#include "clk_mgr.h" #include "clk_mgr.h"
#include "abm.h" #include "abm.h"
...@@ -1112,17 +1110,12 @@ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx) ...@@ -1112,17 +1110,12 @@ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
clk_mgr->funcs->enable_pme_wa(clk_mgr); clk_mgr->funcs->enable_pme_wa(clk_mgr);
/* un-mute audio */ /* un-mute audio */
/* TODO: audio should be per stream rather than per link */ /* TODO: audio should be per stream rather than per link */
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (is_dp_128b_132b_signal(pipe_ctx)) if (is_dp_128b_132b_signal(pipe_ctx))
pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->audio_mute_control( pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->audio_mute_control(
pipe_ctx->stream_res.hpo_dp_stream_enc, false); pipe_ctx->stream_res.hpo_dp_stream_enc, false);
else else
pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
pipe_ctx->stream_res.stream_enc, false); pipe_ctx->stream_res.stream_enc, false);
#else
pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
pipe_ctx->stream_res.stream_enc, false);
#endif
if (pipe_ctx->stream_res.audio) if (pipe_ctx->stream_res.audio)
pipe_ctx->stream_res.audio->enabled = true; pipe_ctx->stream_res.audio->enabled = true;
} }
...@@ -1145,32 +1138,22 @@ void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx) ...@@ -1145,32 +1138,22 @@ void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx)
if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false) if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false)
return; return;
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (is_dp_128b_132b_signal(pipe_ctx)) if (is_dp_128b_132b_signal(pipe_ctx))
pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->audio_mute_control( pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->audio_mute_control(
pipe_ctx->stream_res.hpo_dp_stream_enc, true); pipe_ctx->stream_res.hpo_dp_stream_enc, true);
else else
pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
pipe_ctx->stream_res.stream_enc, true); pipe_ctx->stream_res.stream_enc, true);
#else
pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
pipe_ctx->stream_res.stream_enc, true);
#endif
if (pipe_ctx->stream_res.audio) { if (pipe_ctx->stream_res.audio) {
pipe_ctx->stream_res.audio->enabled = false; pipe_ctx->stream_res.audio->enabled = false;
if (dc_is_dp_signal(pipe_ctx->stream->signal)) if (dc_is_dp_signal(pipe_ctx->stream->signal))
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (is_dp_128b_132b_signal(pipe_ctx)) if (is_dp_128b_132b_signal(pipe_ctx))
pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_disable( pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_disable(
pipe_ctx->stream_res.hpo_dp_stream_enc); pipe_ctx->stream_res.hpo_dp_stream_enc);
else else
pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable( pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
pipe_ctx->stream_res.stream_enc); pipe_ctx->stream_res.stream_enc);
#else
pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
pipe_ctx->stream_res.stream_enc);
#endif
else else
pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable( pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(
pipe_ctx->stream_res.stream_enc); pipe_ctx->stream_res.stream_enc);
...@@ -1204,14 +1187,10 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) ...@@ -1204,14 +1187,10 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
pipe_ctx->stream_res.stream_enc); pipe_ctx->stream_res.stream_enc);
} }
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (is_dp_128b_132b_signal(pipe_ctx)) { if (is_dp_128b_132b_signal(pipe_ctx)) {
pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->stop_dp_info_packets( pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->stop_dp_info_packets(
pipe_ctx->stream_res.hpo_dp_stream_enc); pipe_ctx->stream_res.hpo_dp_stream_enc);
} else if (dc_is_dp_signal(pipe_ctx->stream->signal)) } else if (dc_is_dp_signal(pipe_ctx->stream->signal))
#else
if (dc_is_dp_signal(pipe_ctx->stream->signal))
#endif
pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets( pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
pipe_ctx->stream_res.stream_enc); pipe_ctx->stream_res.stream_enc);
...@@ -1224,7 +1203,6 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) ...@@ -1224,7 +1203,6 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
link_enc = link_enc_cfg_get_link_enc_used_by_link(link->ctx->dc, link); link_enc = link_enc_cfg_get_link_enc_used_by_link(link->ctx->dc, link);
ASSERT(link_enc); ASSERT(link_enc);
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (is_dp_128b_132b_signal(pipe_ctx)) { if (is_dp_128b_132b_signal(pipe_ctx)) {
pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->disable( pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->disable(
pipe_ctx->stream_res.hpo_dp_stream_enc); pipe_ctx->stream_res.hpo_dp_stream_enc);
...@@ -1237,13 +1215,7 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) ...@@ -1237,13 +1215,7 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
pipe_ctx->stream_res.stream_enc->id, pipe_ctx->stream_res.stream_enc->id,
false); false);
} }
#else
if (link_enc)
link_enc->funcs->connect_dig_be_to_fe(
link->link_enc,
pipe_ctx->stream_res.stream_enc->id,
false);
#endif
if (dc_is_dp_signal(pipe_ctx->stream->signal)) if (dc_is_dp_signal(pipe_ctx->stream->signal))
dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DISCONNECT_DIG_FE_BE); dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DISCONNECT_DIG_FE_BE);
...@@ -1285,15 +1257,11 @@ void dce110_blank_stream(struct pipe_ctx *pipe_ctx) ...@@ -1285,15 +1257,11 @@ void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
link->dc->hwss.set_abm_immediate_disable(pipe_ctx); link->dc->hwss.set_abm_immediate_disable(pipe_ctx);
} }
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (is_dp_128b_132b_signal(pipe_ctx)) { if (is_dp_128b_132b_signal(pipe_ctx)) {
/* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_blank( pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_blank(
pipe_ctx->stream_res.hpo_dp_stream_enc); pipe_ctx->stream_res.hpo_dp_stream_enc);
} else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
#else
if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
#endif
pipe_ctx->stream_res.stream_enc->funcs->dp_blank(link, pipe_ctx->stream_res.stream_enc); pipe_ctx->stream_res.stream_enc->funcs->dp_blank(link, pipe_ctx->stream_res.stream_enc);
if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) { if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) {
...@@ -1535,7 +1503,6 @@ static enum dc_status apply_single_controller_ctx_to_hw( ...@@ -1535,7 +1503,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
build_audio_output(context, pipe_ctx, &audio_output); build_audio_output(context, pipe_ctx, &audio_output);
if (dc_is_dp_signal(pipe_ctx->stream->signal)) if (dc_is_dp_signal(pipe_ctx->stream->signal))
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (is_dp_128b_132b_signal(pipe_ctx)) if (is_dp_128b_132b_signal(pipe_ctx))
pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_setup( pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_setup(
pipe_ctx->stream_res.hpo_dp_stream_enc, pipe_ctx->stream_res.hpo_dp_stream_enc,
...@@ -1546,12 +1513,6 @@ static enum dc_status apply_single_controller_ctx_to_hw( ...@@ -1546,12 +1513,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
pipe_ctx->stream_res.stream_enc, pipe_ctx->stream_res.stream_enc,
pipe_ctx->stream_res.audio->inst, pipe_ctx->stream_res.audio->inst,
&pipe_ctx->stream->audio_info); &pipe_ctx->stream->audio_info);
#else
pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(
pipe_ctx->stream_res.stream_enc,
pipe_ctx->stream_res.audio->inst,
&pipe_ctx->stream->audio_info);
#endif
else else
pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup( pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup(
pipe_ctx->stream_res.stream_enc, pipe_ctx->stream_res.stream_enc,
...@@ -1570,14 +1531,12 @@ static enum dc_status apply_single_controller_ctx_to_hw( ...@@ -1570,14 +1531,12 @@ static enum dc_status apply_single_controller_ctx_to_hw(
if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic) if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic)
check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx); check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx);
#if defined(CONFIG_DRM_AMD_DC_DCN)
/* DCN3.1 FPGA Workaround /* DCN3.1 FPGA Workaround
* Need to enable HPO DP Stream Encoder before setting OTG master enable. * Need to enable HPO DP Stream Encoder before setting OTG master enable.
* To do so, move calling function enable_stream_timing to only be done AFTER calling * To do so, move calling function enable_stream_timing to only be done AFTER calling
* function core_link_enable_stream * function core_link_enable_stream
*/ */
if (!(hws->wa.dp_hpo_and_otg_sequence && is_dp_128b_132b_signal(pipe_ctx))) if (!(hws->wa.dp_hpo_and_otg_sequence && is_dp_128b_132b_signal(pipe_ctx)))
#endif
/* */ /* */
/* Do not touch stream timing on seamless boot optimization. */ /* Do not touch stream timing on seamless boot optimization. */
if (!pipe_ctx->stream->apply_seamless_boot_optimization) if (!pipe_ctx->stream->apply_seamless_boot_optimization)
...@@ -1643,7 +1602,6 @@ static enum dc_status apply_single_controller_ctx_to_hw( ...@@ -1643,7 +1602,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
if (!stream->dpms_off) if (!stream->dpms_off)
core_link_enable_stream(context, pipe_ctx); core_link_enable_stream(context, pipe_ctx);
#if defined(CONFIG_DRM_AMD_DC_DCN)
/* DCN3.1 FPGA Workaround /* DCN3.1 FPGA Workaround
* Need to enable HPO DP Stream Encoder before setting OTG master enable. * Need to enable HPO DP Stream Encoder before setting OTG master enable.
* To do so, move calling function enable_stream_timing to only be done AFTER calling * To do so, move calling function enable_stream_timing to only be done AFTER calling
...@@ -1653,7 +1611,6 @@ static enum dc_status apply_single_controller_ctx_to_hw( ...@@ -1653,7 +1611,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
if (!pipe_ctx->stream->apply_seamless_boot_optimization) if (!pipe_ctx->stream->apply_seamless_boot_optimization)
hws->funcs.enable_stream_timing(pipe_ctx, context, dc); hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
} }
#endif
pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
...@@ -2233,8 +2190,6 @@ static void dce110_setup_audio_dto( ...@@ -2233,8 +2190,6 @@ static void dce110_setup_audio_dto(
build_audio_output(context, pipe_ctx, &audio_output); build_audio_output(context, pipe_ctx, &audio_output);
#if defined(CONFIG_DRM_AMD_DC_DCN)
/* For DCN3.1, audio to HPO FRL encoder is using audio DTBCLK DTO */
if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) { if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {
/* disable audio DTBCLK DTO */ /* disable audio DTBCLK DTO */
dc->res_pool->dccg->funcs->set_audio_dtbclk_dto( dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(
...@@ -2251,13 +2206,6 @@ static void dce110_setup_audio_dto( ...@@ -2251,13 +2206,6 @@ static void dce110_setup_audio_dto(
pipe_ctx->stream->signal, pipe_ctx->stream->signal,
&audio_output.crtc_info, &audio_output.crtc_info,
&audio_output.pll_info); &audio_output.pll_info);
#else
pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
pipe_ctx->stream_res.audio,
pipe_ctx->stream->signal,
&audio_output.crtc_info,
&audio_output.pll_info);
#endif
break; break;
} }
} }
......
drivers/gpu/drm/amd/display/dc/inc/core_types.h
View file @ d9eb8fea
...@@ -249,12 +249,10 @@ struct resource_pool { ...@@ -249,12 +249,10 @@ struct resource_pool {
/* Number of USB4 DPIA (DisplayPort Input Adapter) link objects created.*/ /* Number of USB4 DPIA (DisplayPort Input Adapter) link objects created.*/
unsigned int usb4_dpia_count; unsigned int usb4_dpia_count;
#if defined(CONFIG_DRM_AMD_DC_DCN)
unsigned int hpo_dp_stream_enc_count; unsigned int hpo_dp_stream_enc_count;
struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS]; struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS];
unsigned int hpo_dp_link_enc_count; unsigned int hpo_dp_link_enc_count;
struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS]; struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS];
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN) #if defined(CONFIG_DRM_AMD_DC_DCN)
struct dc_3dlut *mpc_lut[MAX_PIPES]; struct dc_3dlut *mpc_lut[MAX_PIPES];
struct dc_transfer_func *mpc_shaper[MAX_PIPES]; struct dc_transfer_func *mpc_shaper[MAX_PIPES];
...@@ -307,9 +305,7 @@ struct stream_resource { ...@@ -307,9 +305,7 @@ struct stream_resource {
struct display_stream_compressor *dsc; struct display_stream_compressor *dsc;
struct timing_generator *tg; struct timing_generator *tg;
struct stream_encoder *stream_enc; struct stream_encoder *stream_enc;
#if defined(CONFIG_DRM_AMD_DC_DCN)
struct hpo_dp_stream_encoder *hpo_dp_stream_enc; struct hpo_dp_stream_encoder *hpo_dp_stream_enc;
#endif
struct audio *audio; struct audio *audio;
struct pixel_clk_params pix_clk_params; struct pixel_clk_params pix_clk_params;
...@@ -334,18 +330,12 @@ struct plane_resource { ...@@ -334,18 +330,12 @@ struct plane_resource {
struct dcn_fe_bandwidth bw; struct dcn_fe_bandwidth bw;
}; };
#if defined(CONFIG_DRM_AMD_DC_DCN)
#define LINK_RES_HPO_DP_REC_MAP__MASK 0xFFFF #define LINK_RES_HPO_DP_REC_MAP__MASK 0xFFFF
#define LINK_RES_HPO_DP_REC_MAP__SHIFT 0 #define LINK_RES_HPO_DP_REC_MAP__SHIFT 0
#endif
/* all mappable hardware resources used to enable a link */ /* all mappable hardware resources used to enable a link */
struct link_resource { struct link_resource {
#if defined(CONFIG_DRM_AMD_DC_DCN)
struct hpo_dp_link_encoder *hpo_dp_link_enc; struct hpo_dp_link_encoder *hpo_dp_link_enc;
#else
void *dummy;
#endif
}; };
union pipe_update_flags { union pipe_update_flags {
...@@ -425,11 +415,9 @@ struct resource_context { ...@@ -425,11 +415,9 @@ struct resource_context {
uint8_t dp_clock_source_ref_count; uint8_t dp_clock_source_ref_count;
bool is_dsc_acquired[MAX_PIPES]; bool is_dsc_acquired[MAX_PIPES];
struct link_enc_cfg_context link_enc_cfg_ctx; struct link_enc_cfg_context link_enc_cfg_ctx;
#if defined(CONFIG_DRM_AMD_DC_DCN)
bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS]; bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS];
unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS]; unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS];
int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS]; int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS];
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN) #if defined(CONFIG_DRM_AMD_DC_DCN)
bool is_mpc_3dlut_acquired[MAX_PIPES]; bool is_mpc_3dlut_acquired[MAX_PIPES];
#endif #endif
......
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
View file @ d9eb8fea
...@@ -79,7 +79,7 @@ struct dccg_funcs { ...@@ -79,7 +79,7 @@ struct dccg_funcs {
void (*otg_drop_pixel)(struct dccg *dccg, void (*otg_drop_pixel)(struct dccg *dccg,
uint32_t otg_inst); uint32_t otg_inst);
void (*dccg_init)(struct dccg *dccg); void (*dccg_init)(struct dccg *dccg);
#if defined(CONFIG_DRM_AMD_DC_DCN)
void (*set_dpstreamclk)( void (*set_dpstreamclk)(
struct dccg *dccg, struct dccg *dccg,
enum hdmistreamclk_source src, enum hdmistreamclk_source src,
...@@ -102,7 +102,7 @@ struct dccg_funcs { ...@@ -102,7 +102,7 @@ struct dccg_funcs {
void (*disable_symclk32_le)( void (*disable_symclk32_le)(
struct dccg *dccg, struct dccg *dccg,
int hpo_le_inst); int hpo_le_inst);
#endif
void (*set_physymclk)( void (*set_physymclk)(
struct dccg *dccg, struct dccg *dccg,
int phy_inst, int phy_inst,
......
drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
View file @ d9eb8fea
...@@ -38,10 +38,8 @@ ...@@ -38,10 +38,8 @@
#define MAX_PIPES 6 #define MAX_PIPES 6
#define MAX_DIG_LINK_ENCODERS 7 #define MAX_DIG_LINK_ENCODERS 7
#define MAX_DWB_PIPES 1 #define MAX_DWB_PIPES 1
#if defined(CONFIG_DRM_AMD_DC_DCN)
#define MAX_HPO_DP2_ENCODERS 4 #define MAX_HPO_DP2_ENCODERS 4
#define MAX_HPO_DP2_LINK_ENCODERS 2 #define MAX_HPO_DP2_LINK_ENCODERS 2
#endif
struct gamma_curve { struct gamma_curve {
uint32_t offset; uint32_t offset;
......
drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
View file @ d9eb8fea
...@@ -220,7 +220,6 @@ enum link_enc_cfg_mode { ...@@ -220,7 +220,6 @@ enum link_enc_cfg_mode {
LINK_ENC_CFG_TRANSIENT /* During commit state - use state to be committed. */ LINK_ENC_CFG_TRANSIENT /* During commit state - use state to be committed. */
}; };
#if defined(CONFIG_DRM_AMD_DC_DCN)
enum dp2_link_mode { enum dp2_link_mode {
DP2_LINK_TRAINING_TPS1, DP2_LINK_TRAINING_TPS1,
DP2_LINK_TRAINING_TPS2, DP2_LINK_TRAINING_TPS2,
...@@ -306,6 +305,5 @@ struct hpo_dp_link_encoder_funcs { ...@@ -306,6 +305,5 @@ struct hpo_dp_link_encoder_funcs {
const struct dc_link_settings *link_settings, const struct dc_link_settings *link_settings,
uint8_t ffe_preset); uint8_t ffe_preset);
}; };
#endif
#endif /* LINK_ENCODER_H_ */ #endif /* LINK_ENCODER_H_ */
drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
View file @ d9eb8fea
...@@ -249,7 +249,6 @@ struct stream_encoder_funcs { ...@@ -249,7 +249,6 @@ struct stream_encoder_funcs {
struct stream_encoder *enc); struct stream_encoder *enc);
}; };
#if defined(CONFIG_DRM_AMD_DC_DCN)
struct hpo_dp_stream_encoder_state { struct hpo_dp_stream_encoder_state {
uint32_t stream_enc_enabled; uint32_t stream_enc_enabled;
uint32_t vid_stream_enabled; uint32_t vid_stream_enabled;
...@@ -329,6 +328,5 @@ struct hpo_dp_stream_encoder_funcs { ...@@ -329,6 +328,5 @@ struct hpo_dp_stream_encoder_funcs {
struct hpo_dp_stream_encoder *enc, struct hpo_dp_stream_encoder *enc,
struct hpo_dp_stream_encoder_state *state); struct hpo_dp_stream_encoder_state *state);
}; };
#endif
#endif /* STREAM_ENCODER_H_ */ #endif /* STREAM_ENCODER_H_ */
drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
View file @ d9eb8fea
...@@ -100,9 +100,7 @@ enum crc_selection { ...@@ -100,9 +100,7 @@ enum crc_selection {
enum otg_out_mux_dest { enum otg_out_mux_dest {
OUT_MUX_DIO = 0, OUT_MUX_DIO = 0,
#if defined(CONFIG_DRM_AMD_DC_DCN)
OUT_MUX_HPO_DP = 2, OUT_MUX_HPO_DP = 2,
#endif
}; };
enum h_timing_div_mode { enum h_timing_div_mode {
......
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
View file @ d9eb8fea
...@@ -41,9 +41,7 @@ struct dce_hwseq_wa { ...@@ -41,9 +41,7 @@ struct dce_hwseq_wa {
bool DEGVIDCN10_254; bool DEGVIDCN10_254;
bool DEGVIDCN21; bool DEGVIDCN21;
bool disallow_self_refresh_during_multi_plane_transition; bool disallow_self_refresh_during_multi_plane_transition;
#if defined(CONFIG_DRM_AMD_DC_DCN)
bool dp_hpo_and_otg_sequence; bool dp_hpo_and_otg_sequence;
#endif
}; };
struct hwseq_wa_state { struct hwseq_wa_state {
......
drivers/gpu/drm/amd/display/dc/inc/resource.h
View file @ d9eb8fea
...@@ -54,10 +54,8 @@ struct resource_caps { ...@@ -54,10 +54,8 @@ struct resource_caps {
int num_dsc; int num_dsc;
unsigned int num_dig_link_enc; // Total number of DIGs (digital encoders) in DIO (Display Input/Output). unsigned int num_dig_link_enc; // Total number of DIGs (digital encoders) in DIO (Display Input/Output).
unsigned int num_usb4_dpia; // Total number of USB4 DPIA (DisplayPort Input Adapters). unsigned int num_usb4_dpia; // Total number of USB4 DPIA (DisplayPort Input Adapters).
#if defined(CONFIG_DRM_AMD_DC_DCN)
int num_hpo_dp_stream_encoder; int num_hpo_dp_stream_encoder;
int num_hpo_dp_link_encoder; int num_hpo_dp_link_encoder;
#endif
int num_mpc_3dlut; int num_mpc_3dlut;
}; };
...@@ -77,14 +75,12 @@ struct resource_create_funcs { ...@@ -77,14 +75,12 @@ struct resource_create_funcs {
struct stream_encoder *(*create_stream_encoder)( struct stream_encoder *(*create_stream_encoder)(
enum engine_id eng_id, struct dc_context *ctx); enum engine_id eng_id, struct dc_context *ctx);
#if defined(CONFIG_DRM_AMD_DC_DCN)
struct hpo_dp_stream_encoder *(*create_hpo_dp_stream_encoder)( struct hpo_dp_stream_encoder *(*create_hpo_dp_stream_encoder)(
enum engine_id eng_id, struct dc_context *ctx); enum engine_id eng_id, struct dc_context *ctx);
struct hpo_dp_link_encoder *(*create_hpo_dp_link_encoder)( struct hpo_dp_link_encoder *(*create_hpo_dp_link_encoder)(
uint8_t inst, uint8_t inst,
struct dc_context *ctx); struct dc_context *ctx);
#endif
struct dce_hwseq *(*create_hwseq)( struct dce_hwseq *(*create_hwseq)(
struct dc_context *ctx); struct dc_context *ctx);
...@@ -205,12 +201,10 @@ int get_num_mpc_splits(struct pipe_ctx *pipe); ...@@ -205,12 +201,10 @@ int get_num_mpc_splits(struct pipe_ctx *pipe);
int get_num_odm_splits(struct pipe_ctx *pipe); int get_num_odm_splits(struct pipe_ctx *pipe);
#if defined(CONFIG_DRM_AMD_DC_DCN)
struct hpo_dp_link_encoder *resource_get_hpo_dp_link_enc_for_det_lt( struct hpo_dp_link_encoder *resource_get_hpo_dp_link_enc_for_det_lt(
const struct resource_context *res_ctx, const struct resource_context *res_ctx,
const struct resource_pool *pool, const struct resource_pool *pool,
const struct dc_link *link); const struct dc_link *link);
#endif
void reset_syncd_pipes_from_disabled_pipes(struct dc *dc, void reset_syncd_pipes_from_disabled_pipes(struct dc *dc,
struct dc_state *context); struct dc_state *context);
......
drivers/gpu/drm/amd/display/include/bios_parser_types.h
View file @ d9eb8fea
...@@ -152,10 +152,8 @@ struct bp_transmitter_control { ...@@ -152,10 +152,8 @@ struct bp_transmitter_control {
enum signal_type signal; enum signal_type signal;
enum dc_color_depth color_depth; /* not used for DCE6.0 */ enum dc_color_depth color_depth; /* not used for DCE6.0 */
enum hpd_source_id hpd_sel; /* ucHPDSel, used for DCe6.0 */ enum hpd_source_id hpd_sel; /* ucHPDSel, used for DCe6.0 */
#if defined(CONFIG_DRM_AMD_DC_DCN)
enum tx_ffe_id txffe_sel; /* used for DCN3 */ enum tx_ffe_id txffe_sel; /* used for DCN3 */
enum engine_id hpo_engine_id; /* used for DCN3 */ enum engine_id hpo_engine_id; /* used for DCN3 */
#endif
struct graphics_object_id connector_obj_id; struct graphics_object_id connector_obj_id;
/* symClock; in 10kHz, pixel clock, in HDMI deep color mode, it should /* symClock; in 10kHz, pixel clock, in HDMI deep color mode, it should
* be pixel clock * deep_color_ratio (in KHz) * be pixel clock * deep_color_ratio (in KHz)
......
drivers/gpu/drm/amd/display/include/dpcd_defs.h
View file @ d9eb8fea
...@@ -144,14 +144,10 @@ enum dpcd_training_patterns { ...@@ -144,14 +144,10 @@ enum dpcd_training_patterns {
DPCD_TRAINING_PATTERN_1, DPCD_TRAINING_PATTERN_1,
DPCD_TRAINING_PATTERN_2, DPCD_TRAINING_PATTERN_2,
DPCD_TRAINING_PATTERN_3, DPCD_TRAINING_PATTERN_3,
#if defined(CONFIG_DRM_AMD_DC_DCN)
DPCD_TRAINING_PATTERN_4 = 7, DPCD_TRAINING_PATTERN_4 = 7,
DPCD_128b_132b_TPS1 = 1, DPCD_128b_132b_TPS1 = 1,
DPCD_128b_132b_TPS2 = 2, DPCD_128b_132b_TPS2 = 2,
DPCD_128b_132b_TPS2_CDS = 3, DPCD_128b_132b_TPS2_CDS = 3,
#else
DPCD_TRAINING_PATTERN_4 = 7
#endif
}; };
/* This enum is for use with PsrSinkPsrStatus.bits.sinkSelfRefreshStatus /* This enum is for use with PsrSinkPsrStatus.bits.sinkSelfRefreshStatus
......
drivers/gpu/drm/amd/display/include/grph_object_defs.h
View file @ d9eb8fea
...@@ -140,7 +140,6 @@ enum sync_source { ...@@ -140,7 +140,6 @@ enum sync_source {
SYNC_SOURCE_DUAL_GPU_PIN SYNC_SOURCE_DUAL_GPU_PIN
}; };
#if defined(CONFIG_DRM_AMD_DC_DCN)
enum tx_ffe_id { enum tx_ffe_id {
TX_FFE0 = 0, TX_FFE0 = 0,
TX_FFE1, TX_FFE1,
...@@ -150,7 +149,6 @@ enum tx_ffe_id { ...@@ -150,7 +149,6 @@ enum tx_ffe_id {
TX_FFE_PreShoot_Only, TX_FFE_PreShoot_Only,
TX_FFE_No_FFE, TX_FFE_No_FFE,
}; };
#endif
/* connector sizes in millimeters - from BiosParserTypes.hpp */ /* connector sizes in millimeters - from BiosParserTypes.hpp */
#define CONNECTOR_SIZE_DVI 40 #define CONNECTOR_SIZE_DVI 40
......
drivers/gpu/drm/amd/display/include/grph_object_id.h
View file @ d9eb8fea
...@@ -184,14 +184,12 @@ enum engine_id { ...@@ -184,14 +184,12 @@ enum engine_id {
ENGINE_ID_DACA, ENGINE_ID_DACA,
ENGINE_ID_DACB, ENGINE_ID_DACB,
ENGINE_ID_VCE, /* wireless display pseudo-encoder */ ENGINE_ID_VCE, /* wireless display pseudo-encoder */
#if defined(CONFIG_DRM_AMD_DC_DCN)
ENGINE_ID_HPO_0, ENGINE_ID_HPO_0,
ENGINE_ID_HPO_1, ENGINE_ID_HPO_1,
ENGINE_ID_HPO_DP_0, ENGINE_ID_HPO_DP_0,
ENGINE_ID_HPO_DP_1, ENGINE_ID_HPO_DP_1,
ENGINE_ID_HPO_DP_2, ENGINE_ID_HPO_DP_2,
ENGINE_ID_HPO_DP_3, ENGINE_ID_HPO_DP_3,
#endif
ENGINE_ID_VIRTUAL, ENGINE_ID_VIRTUAL,
ENGINE_ID_COUNT, ENGINE_ID_COUNT,
......
drivers/gpu/drm/amd/display/include/link_service_types.h
View file @ d9eb8fea
...@@ -74,12 +74,10 @@ enum link_training_result { ...@@ -74,12 +74,10 @@ enum link_training_result {
LINK_TRAINING_LINK_LOSS, LINK_TRAINING_LINK_LOSS,
/* Abort link training (because sink unplugged) */ /* Abort link training (because sink unplugged) */
LINK_TRAINING_ABORT, LINK_TRAINING_ABORT,
#if defined(CONFIG_DRM_AMD_DC_DCN)
DP_128b_132b_LT_FAILED, DP_128b_132b_LT_FAILED,
DP_128b_132b_MAX_LOOP_COUNT_REACHED, DP_128b_132b_MAX_LOOP_COUNT_REACHED,
DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT, DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT,
DP_128b_132b_CDS_DONE_TIMEOUT, DP_128b_132b_CDS_DONE_TIMEOUT,
#endif
}; };
enum lttpr_mode { enum lttpr_mode {
...@@ -99,23 +97,19 @@ struct link_training_settings { ...@@ -99,23 +97,19 @@ struct link_training_settings {
enum dc_pre_emphasis *pre_emphasis; enum dc_pre_emphasis *pre_emphasis;
enum dc_post_cursor2 *post_cursor2; enum dc_post_cursor2 *post_cursor2;
bool should_set_fec_ready; bool should_set_fec_ready;
#if defined(CONFIG_DRM_AMD_DC_DCN)
/* TODO - factor lane_settings out because it changes during LT */ /* TODO - factor lane_settings out because it changes during LT */
union dc_dp_ffe_preset *ffe_preset; union dc_dp_ffe_preset *ffe_preset;
#endif
uint16_t cr_pattern_time; uint16_t cr_pattern_time;
uint16_t eq_pattern_time; uint16_t eq_pattern_time;
uint16_t cds_pattern_time; uint16_t cds_pattern_time;
enum dc_dp_training_pattern pattern_for_cr; enum dc_dp_training_pattern pattern_for_cr;
enum dc_dp_training_pattern pattern_for_eq; enum dc_dp_training_pattern pattern_for_eq;
#if defined(CONFIG_DRM_AMD_DC_DCN)
enum dc_dp_training_pattern pattern_for_cds; enum dc_dp_training_pattern pattern_for_cds;
uint32_t eq_wait_time_limit; uint32_t eq_wait_time_limit;
uint8_t eq_loop_count_limit; uint8_t eq_loop_count_limit;
uint32_t cds_wait_time_limit; uint32_t cds_wait_time_limit;
#endif
bool enhanced_framing; bool enhanced_framing;
enum lttpr_mode lttpr_mode; enum lttpr_mode lttpr_mode;
...@@ -161,7 +155,6 @@ enum dp_test_pattern { ...@@ -161,7 +155,6 @@ enum dp_test_pattern {
DP_TEST_PATTERN_CP2520_2, DP_TEST_PATTERN_CP2520_2,
DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE = DP_TEST_PATTERN_CP2520_2, DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE = DP_TEST_PATTERN_CP2520_2,
DP_TEST_PATTERN_CP2520_3, DP_TEST_PATTERN_CP2520_3,
#if defined(CONFIG_DRM_AMD_DC_DCN)
DP_TEST_PATTERN_128b_132b_TPS1, DP_TEST_PATTERN_128b_132b_TPS1,
DP_TEST_PATTERN_128b_132b_TPS2, DP_TEST_PATTERN_128b_132b_TPS2,
DP_TEST_PATTERN_PRBS9, DP_TEST_PATTERN_PRBS9,
...@@ -171,20 +164,15 @@ enum dp_test_pattern { ...@@ -171,20 +164,15 @@ enum dp_test_pattern {
DP_TEST_PATTERN_PRBS31, DP_TEST_PATTERN_PRBS31,
DP_TEST_PATTERN_264BIT_CUSTOM, DP_TEST_PATTERN_264BIT_CUSTOM,
DP_TEST_PATTERN_SQUARE_PULSE, DP_TEST_PATTERN_SQUARE_PULSE,
#endif
/* Link Training Patterns */ /* Link Training Patterns */
DP_TEST_PATTERN_TRAINING_PATTERN1, DP_TEST_PATTERN_TRAINING_PATTERN1,
DP_TEST_PATTERN_TRAINING_PATTERN2, DP_TEST_PATTERN_TRAINING_PATTERN2,
DP_TEST_PATTERN_TRAINING_PATTERN3, DP_TEST_PATTERN_TRAINING_PATTERN3,
DP_TEST_PATTERN_TRAINING_PATTERN4, DP_TEST_PATTERN_TRAINING_PATTERN4,
#if defined(CONFIG_DRM_AMD_DC_DCN)
DP_TEST_PATTERN_128b_132b_TPS1_TRAINING_MODE, DP_TEST_PATTERN_128b_132b_TPS1_TRAINING_MODE,
DP_TEST_PATTERN_128b_132b_TPS2_TRAINING_MODE, DP_TEST_PATTERN_128b_132b_TPS2_TRAINING_MODE,
DP_TEST_PATTERN_PHY_PATTERN_END = DP_TEST_PATTERN_128b_132b_TPS2_TRAINING_MODE, DP_TEST_PATTERN_PHY_PATTERN_END = DP_TEST_PATTERN_128b_132b_TPS2_TRAINING_MODE,
#else
DP_TEST_PATTERN_PHY_PATTERN_END = DP_TEST_PATTERN_TRAINING_PATTERN4,
#endif
/* link test patterns*/ /* link test patterns*/
DP_TEST_PATTERN_COLOR_SQUARES, DP_TEST_PATTERN_COLOR_SQUARES,
......
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