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Commit da32cc90 authored by Dave Airlie's avatar Dave Airlie
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Merge tag 'drm-intel-next-2013-11-29' of... 

Merge tag 'drm-intel-next-2013-11-29' of git://people.freedesktop.org/~danvet/drm-intel into drm-next

- some more ppgtt prep patches from Ben
- a few fbc fixes from Ville
- power well rework from Imre
- vlv forcewake improvements from Deepak S, Ville and Jesse
- a few smaller things all over

[airlied: fixup forwcewake conflict]
* tag 'drm-intel-next-2013-11-29' of git://people.freedesktop.org/~danvet/drm-intel: (97 commits)
  drm/i915: Fix port name in vlv_wait_port_ready() timeout warning
  drm/i915: Return a drm_mode_status enum in the mode_valid vfuncs
  drm/i915: add intel_display_power_enabled_sw() for use in atomic ctx
  drm/i915: drop DRM_ERROR in intel_fbdev init
  drm/i915/vlv: use parallel context restore when coming out of RC6
  drm/i915/vlv: use a lower RC6 timeout on VLV
  drm/i915/sdvo: Fix up debug output to not split lines
  drm/i915: make sparse happy for the new vlv mmio read function
  drm/i915: drop the right force-wake engine in the vlv mmio funcs
  drm/i915: Fix GT wake FIFO free entries for VLV
  drm/i915: Report all GTFIFODBG errors
  drm/i915: Enabling DebugFS for valleyview forcewake counts
  drm/i915/vlv: Valleyview support for forcewake Individual power wells.
  drm/i915: Add power well arguments to force wake routines.
  drm/i915: Do not attempt to re-enable an unconnected primary plane
  drm/i915: add a debugfs entry for power domain info
  drm/i915: add a default always-on power well
  drm/i915: don't do BDW/HSW specific powerdomains init on other platforms
  drm/i915: protect HSW power well check with IS_HASWELL in redisable_vga
  drm/i915: use IS_HASWELL/BROADWELL instead of HAS_POWER_WELL
  ...

Conflicts:
	drivers/gpu/drm/i915/intel_display.c
parents 319e2e3f be46ffd4
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Showing with 2088 additions and 1184 deletions
drivers/char/Makefile
View file @ da32cc90
...@@ -50,7 +50,7 @@ obj-$(CONFIG_GPIO_TB0219) += tb0219.o ...@@ -50,7 +50,7 @@ obj-$(CONFIG_GPIO_TB0219) += tb0219.o
obj-$(CONFIG_TELCLOCK) += tlclk.o obj-$(CONFIG_TELCLOCK) += tlclk.o
obj-$(CONFIG_MWAVE) += mwave/ obj-$(CONFIG_MWAVE) += mwave/
obj-$(CONFIG_AGP) += agp/ obj-y += agp/
obj-$(CONFIG_PCMCIA) += pcmcia/ obj-$(CONFIG_PCMCIA) += pcmcia/
obj-$(CONFIG_HANGCHECK_TIMER) += hangcheck-timer.o obj-$(CONFIG_HANGCHECK_TIMER) += hangcheck-timer.o
......
drivers/char/agp/Kconfig
View file @ da32cc90
...@@ -68,6 +68,7 @@ config AGP_AMD64 ...@@ -68,6 +68,7 @@ config AGP_AMD64
config AGP_INTEL config AGP_INTEL
tristate "Intel 440LX/BX/GX, I8xx and E7x05 chipset support" tristate "Intel 440LX/BX/GX, I8xx and E7x05 chipset support"
depends on AGP && X86 depends on AGP && X86
select INTEL_GTT
help help
This option gives you AGP support for the GLX component of X This option gives you AGP support for the GLX component of X
on Intel 440LX/BX/GX, 815, 820, 830, 840, 845, 850, 860, 875, on Intel 440LX/BX/GX, 815, 820, 830, 840, 845, 850, 860, 875,
...@@ -155,3 +156,7 @@ config AGP_SGI_TIOCA ...@@ -155,3 +156,7 @@ config AGP_SGI_TIOCA
This option gives you AGP GART support for the SGI TIO chipset This option gives you AGP GART support for the SGI TIO chipset
for IA64 processors. for IA64 processors.
config INTEL_GTT
tristate
depends on X86 && PCI
drivers/char/agp/Makefile
View file @ da32cc90
...@@ -13,7 +13,7 @@ obj-$(CONFIG_AGP_HP_ZX1) += hp-agp.o ...@@ -13,7 +13,7 @@ obj-$(CONFIG_AGP_HP_ZX1) += hp-agp.o
obj-$(CONFIG_AGP_PARISC) += parisc-agp.o obj-$(CONFIG_AGP_PARISC) += parisc-agp.o
obj-$(CONFIG_AGP_I460) += i460-agp.o obj-$(CONFIG_AGP_I460) += i460-agp.o
obj-$(CONFIG_AGP_INTEL) += intel-agp.o obj-$(CONFIG_AGP_INTEL) += intel-agp.o
obj-$(CONFIG_AGP_INTEL) += intel-gtt.o obj-$(CONFIG_INTEL_GTT) += intel-gtt.o
obj-$(CONFIG_AGP_NVIDIA) += nvidia-agp.o obj-$(CONFIG_AGP_NVIDIA) += nvidia-agp.o
obj-$(CONFIG_AGP_SGI_TIOCA) += sgi-agp.o obj-$(CONFIG_AGP_SGI_TIOCA) += sgi-agp.o
obj-$(CONFIG_AGP_SIS) += sis-agp.o obj-$(CONFIG_AGP_SIS) += sis-agp.o
......
drivers/char/agp/intel-agp.c
View file @ da32cc90
...@@ -14,9 +14,6 @@ ...@@ -14,9 +14,6 @@
#include "intel-agp.h" #include "intel-agp.h"
#include <drm/intel-gtt.h> #include <drm/intel-gtt.h>
int intel_agp_enabled;
EXPORT_SYMBOL(intel_agp_enabled);
static int intel_fetch_size(void) static int intel_fetch_size(void)
{ {
int i; int i;
...@@ -814,8 +811,6 @@ static int agp_intel_probe(struct pci_dev *pdev, ...@@ -814,8 +811,6 @@ static int agp_intel_probe(struct pci_dev *pdev,
found_gmch: found_gmch:
pci_set_drvdata(pdev, bridge); pci_set_drvdata(pdev, bridge);
err = agp_add_bridge(bridge); err = agp_add_bridge(bridge);
if (!err)
intel_agp_enabled = 1;
return err; return err;
} }
......
drivers/char/agp/intel-gtt.c
View file @ da32cc90
...@@ -94,6 +94,7 @@ static struct _intel_private { ...@@ -94,6 +94,7 @@ static struct _intel_private {
#define IS_IRONLAKE intel_private.driver->is_ironlake #define IS_IRONLAKE intel_private.driver->is_ironlake
#define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable
#if IS_ENABLED(CONFIG_AGP_INTEL)
static int intel_gtt_map_memory(struct page **pages, static int intel_gtt_map_memory(struct page **pages,
unsigned int num_entries, unsigned int num_entries,
struct sg_table *st) struct sg_table *st)
...@@ -168,6 +169,7 @@ static void i8xx_destroy_pages(struct page *page) ...@@ -168,6 +169,7 @@ static void i8xx_destroy_pages(struct page *page)
__free_pages(page, 2); __free_pages(page, 2);
atomic_dec(&agp_bridge->current_memory_agp); atomic_dec(&agp_bridge->current_memory_agp);
} }
#endif
#define I810_GTT_ORDER 4 #define I810_GTT_ORDER 4
static int i810_setup(void) static int i810_setup(void)
...@@ -209,6 +211,7 @@ static void i810_cleanup(void) ...@@ -209,6 +211,7 @@ static void i810_cleanup(void)
free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER); free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER);
} }
#if IS_ENABLED(CONFIG_AGP_INTEL)
static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start, static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start,
int type) int type)
{ {
...@@ -289,6 +292,7 @@ static void intel_i810_free_by_type(struct agp_memory *curr) ...@@ -289,6 +292,7 @@ static void intel_i810_free_by_type(struct agp_memory *curr)
} }
kfree(curr); kfree(curr);
} }
#endif
static int intel_gtt_setup_scratch_page(void) static int intel_gtt_setup_scratch_page(void)
{ {
...@@ -647,7 +651,9 @@ static int intel_gtt_init(void) ...@@ -647,7 +651,9 @@ static int intel_gtt_init(void)
return -ENOMEM; return -ENOMEM;
} }
#if IS_ENABLED(CONFIG_AGP_INTEL)
global_cache_flush(); /* FIXME: ? */ global_cache_flush(); /* FIXME: ? */
#endif
intel_private.stolen_size = intel_gtt_stolen_size(); intel_private.stolen_size = intel_gtt_stolen_size();
...@@ -671,6 +677,7 @@ static int intel_gtt_init(void) ...@@ -671,6 +677,7 @@ static int intel_gtt_init(void)
return 0; return 0;
} }
#if IS_ENABLED(CONFIG_AGP_INTEL)
static int intel_fake_agp_fetch_size(void) static int intel_fake_agp_fetch_size(void)
{ {
int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes); int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
...@@ -689,6 +696,7 @@ static int intel_fake_agp_fetch_size(void) ...@@ -689,6 +696,7 @@ static int intel_fake_agp_fetch_size(void)
return 0; return 0;
} }
#endif
static void i830_cleanup(void) static void i830_cleanup(void)
{ {
...@@ -801,6 +809,7 @@ static int i830_setup(void) ...@@ -801,6 +809,7 @@ static int i830_setup(void)
return 0; return 0;
} }
#if IS_ENABLED(CONFIG_AGP_INTEL)
static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge) static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
{ {
agp_bridge->gatt_table_real = NULL; agp_bridge->gatt_table_real = NULL;
...@@ -825,6 +834,7 @@ static int intel_fake_agp_configure(void) ...@@ -825,6 +834,7 @@ static int intel_fake_agp_configure(void)
return 0; return 0;
} }
#endif
static bool i830_check_flags(unsigned int flags) static bool i830_check_flags(unsigned int flags)
{ {
...@@ -863,6 +873,7 @@ void intel_gtt_insert_sg_entries(struct sg_table *st, ...@@ -863,6 +873,7 @@ void intel_gtt_insert_sg_entries(struct sg_table *st,
} }
EXPORT_SYMBOL(intel_gtt_insert_sg_entries); EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
#if IS_ENABLED(CONFIG_AGP_INTEL)
static void intel_gtt_insert_pages(unsigned int first_entry, static void intel_gtt_insert_pages(unsigned int first_entry,
unsigned int num_entries, unsigned int num_entries,
struct page **pages, struct page **pages,
...@@ -928,6 +939,7 @@ static int intel_fake_agp_insert_entries(struct agp_memory *mem, ...@@ -928,6 +939,7 @@ static int intel_fake_agp_insert_entries(struct agp_memory *mem,
mem->is_flushed = true; mem->is_flushed = true;
return ret; return ret;
} }
#endif
void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
{ {
...@@ -941,6 +953,7 @@ void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) ...@@ -941,6 +953,7 @@ void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
} }
EXPORT_SYMBOL(intel_gtt_clear_range); EXPORT_SYMBOL(intel_gtt_clear_range);
#if IS_ENABLED(CONFIG_AGP_INTEL)
static int intel_fake_agp_remove_entries(struct agp_memory *mem, static int intel_fake_agp_remove_entries(struct agp_memory *mem,
off_t pg_start, int type) off_t pg_start, int type)
{ {
...@@ -982,6 +995,7 @@ static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count, ...@@ -982,6 +995,7 @@ static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
/* always return NULL for other allocation types for now */ /* always return NULL for other allocation types for now */
return NULL; return NULL;
} }
#endif
static int intel_alloc_chipset_flush_resource(void) static int intel_alloc_chipset_flush_resource(void)
{ {
...@@ -1138,6 +1152,7 @@ static int i9xx_setup(void) ...@@ -1138,6 +1152,7 @@ static int i9xx_setup(void)
return 0; return 0;
} }
#if IS_ENABLED(CONFIG_AGP_INTEL)
static const struct agp_bridge_driver intel_fake_agp_driver = { static const struct agp_bridge_driver intel_fake_agp_driver = {
.owner = THIS_MODULE, .owner = THIS_MODULE,
.size_type = FIXED_APER_SIZE, .size_type = FIXED_APER_SIZE,
...@@ -1159,6 +1174,7 @@ static const struct agp_bridge_driver intel_fake_agp_driver = { ...@@ -1159,6 +1174,7 @@ static const struct agp_bridge_driver intel_fake_agp_driver = {
.agp_destroy_page = agp_generic_destroy_page, .agp_destroy_page = agp_generic_destroy_page,
.agp_destroy_pages = agp_generic_destroy_pages, .agp_destroy_pages = agp_generic_destroy_pages,
}; };
#endif
static const struct intel_gtt_driver i81x_gtt_driver = { static const struct intel_gtt_driver i81x_gtt_driver = {
.gen = 1, .gen = 1,
...@@ -1376,11 +1392,13 @@ int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, ...@@ -1376,11 +1392,13 @@ int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
intel_private.refcount++; intel_private.refcount++;
#if IS_ENABLED(CONFIG_AGP_INTEL)
if (bridge) { if (bridge) {
bridge->driver = &intel_fake_agp_driver; bridge->driver = &intel_fake_agp_driver;
bridge->dev_private_data = &intel_private; bridge->dev_private_data = &intel_private;
bridge->dev = bridge_pdev; bridge->dev = bridge_pdev;
} }
#endif
intel_private.bridge_dev = pci_dev_get(bridge_pdev); intel_private.bridge_dev = pci_dev_get(bridge_pdev);
......
drivers/gpu/drm/i915/Kconfig
View file @ da32cc90
config DRM_I915 config DRM_I915
tristate "Intel 8xx/9xx/G3x/G4x/HD Graphics" tristate "Intel 8xx/9xx/G3x/G4x/HD Graphics"
depends on DRM depends on DRM
depends on AGP depends on X86 && PCI
depends on AGP_INTEL depends on (AGP || AGP=n)
select INTEL_GTT
select AGP_INTEL if AGP
# we need shmfs for the swappable backing store, and in particular # we need shmfs for the swappable backing store, and in particular
# the shmem_readpage() which depends upon tmpfs # the shmem_readpage() which depends upon tmpfs
select SHMEM select SHMEM
...@@ -35,15 +37,14 @@ config DRM_I915 ...@@ -35,15 +37,14 @@ config DRM_I915
config DRM_I915_KMS config DRM_I915_KMS
bool "Enable modesetting on intel by default" bool "Enable modesetting on intel by default"
depends on DRM_I915 depends on DRM_I915
default y
help help
Choose this option if you want kernel modesetting enabled by default, Choose this option if you want kernel modesetting enabled by default.
and you have a new enough userspace to support this. Running old
userspaces with this enabled will cause pain. Note that this causes If in doubt, say "Y".
the driver to bind to PCI devices, which precludes loading things
like intelfb.
config DRM_I915_FBDEV config DRM_I915_FBDEV
bool "Enable legacy fbdev support for the modesettting intel driver" bool "Enable legacy fbdev support for the modesetting intel driver"
depends on DRM_I915 depends on DRM_I915
select DRM_KMS_FB_HELPER select DRM_KMS_FB_HELPER
select FB_CFB_FILLRECT select FB_CFB_FILLRECT
...@@ -55,9 +56,12 @@ config DRM_I915_FBDEV ...@@ -55,9 +56,12 @@ config DRM_I915_FBDEV
support. Note that this support also provide the linux console support. Note that this support also provide the linux console
support on top of the intel modesetting driver. support on top of the intel modesetting driver.
If in doubt, say "Y".
config DRM_I915_PRELIMINARY_HW_SUPPORT config DRM_I915_PRELIMINARY_HW_SUPPORT
bool "Enable preliminary support for prerelease Intel hardware by default" bool "Enable preliminary support for prerelease Intel hardware by default"
depends on DRM_I915 depends on DRM_I915
default n
help help
Choose this option if you have prerelease Intel hardware and want the Choose this option if you have prerelease Intel hardware and want the
i915 driver to support it by default. You can enable such support at i915 driver to support it by default. You can enable such support at
...@@ -65,3 +69,15 @@ config DRM_I915_PRELIMINARY_HW_SUPPORT ...@@ -65,3 +69,15 @@ config DRM_I915_PRELIMINARY_HW_SUPPORT
option changes the default for that module option. option changes the default for that module option.
If in doubt, say "N". If in doubt, say "N".
config DRM_I915_UMS
bool "Enable userspace modesetting on Intel hardware (DEPRECATED)"
depends on DRM_I915
default n
help
Choose this option if you still need userspace modesetting.
Userspace modesetting is deprecated for quite some time now, so
enable this only if you have ancient versions of the DDX drivers.
If in doubt, say "N".
drivers/gpu/drm/i915/dvo_ns2501.c
View file @ da32cc90
...@@ -87,49 +87,6 @@ struct ns2501_priv { ...@@ -87,49 +87,6 @@ struct ns2501_priv {
* when switching the resolution. * when switching the resolution.
*/ */
static void enable_dvo(struct intel_dvo_device *dvo)
{
struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv);
struct i2c_adapter *adapter = dvo->i2c_bus;
struct intel_gmbus *bus = container_of(adapter,
struct intel_gmbus,
adapter);
struct drm_i915_private *dev_priv = bus->dev_priv;
DRM_DEBUG_KMS("%s: Trying to re-enable the DVO\n", __FUNCTION__);
ns->dvoc = I915_READ(DVO_C);
ns->pll_a = I915_READ(_DPLL_A);
ns->srcdim = I915_READ(DVOC_SRCDIM);
ns->fw_blc = I915_READ(FW_BLC);
I915_WRITE(DVOC, 0x10004084);
I915_WRITE(_DPLL_A, 0xd0820000);
I915_WRITE(DVOC_SRCDIM, 0x400300); // 1024x768
I915_WRITE(FW_BLC, 0x1080304);
I915_WRITE(DVOC, 0x90004084);
}
/*
* Restore the I915 registers modified by the above
* trigger function.
*/
static void restore_dvo(struct intel_dvo_device *dvo)
{
struct i2c_adapter *adapter = dvo->i2c_bus;
struct intel_gmbus *bus = container_of(adapter,
struct intel_gmbus,
adapter);
struct drm_i915_private *dev_priv = bus->dev_priv;
struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv);
I915_WRITE(DVOC, ns->dvoc);
I915_WRITE(_DPLL_A, ns->pll_a);
I915_WRITE(DVOC_SRCDIM, ns->srcdim);
I915_WRITE(FW_BLC, ns->fw_blc);
}
/* /*
** Read a register from the ns2501. ** Read a register from the ns2501.
** Returns true if successful, false otherwise. ** Returns true if successful, false otherwise.
...@@ -300,7 +257,7 @@ static void ns2501_mode_set(struct intel_dvo_device *dvo, ...@@ -300,7 +257,7 @@ static void ns2501_mode_set(struct intel_dvo_device *dvo,
struct drm_display_mode *adjusted_mode) struct drm_display_mode *adjusted_mode)
{ {
bool ok; bool ok;
bool restore = false; int retries = 10;
struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv); struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv);
DRM_DEBUG_KMS DRM_DEBUG_KMS
...@@ -476,20 +433,7 @@ static void ns2501_mode_set(struct intel_dvo_device *dvo, ...@@ -476,20 +433,7 @@ static void ns2501_mode_set(struct intel_dvo_device *dvo,
ns->reg_8_shadow |= NS2501_8_BPAS; ns->reg_8_shadow |= NS2501_8_BPAS;
} }
ok &= ns2501_writeb(dvo, NS2501_REG8, ns->reg_8_shadow); ok &= ns2501_writeb(dvo, NS2501_REG8, ns->reg_8_shadow);
} while (!ok && retries--);
if (!ok) {
if (restore)
restore_dvo(dvo);
enable_dvo(dvo);
restore = true;
}
} while (!ok);
/*
* Restore the old i915 registers before
* forcing the ns2501 on.
*/
if (restore)
restore_dvo(dvo);
} }
/* set the NS2501 power state */ /* set the NS2501 power state */
...@@ -510,7 +454,7 @@ static bool ns2501_get_hw_state(struct intel_dvo_device *dvo) ...@@ -510,7 +454,7 @@ static bool ns2501_get_hw_state(struct intel_dvo_device *dvo)
static void ns2501_dpms(struct intel_dvo_device *dvo, bool enable) static void ns2501_dpms(struct intel_dvo_device *dvo, bool enable)
{ {
bool ok; bool ok;
bool restore = false; int retries = 10;
struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv); struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv);
unsigned char ch; unsigned char ch;
...@@ -537,16 +481,7 @@ static void ns2501_dpms(struct intel_dvo_device *dvo, bool enable) ...@@ -537,16 +481,7 @@ static void ns2501_dpms(struct intel_dvo_device *dvo, bool enable)
ok &= ok &=
ns2501_writeb(dvo, 0x35, ns2501_writeb(dvo, 0x35,
enable ? 0xff : 0x00); enable ? 0xff : 0x00);
if (!ok) { } while (!ok && retries--);
if (restore)
restore_dvo(dvo);
enable_dvo(dvo);
restore = true;
}
} while (!ok);
if (restore)
restore_dvo(dvo);
} }
} }
......
drivers/gpu/drm/i915/i915_debugfs.c
View file @ da32cc90
This diff is collapsed.
drivers/gpu/drm/i915/i915_dma.c
View file @ da32cc90
...@@ -1486,7 +1486,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) ...@@ -1486,7 +1486,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
spin_lock_init(&dev_priv->irq_lock); spin_lock_init(&dev_priv->irq_lock);
spin_lock_init(&dev_priv->gpu_error.lock); spin_lock_init(&dev_priv->gpu_error.lock);
spin_lock_init(&dev_priv->backlight.lock); spin_lock_init(&dev_priv->backlight_lock);
spin_lock_init(&dev_priv->uncore.lock); spin_lock_init(&dev_priv->uncore.lock);
spin_lock_init(&dev_priv->mm.object_stat_lock); spin_lock_init(&dev_priv->mm.object_stat_lock);
mutex_init(&dev_priv->dpio_lock); mutex_init(&dev_priv->dpio_lock);
...@@ -1639,8 +1639,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) ...@@ -1639,8 +1639,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
goto out_gem_unload; goto out_gem_unload;
} }
if (HAS_POWER_WELL(dev)) intel_power_domains_init(dev);
intel_power_domains_init(dev);
if (drm_core_check_feature(dev, DRIVER_MODESET)) { if (drm_core_check_feature(dev, DRIVER_MODESET)) {
ret = i915_load_modeset_init(dev); ret = i915_load_modeset_init(dev);
...@@ -1667,8 +1666,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) ...@@ -1667,8 +1666,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
return 0; return 0;
out_power_well: out_power_well:
if (HAS_POWER_WELL(dev)) intel_power_domains_remove(dev);
intel_power_domains_remove(dev);
drm_vblank_cleanup(dev); drm_vblank_cleanup(dev);
out_gem_unload: out_gem_unload:
if (dev_priv->mm.inactive_shrinker.scan_objects) if (dev_priv->mm.inactive_shrinker.scan_objects)
...@@ -1706,13 +1704,11 @@ int i915_driver_unload(struct drm_device *dev) ...@@ -1706,13 +1704,11 @@ int i915_driver_unload(struct drm_device *dev)
intel_gpu_ips_teardown(); intel_gpu_ips_teardown();
if (HAS_POWER_WELL(dev)) { /* The i915.ko module is still not prepared to be loaded when
/* The i915.ko module is still not prepared to be loaded when * the power well is not enabled, so just enable it in case
* the power well is not enabled, so just enable it in case * we're going to unload/reload. */
* we're going to unload/reload. */ intel_display_set_init_power(dev, true);
intel_display_set_init_power(dev, true); intel_power_domains_remove(dev);
intel_power_domains_remove(dev);
}
i915_teardown_sysfs(dev); i915_teardown_sysfs(dev);
...@@ -1777,7 +1773,6 @@ int i915_driver_unload(struct drm_device *dev) ...@@ -1777,7 +1773,6 @@ int i915_driver_unload(struct drm_device *dev)
list_del(&dev_priv->gtt.base.global_link); list_del(&dev_priv->gtt.base.global_link);
WARN_ON(!list_empty(&dev_priv->vm_list)); WARN_ON(!list_empty(&dev_priv->vm_list));
drm_mm_takedown(&dev_priv->gtt.base.mm);
drm_vblank_cleanup(dev); drm_vblank_cleanup(dev);
...@@ -1908,6 +1903,7 @@ const struct drm_ioctl_desc i915_ioctls[] = { ...@@ -1908,6 +1903,7 @@ const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
}; };
int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
......
drivers/gpu/drm/i915/i915_drv.c
View file @ da32cc90
...@@ -114,7 +114,7 @@ MODULE_PARM_DESC(enable_hangcheck, ...@@ -114,7 +114,7 @@ MODULE_PARM_DESC(enable_hangcheck,
"(default: true)"); "(default: true)");
int i915_enable_ppgtt __read_mostly = -1; int i915_enable_ppgtt __read_mostly = -1;
module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600); module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0400);
MODULE_PARM_DESC(i915_enable_ppgtt, MODULE_PARM_DESC(i915_enable_ppgtt,
"Enable PPGTT (default: true)"); "Enable PPGTT (default: true)");
...@@ -155,7 +155,6 @@ MODULE_PARM_DESC(prefault_disable, ...@@ -155,7 +155,6 @@ MODULE_PARM_DESC(prefault_disable,
"Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only."); "Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only.");
static struct drm_driver driver; static struct drm_driver driver;
extern int intel_agp_enabled;
static const struct intel_device_info intel_i830_info = { static const struct intel_device_info intel_i830_info = {
.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
...@@ -265,6 +264,7 @@ static const struct intel_device_info intel_ironlake_m_info = { ...@@ -265,6 +264,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
static const struct intel_device_info intel_sandybridge_d_info = { static const struct intel_device_info intel_sandybridge_d_info = {
.gen = 6, .num_pipes = 2, .gen = 6, .num_pipes = 2,
.need_gfx_hws = 1, .has_hotplug = 1, .need_gfx_hws = 1, .has_hotplug = 1,
.has_fbc = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
.has_llc = 1, .has_llc = 1,
}; };
...@@ -280,6 +280,7 @@ static const struct intel_device_info intel_sandybridge_m_info = { ...@@ -280,6 +280,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
#define GEN7_FEATURES \ #define GEN7_FEATURES \
.gen = 7, .num_pipes = 3, \ .gen = 7, .num_pipes = 3, \
.need_gfx_hws = 1, .has_hotplug = 1, \ .need_gfx_hws = 1, .has_hotplug = 1, \
.has_fbc = 1, \
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.has_llc = 1 .has_llc = 1
...@@ -292,7 +293,6 @@ static const struct intel_device_info intel_ivybridge_m_info = { ...@@ -292,7 +293,6 @@ static const struct intel_device_info intel_ivybridge_m_info = {
GEN7_FEATURES, GEN7_FEATURES,
.is_ivybridge = 1, .is_ivybridge = 1,
.is_mobile = 1, .is_mobile = 1,
.has_fbc = 1,
}; };
static const struct intel_device_info intel_ivybridge_q_info = { static const struct intel_device_info intel_ivybridge_q_info = {
...@@ -307,6 +307,7 @@ static const struct intel_device_info intel_valleyview_m_info = { ...@@ -307,6 +307,7 @@ static const struct intel_device_info intel_valleyview_m_info = {
.num_pipes = 2, .num_pipes = 2,
.is_valleyview = 1, .is_valleyview = 1,
.display_mmio_offset = VLV_DISPLAY_BASE, .display_mmio_offset = VLV_DISPLAY_BASE,
.has_fbc = 0, /* legal, last one wins */
.has_llc = 0, /* legal, last one wins */ .has_llc = 0, /* legal, last one wins */
}; };
...@@ -315,6 +316,7 @@ static const struct intel_device_info intel_valleyview_d_info = { ...@@ -315,6 +316,7 @@ static const struct intel_device_info intel_valleyview_d_info = {
.num_pipes = 2, .num_pipes = 2,
.is_valleyview = 1, .is_valleyview = 1,
.display_mmio_offset = VLV_DISPLAY_BASE, .display_mmio_offset = VLV_DISPLAY_BASE,
.has_fbc = 0, /* legal, last one wins */
.has_llc = 0, /* legal, last one wins */ .has_llc = 0, /* legal, last one wins */
}; };
...@@ -332,7 +334,6 @@ static const struct intel_device_info intel_haswell_m_info = { ...@@ -332,7 +334,6 @@ static const struct intel_device_info intel_haswell_m_info = {
.is_mobile = 1, .is_mobile = 1,
.has_ddi = 1, .has_ddi = 1,
.has_fpga_dbg = 1, .has_fpga_dbg = 1,
.has_fbc = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
}; };
...@@ -761,14 +762,14 @@ int i915_reset(struct drm_device *dev) ...@@ -761,14 +762,14 @@ int i915_reset(struct drm_device *dev)
DRM_INFO("Simulated gpu hang, resetting stop_rings\n"); DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
dev_priv->gpu_error.stop_rings = 0; dev_priv->gpu_error.stop_rings = 0;
if (ret == -ENODEV) { if (ret == -ENODEV) {
DRM_ERROR("Reset not implemented, but ignoring " DRM_INFO("Reset not implemented, but ignoring "
"error for simulated gpu hangs\n"); "error for simulated gpu hangs\n");
ret = 0; ret = 0;
} }
} }
if (ret) { if (ret) {
DRM_ERROR("Failed to reset chip.\n"); DRM_ERROR("Failed to reset chip: %i\n", ret);
mutex_unlock(&dev->struct_mutex); mutex_unlock(&dev->struct_mutex);
return ret; return ret;
} }
...@@ -789,12 +790,9 @@ int i915_reset(struct drm_device *dev) ...@@ -789,12 +790,9 @@ int i915_reset(struct drm_device *dev)
*/ */
if (drm_core_check_feature(dev, DRIVER_MODESET) || if (drm_core_check_feature(dev, DRIVER_MODESET) ||
!dev_priv->ums.mm_suspended) { !dev_priv->ums.mm_suspended) {
bool hw_contexts_disabled = dev_priv->hw_contexts_disabled;
dev_priv->ums.mm_suspended = 0; dev_priv->ums.mm_suspended = 0;
ret = i915_gem_init_hw(dev); ret = i915_gem_init_hw(dev);
if (!hw_contexts_disabled && dev_priv->hw_contexts_disabled)
DRM_ERROR("HW contexts didn't survive reset\n");
mutex_unlock(&dev->struct_mutex); mutex_unlock(&dev->struct_mutex);
if (ret) { if (ret) {
DRM_ERROR("Failed hw init on reset %d\n", ret); DRM_ERROR("Failed hw init on reset %d\n", ret);
...@@ -830,17 +828,7 @@ static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) ...@@ -830,17 +828,7 @@ static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
if (PCI_FUNC(pdev->devfn)) if (PCI_FUNC(pdev->devfn))
return -ENODEV; return -ENODEV;
/* We've managed to ship a kms-enabled ddx that shipped with an XvMC driver.driver_features &= ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
* implementation for gen3 (and only gen3) that used legacy drm maps
* (gasp!) to share buffers between X and the client. Hence we need to
* keep around the fake agp stuff for gen3, even when kms is enabled. */
if (intel_info->gen != 3) {
driver.driver_features &=
~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
} else if (!intel_agp_enabled) {
DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
return -ENODEV;
}
return drm_get_pci_dev(pdev, ent, &driver); return drm_get_pci_dev(pdev, ent, &driver);
} }
...@@ -1023,14 +1011,24 @@ static int __init i915_init(void) ...@@ -1023,14 +1011,24 @@ static int __init i915_init(void)
driver.driver_features &= ~DRIVER_MODESET; driver.driver_features &= ~DRIVER_MODESET;
#endif #endif
if (!(driver.driver_features & DRIVER_MODESET)) if (!(driver.driver_features & DRIVER_MODESET)) {
driver.get_vblank_timestamp = NULL; driver.get_vblank_timestamp = NULL;
#ifndef CONFIG_DRM_I915_UMS
/* Silently fail loading to not upset userspace. */
return 0;
#endif
}
return drm_pci_init(&driver, &i915_pci_driver); return drm_pci_init(&driver, &i915_pci_driver);
} }
static void __exit i915_exit(void) static void __exit i915_exit(void)
{ {
#ifndef CONFIG_DRM_I915_UMS
if (!(driver.driver_features & DRIVER_MODESET))
return; /* Never loaded a driver. */
#endif
drm_pci_exit(&driver, &i915_pci_driver); drm_pci_exit(&driver, &i915_pci_driver);
} }
......
drivers/gpu/drm/i915/i915_drv.h
View file @ da32cc90
This diff is collapsed.
drivers/gpu/drm/i915/i915_gem.c
View file @ da32cc90
...@@ -4465,7 +4465,13 @@ i915_gem_init_hw(struct drm_device *dev) ...@@ -4465,7 +4465,13 @@ i915_gem_init_hw(struct drm_device *dev)
* XXX: There was some w/a described somewhere suggesting loading * XXX: There was some w/a described somewhere suggesting loading
* contexts before PPGTT. * contexts before PPGTT.
*/ */
i915_gem_context_init(dev); ret = i915_gem_context_init(dev);
if (ret) {
i915_gem_cleanup_ringbuffer(dev);
DRM_ERROR("Context initialization failed %d\n", ret);
return ret;
}
if (dev_priv->mm.aliasing_ppgtt) { if (dev_priv->mm.aliasing_ppgtt) {
ret = dev_priv->mm.aliasing_ppgtt->enable(dev); ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
if (ret) { if (ret) {
......
drivers/gpu/drm/i915/i915_gem_context.c
View file @ da32cc90
...@@ -247,36 +247,34 @@ static int create_default_context(struct drm_i915_private *dev_priv) ...@@ -247,36 +247,34 @@ static int create_default_context(struct drm_i915_private *dev_priv)
return ret; return ret;
} }
void i915_gem_context_init(struct drm_device *dev) int i915_gem_context_init(struct drm_device *dev)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
int ret;
if (!HAS_HW_CONTEXTS(dev)) { if (!HAS_HW_CONTEXTS(dev))
dev_priv->hw_contexts_disabled = true; return 0;
DRM_DEBUG_DRIVER("Disabling HW Contexts; old hardware\n");
return;
}
/* If called from reset, or thaw... we've been here already */ /* If called from reset, or thaw... we've been here already */
if (dev_priv->hw_contexts_disabled || if (dev_priv->ring[RCS].default_context)
dev_priv->ring[RCS].default_context) return 0;
return;
dev_priv->hw_context_size = round_up(get_context_size(dev), 4096); dev_priv->hw_context_size = round_up(get_context_size(dev), 4096);
if (dev_priv->hw_context_size > (1<<20)) { if (dev_priv->hw_context_size > (1<<20)) {
dev_priv->hw_contexts_disabled = true;
DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size\n"); DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size\n");
return; return -E2BIG;
} }
if (create_default_context(dev_priv)) { ret = create_default_context(dev_priv);
dev_priv->hw_contexts_disabled = true; if (ret) {
DRM_DEBUG_DRIVER("Disabling HW Contexts; create failed\n"); DRM_DEBUG_DRIVER("Disabling HW Contexts; create failed %d\n",
return; ret);
return ret;
} }
DRM_DEBUG_DRIVER("HW context support initialized\n"); DRM_DEBUG_DRIVER("HW context support initialized\n");
return 0;
} }
void i915_gem_context_fini(struct drm_device *dev) void i915_gem_context_fini(struct drm_device *dev)
...@@ -284,7 +282,7 @@ void i915_gem_context_fini(struct drm_device *dev) ...@@ -284,7 +282,7 @@ void i915_gem_context_fini(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
struct i915_hw_context *dctx = dev_priv->ring[RCS].default_context; struct i915_hw_context *dctx = dev_priv->ring[RCS].default_context;
if (dev_priv->hw_contexts_disabled) if (!HAS_HW_CONTEXTS(dev))
return; return;
/* The only known way to stop the gpu from accessing the hw context is /* The only known way to stop the gpu from accessing the hw context is
...@@ -327,16 +325,16 @@ i915_gem_context_get_hang_stats(struct drm_device *dev, ...@@ -327,16 +325,16 @@ i915_gem_context_get_hang_stats(struct drm_device *dev,
struct drm_file *file, struct drm_file *file,
u32 id) u32 id)
{ {
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_i915_file_private *file_priv = file->driver_priv; struct drm_i915_file_private *file_priv = file->driver_priv;
struct i915_hw_context *ctx; struct i915_hw_context *ctx;
if (id == DEFAULT_CONTEXT_ID) if (id == DEFAULT_CONTEXT_ID)
return &file_priv->hang_stats; return &file_priv->hang_stats;
ctx = NULL; if (!HAS_HW_CONTEXTS(dev))
if (!dev_priv->hw_contexts_disabled) return ERR_PTR(-ENOENT);
ctx = i915_gem_context_get(file->driver_priv, id);
ctx = i915_gem_context_get(file->driver_priv, id);
if (ctx == NULL) if (ctx == NULL)
return ERR_PTR(-ENOENT); return ERR_PTR(-ENOENT);
...@@ -494,8 +492,6 @@ static int do_switch(struct i915_hw_context *to) ...@@ -494,8 +492,6 @@ static int do_switch(struct i915_hw_context *to)
* @ring: ring for which we'll execute the context switch * @ring: ring for which we'll execute the context switch
* @file_priv: file_priv associated with the context, may be NULL * @file_priv: file_priv associated with the context, may be NULL
* @id: context id number * @id: context id number
* @seqno: sequence number by which the new context will be switched to
* @flags:
* *
* The context life cycle is simple. The context refcount is incremented and * The context life cycle is simple. The context refcount is incremented and
* decremented by 1 and create and destroy. If the context is in use by the GPU, * decremented by 1 and create and destroy. If the context is in use by the GPU,
...@@ -509,7 +505,7 @@ int i915_switch_context(struct intel_ring_buffer *ring, ...@@ -509,7 +505,7 @@ int i915_switch_context(struct intel_ring_buffer *ring,
struct drm_i915_private *dev_priv = ring->dev->dev_private; struct drm_i915_private *dev_priv = ring->dev->dev_private;
struct i915_hw_context *to; struct i915_hw_context *to;
if (dev_priv->hw_contexts_disabled) if (!HAS_HW_CONTEXTS(ring->dev))
return 0; return 0;
WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
...@@ -534,7 +530,6 @@ int i915_switch_context(struct intel_ring_buffer *ring, ...@@ -534,7 +530,6 @@ int i915_switch_context(struct intel_ring_buffer *ring,
int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
struct drm_file *file) struct drm_file *file)
{ {
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_i915_gem_context_create *args = data; struct drm_i915_gem_context_create *args = data;
struct drm_i915_file_private *file_priv = file->driver_priv; struct drm_i915_file_private *file_priv = file->driver_priv;
struct i915_hw_context *ctx; struct i915_hw_context *ctx;
...@@ -543,7 +538,7 @@ int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, ...@@ -543,7 +538,7 @@ int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
if (!(dev->driver->driver_features & DRIVER_GEM)) if (!(dev->driver->driver_features & DRIVER_GEM))
return -ENODEV; return -ENODEV;
if (dev_priv->hw_contexts_disabled) if (!HAS_HW_CONTEXTS(dev))
return -ENODEV; return -ENODEV;
ret = i915_mutex_lock_interruptible(dev); ret = i915_mutex_lock_interruptible(dev);
......
drivers/gpu/drm/i915/i915_gem_execbuffer.c
View file @ da32cc90
...@@ -46,7 +46,7 @@ struct eb_vmas { ...@@ -46,7 +46,7 @@ struct eb_vmas {
}; };
static struct eb_vmas * static struct eb_vmas *
eb_create(struct drm_i915_gem_execbuffer2 *args, struct i915_address_space *vm) eb_create(struct drm_i915_gem_execbuffer2 *args)
{ {
struct eb_vmas *eb = NULL; struct eb_vmas *eb = NULL;
...@@ -332,7 +332,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, ...@@ -332,7 +332,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
target_i915_obj = target_vma->obj; target_i915_obj = target_vma->obj;
target_obj = &target_vma->obj->base; target_obj = &target_vma->obj->base;
target_offset = i915_gem_obj_ggtt_offset(target_i915_obj); target_offset = target_vma->node.start;
/* Sandybridge PPGTT errata: We need a global gtt mapping for MI and /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
* pipe_control writes because the gpu doesn't properly redirect them * pipe_control writes because the gpu doesn't properly redirect them
...@@ -479,8 +479,7 @@ i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma, ...@@ -479,8 +479,7 @@ i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma,
} }
static int static int
i915_gem_execbuffer_relocate(struct eb_vmas *eb, i915_gem_execbuffer_relocate(struct eb_vmas *eb)
struct i915_address_space *vm)
{ {
struct i915_vma *vma; struct i915_vma *vma;
int ret = 0; int ret = 0;
...@@ -1106,7 +1105,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, ...@@ -1106,7 +1105,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
goto pre_mutex_err; goto pre_mutex_err;
} }
eb = eb_create(args, vm); eb = eb_create(args);
if (eb == NULL) { if (eb == NULL) {
mutex_unlock(&dev->struct_mutex); mutex_unlock(&dev->struct_mutex);
ret = -ENOMEM; ret = -ENOMEM;
...@@ -1129,7 +1128,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, ...@@ -1129,7 +1128,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
/* The objects are in their final locations, apply the relocations. */ /* The objects are in their final locations, apply the relocations. */
if (need_relocs) if (need_relocs)
ret = i915_gem_execbuffer_relocate(eb, vm); ret = i915_gem_execbuffer_relocate(eb);
if (ret) { if (ret) {
if (ret == -EFAULT) { if (ret == -EFAULT) {
ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring, ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring,
......
drivers/gpu/drm/i915/i915_gem_gtt.c
View file @ da32cc90
...@@ -240,10 +240,16 @@ static int gen8_ppgtt_enable(struct drm_device *dev) ...@@ -240,10 +240,16 @@ static int gen8_ppgtt_enable(struct drm_device *dev)
for_each_ring(ring, dev_priv, j) { for_each_ring(ring, dev_priv, j) {
ret = gen8_write_pdp(ring, i, addr); ret = gen8_write_pdp(ring, i, addr);
if (ret) if (ret)
return ret; goto err_out;
} }
} }
return 0; return 0;
err_out:
for_each_ring(ring, dev_priv, j)
I915_WRITE(RING_MODE_GEN7(ring),
_MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE));
return ret;
} }
static void gen8_ppgtt_clear_range(struct i915_address_space *vm, static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
...@@ -318,6 +324,8 @@ static void gen8_ppgtt_cleanup(struct i915_address_space *vm) ...@@ -318,6 +324,8 @@ static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
container_of(vm, struct i915_hw_ppgtt, base); container_of(vm, struct i915_hw_ppgtt, base);
int i, j; int i, j;
drm_mm_takedown(&vm->mm);
for (i = 0; i < ppgtt->num_pd_pages ; i++) { for (i = 0; i < ppgtt->num_pd_pages ; i++) {
if (ppgtt->pd_dma_addr[i]) { if (ppgtt->pd_dma_addr[i]) {
pci_unmap_page(ppgtt->base.dev->pdev, pci_unmap_page(ppgtt->base.dev->pdev,
...@@ -337,8 +345,8 @@ static void gen8_ppgtt_cleanup(struct i915_address_space *vm) ...@@ -337,8 +345,8 @@ static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
kfree(ppgtt->gen8_pt_dma_addr[i]); kfree(ppgtt->gen8_pt_dma_addr[i]);
} }
__free_pages(ppgtt->gen8_pt_pages, ppgtt->num_pt_pages << PAGE_SHIFT); __free_pages(ppgtt->gen8_pt_pages, get_order(ppgtt->num_pt_pages << PAGE_SHIFT));
__free_pages(ppgtt->pd_pages, ppgtt->num_pd_pages << PAGE_SHIFT); __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
} }
/** /**
...@@ -381,6 +389,8 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) ...@@ -381,6 +389,8 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
ppgtt->base.clear_range = gen8_ppgtt_clear_range; ppgtt->base.clear_range = gen8_ppgtt_clear_range;
ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
ppgtt->base.cleanup = gen8_ppgtt_cleanup; ppgtt->base.cleanup = gen8_ppgtt_cleanup;
ppgtt->base.start = 0;
ppgtt->base.total = ppgtt->num_pt_pages * GEN8_PTES_PER_PAGE * PAGE_SIZE;
BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS); BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
...@@ -632,6 +642,8 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) ...@@ -632,6 +642,8 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
ppgtt->base.cleanup = gen6_ppgtt_cleanup; ppgtt->base.cleanup = gen6_ppgtt_cleanup;
ppgtt->base.scratch = dev_priv->gtt.base.scratch; ppgtt->base.scratch = dev_priv->gtt.base.scratch;
ppgtt->base.start = 0;
ppgtt->base.total = GEN6_PPGTT_PD_ENTRIES * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *), ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *),
GFP_KERNEL); GFP_KERNEL);
if (!ppgtt->pt_pages) if (!ppgtt->pt_pages)
...@@ -1126,7 +1138,6 @@ void i915_gem_setup_global_gtt(struct drm_device *dev, ...@@ -1126,7 +1138,6 @@ void i915_gem_setup_global_gtt(struct drm_device *dev,
if (ret) if (ret)
DRM_DEBUG_KMS("Reservation failed\n"); DRM_DEBUG_KMS("Reservation failed\n");
obj->has_global_gtt_mapping = 1; obj->has_global_gtt_mapping = 1;
list_add(&vma->vma_link, &obj->vma_list);
} }
dev_priv->gtt.base.start = start; dev_priv->gtt.base.start = start;
...@@ -1241,6 +1252,11 @@ static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) ...@@ -1241,6 +1252,11 @@ static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
if (bdw_gmch_ctl) if (bdw_gmch_ctl)
bdw_gmch_ctl = 1 << bdw_gmch_ctl; bdw_gmch_ctl = 1 << bdw_gmch_ctl;
if (bdw_gmch_ctl > 4) {
WARN_ON(!i915_preliminary_hw_support);
return 4<<20;
}
return bdw_gmch_ctl << 20; return bdw_gmch_ctl << 20;
} }
...@@ -1397,6 +1413,8 @@ static void gen6_gmch_remove(struct i915_address_space *vm) ...@@ -1397,6 +1413,8 @@ static void gen6_gmch_remove(struct i915_address_space *vm)
{ {
struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
drm_mm_takedown(&vm->mm);
iounmap(gtt->gsm); iounmap(gtt->gsm);
teardown_scratch_page(vm->dev); teardown_scratch_page(vm->dev);
} }
......
drivers/gpu/drm/i915/i915_irq.c
View file @ da32cc90
...@@ -600,7 +600,7 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) ...@@ -600,7 +600,7 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
* Cook up a vblank counter by also checking the pixel * Cook up a vblank counter by also checking the pixel
* counter against vblank start. * counter against vblank start.
*/ */
return ((high1 << 8) | low) + (pixel >= vbl_start); return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
} }
static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
...@@ -1015,10 +1015,8 @@ static void gen6_pm_rps_work(struct work_struct *work) ...@@ -1015,10 +1015,8 @@ static void gen6_pm_rps_work(struct work_struct *work)
/* sysfs frequency interfaces may have snuck in while servicing the /* sysfs frequency interfaces may have snuck in while servicing the
* interrupt * interrupt
*/ */
if (new_delay < (int)dev_priv->rps.min_delay) new_delay = clamp_t(int, new_delay,
new_delay = dev_priv->rps.min_delay; dev_priv->rps.min_delay, dev_priv->rps.max_delay);
if (new_delay > (int)dev_priv->rps.max_delay)
new_delay = dev_priv->rps.max_delay;
dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay; dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay;
if (IS_VALLEYVIEW(dev_priv->dev)) if (IS_VALLEYVIEW(dev_priv->dev))
...@@ -1474,6 +1472,9 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg) ...@@ -1474,6 +1472,9 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
dp_aux_irq_handler(dev);
I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
I915_READ(PORT_HOTPLUG_STAT); I915_READ(PORT_HOTPLUG_STAT);
} }
...@@ -1993,7 +1994,7 @@ static void i915_error_work_func(struct work_struct *work) ...@@ -1993,7 +1994,7 @@ static void i915_error_work_func(struct work_struct *work)
kobject_uevent_env(&dev->primary->kdev->kobj, kobject_uevent_env(&dev->primary->kdev->kobj,
KOBJ_CHANGE, reset_done_event); KOBJ_CHANGE, reset_done_event);
} else { } else {
atomic_set(&error->reset_counter, I915_WEDGED); atomic_set_mask(I915_WEDGED, &error->reset_counter);
} }
/* /*
...@@ -3655,6 +3656,10 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) ...@@ -3655,6 +3656,10 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
intel_hpd_irq_handler(dev, hotplug_trigger, intel_hpd_irq_handler(dev, hotplug_trigger,
IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915); IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915);
if (IS_G4X(dev) &&
(hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X))
dp_aux_irq_handler(dev);
I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
I915_READ(PORT_HOTPLUG_STAT); I915_READ(PORT_HOTPLUG_STAT);
} }
......
drivers/gpu/drm/i915/i915_reg.h
View file @ da32cc90
This diff is collapsed.
drivers/gpu/drm/i915/i915_suspend.c
View file @ da32cc90
...@@ -192,7 +192,6 @@ static void i915_restore_vga(struct drm_device *dev) ...@@ -192,7 +192,6 @@ static void i915_restore_vga(struct drm_device *dev)
static void i915_save_display(struct drm_device *dev) static void i915_save_display(struct drm_device *dev)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
unsigned long flags;
/* Display arbitration control */ /* Display arbitration control */
if (INTEL_INFO(dev)->gen <= 4) if (INTEL_INFO(dev)->gen <= 4)
...@@ -203,46 +202,27 @@ static void i915_save_display(struct drm_device *dev) ...@@ -203,46 +202,27 @@ static void i915_save_display(struct drm_device *dev)
if (!drm_core_check_feature(dev, DRIVER_MODESET)) if (!drm_core_check_feature(dev, DRIVER_MODESET))
i915_save_display_reg(dev); i915_save_display_reg(dev);
spin_lock_irqsave(&dev_priv->backlight.lock, flags);
/* LVDS state */ /* LVDS state */
if (HAS_PCH_SPLIT(dev)) { if (HAS_PCH_SPLIT(dev)) {
dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL); dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS); dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
} else if (IS_VALLEYVIEW(dev)) { } else if (IS_VALLEYVIEW(dev)) {
dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL); dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS); dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
dev_priv->regfile.saveBLC_PWM_CTL =
I915_READ(VLV_BLC_PWM_CTL(PIPE_A));
dev_priv->regfile.saveBLC_HIST_CTL = dev_priv->regfile.saveBLC_HIST_CTL =
I915_READ(VLV_BLC_HIST_CTL(PIPE_A)); I915_READ(VLV_BLC_HIST_CTL(PIPE_A));
dev_priv->regfile.saveBLC_PWM_CTL2 =
I915_READ(VLV_BLC_PWM_CTL2(PIPE_A));
dev_priv->regfile.saveBLC_PWM_CTL_B =
I915_READ(VLV_BLC_PWM_CTL(PIPE_B));
dev_priv->regfile.saveBLC_HIST_CTL_B = dev_priv->regfile.saveBLC_HIST_CTL_B =
I915_READ(VLV_BLC_HIST_CTL(PIPE_B)); I915_READ(VLV_BLC_HIST_CTL(PIPE_B));
dev_priv->regfile.saveBLC_PWM_CTL2_B =
I915_READ(VLV_BLC_PWM_CTL2(PIPE_B));
} else { } else {
dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL); dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS); dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL); dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
if (INTEL_INFO(dev)->gen >= 4)
dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
if (IS_MOBILE(dev) && !IS_I830(dev)) if (IS_MOBILE(dev) && !IS_I830(dev))
dev_priv->regfile.saveLVDS = I915_READ(LVDS); dev_priv->regfile.saveLVDS = I915_READ(LVDS);
} }
spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev)) if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL); dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
...@@ -278,7 +258,6 @@ static void i915_restore_display(struct drm_device *dev) ...@@ -278,7 +258,6 @@ static void i915_restore_display(struct drm_device *dev)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
u32 mask = 0xffffffff; u32 mask = 0xffffffff;
unsigned long flags;
/* Display arbitration */ /* Display arbitration */
if (INTEL_INFO(dev)->gen <= 4) if (INTEL_INFO(dev)->gen <= 4)
...@@ -287,12 +266,6 @@ static void i915_restore_display(struct drm_device *dev) ...@@ -287,12 +266,6 @@ static void i915_restore_display(struct drm_device *dev)
if (!drm_core_check_feature(dev, DRIVER_MODESET)) if (!drm_core_check_feature(dev, DRIVER_MODESET))
i915_restore_display_reg(dev); i915_restore_display_reg(dev);
spin_lock_irqsave(&dev_priv->backlight.lock, flags);
/* LVDS state */
if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
if (drm_core_check_feature(dev, DRIVER_MODESET)) if (drm_core_check_feature(dev, DRIVER_MODESET))
mask = ~LVDS_PORT_EN; mask = ~LVDS_PORT_EN;
...@@ -305,13 +278,6 @@ static void i915_restore_display(struct drm_device *dev) ...@@ -305,13 +278,6 @@ static void i915_restore_display(struct drm_device *dev)
I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL); I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);
if (HAS_PCH_SPLIT(dev)) { if (HAS_PCH_SPLIT(dev)) {
I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->regfile.saveBLC_PWM_CTL);
I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
/* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2;
* otherwise we get blank eDP screen after S3 on some machines
*/
I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2);
I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL);
I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS); I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS); I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR); I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
...@@ -319,21 +285,12 @@ static void i915_restore_display(struct drm_device *dev) ...@@ -319,21 +285,12 @@ static void i915_restore_display(struct drm_device *dev)
I915_WRITE(RSTDBYCTL, I915_WRITE(RSTDBYCTL,
dev_priv->regfile.saveMCHBAR_RENDER_STANDBY); dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);
} else if (IS_VALLEYVIEW(dev)) { } else if (IS_VALLEYVIEW(dev)) {
I915_WRITE(VLV_BLC_PWM_CTL(PIPE_A),
dev_priv->regfile.saveBLC_PWM_CTL);
I915_WRITE(VLV_BLC_HIST_CTL(PIPE_A), I915_WRITE(VLV_BLC_HIST_CTL(PIPE_A),
dev_priv->regfile.saveBLC_HIST_CTL); dev_priv->regfile.saveBLC_HIST_CTL);
I915_WRITE(VLV_BLC_PWM_CTL2(PIPE_A),
dev_priv->regfile.saveBLC_PWM_CTL2);
I915_WRITE(VLV_BLC_PWM_CTL(PIPE_B),
dev_priv->regfile.saveBLC_PWM_CTL);
I915_WRITE(VLV_BLC_HIST_CTL(PIPE_B), I915_WRITE(VLV_BLC_HIST_CTL(PIPE_B),
dev_priv->regfile.saveBLC_HIST_CTL); dev_priv->regfile.saveBLC_HIST_CTL);
I915_WRITE(VLV_BLC_PWM_CTL2(PIPE_B),
dev_priv->regfile.saveBLC_PWM_CTL2);
} else { } else {
I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS); I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL); I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);
I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS); I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS); I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
...@@ -341,8 +298,6 @@ static void i915_restore_display(struct drm_device *dev) ...@@ -341,8 +298,6 @@ static void i915_restore_display(struct drm_device *dev)
I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL); I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
} }
spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
/* only restore FBC info on the platform that supports FBC*/ /* only restore FBC info on the platform that supports FBC*/
intel_disable_fbc(dev); intel_disable_fbc(dev);
if (I915_HAS_FBC(dev)) { if (I915_HAS_FBC(dev)) {
......
drivers/gpu/drm/i915/i915_sysfs.c
View file @ da32cc90
...@@ -183,13 +183,13 @@ i915_l3_write(struct file *filp, struct kobject *kobj, ...@@ -183,13 +183,13 @@ i915_l3_write(struct file *filp, struct kobject *kobj,
int slice = (int)(uintptr_t)attr->private; int slice = (int)(uintptr_t)attr->private;
int ret; int ret;
if (!HAS_HW_CONTEXTS(drm_dev))
return -ENXIO;
ret = l3_access_valid(drm_dev, offset); ret = l3_access_valid(drm_dev, offset);
if (ret) if (ret)
return ret; return ret;
if (dev_priv->hw_contexts_disabled)
return -ENXIO;
ret = i915_mutex_lock_interruptible(drm_dev); ret = i915_mutex_lock_interruptible(drm_dev);
if (ret) if (ret)
return ret; return ret;
...@@ -259,7 +259,7 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev, ...@@ -259,7 +259,7 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
if (IS_VALLEYVIEW(dev_priv->dev)) { if (IS_VALLEYVIEW(dev_priv->dev)) {
u32 freq; u32 freq;
freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
ret = vlv_gpu_freq(dev_priv->mem_freq, (freq >> 8) & 0xff); ret = vlv_gpu_freq(dev_priv, (freq >> 8) & 0xff);
} else { } else {
ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER; ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER;
} }
...@@ -276,8 +276,7 @@ static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev, ...@@ -276,8 +276,7 @@ static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
return snprintf(buf, PAGE_SIZE, "%d\n", return snprintf(buf, PAGE_SIZE, "%d\n",
vlv_gpu_freq(dev_priv->mem_freq, vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay));
dev_priv->rps.rpe_delay));
} }
static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
...@@ -291,7 +290,7 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute ...@@ -291,7 +290,7 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->rps.hw_lock);
if (IS_VALLEYVIEW(dev_priv->dev)) if (IS_VALLEYVIEW(dev_priv->dev))
ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.max_delay); ret = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay);
else else
ret = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; ret = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->rps.hw_lock);
...@@ -318,7 +317,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev, ...@@ -318,7 +317,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->rps.hw_lock);
if (IS_VALLEYVIEW(dev_priv->dev)) { if (IS_VALLEYVIEW(dev_priv->dev)) {
val = vlv_freq_opcode(dev_priv->mem_freq, val); val = vlv_freq_opcode(dev_priv, val);
hw_max = valleyview_rps_max_freq(dev_priv); hw_max = valleyview_rps_max_freq(dev_priv);
hw_min = valleyview_rps_min_freq(dev_priv); hw_min = valleyview_rps_min_freq(dev_priv);
...@@ -342,15 +341,15 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev, ...@@ -342,15 +341,15 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
DRM_DEBUG("User requested overclocking to %d\n", DRM_DEBUG("User requested overclocking to %d\n",
val * GT_FREQUENCY_MULTIPLIER); val * GT_FREQUENCY_MULTIPLIER);
dev_priv->rps.max_delay = val;
if (dev_priv->rps.cur_delay > val) { if (dev_priv->rps.cur_delay > val) {
if (IS_VALLEYVIEW(dev_priv->dev)) if (IS_VALLEYVIEW(dev))
valleyview_set_rps(dev_priv->dev, val); valleyview_set_rps(dev, val);
else else
gen6_set_rps(dev_priv->dev, val); gen6_set_rps(dev, val);
} }
dev_priv->rps.max_delay = val;
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->rps.hw_lock);
return count; return count;
...@@ -367,7 +366,7 @@ static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute ...@@ -367,7 +366,7 @@ static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->rps.hw_lock);
if (IS_VALLEYVIEW(dev_priv->dev)) if (IS_VALLEYVIEW(dev_priv->dev))
ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.min_delay); ret = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay);
else else
ret = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; ret = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->rps.hw_lock);
...@@ -394,7 +393,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev, ...@@ -394,7 +393,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->rps.hw_lock);
if (IS_VALLEYVIEW(dev)) { if (IS_VALLEYVIEW(dev)) {
val = vlv_freq_opcode(dev_priv->mem_freq, val); val = vlv_freq_opcode(dev_priv, val);
hw_max = valleyview_rps_max_freq(dev_priv); hw_max = valleyview_rps_max_freq(dev_priv);
hw_min = valleyview_rps_min_freq(dev_priv); hw_min = valleyview_rps_min_freq(dev_priv);
...@@ -411,15 +410,15 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev, ...@@ -411,15 +410,15 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
return -EINVAL; return -EINVAL;
} }
dev_priv->rps.min_delay = val;
if (dev_priv->rps.cur_delay < val) { if (dev_priv->rps.cur_delay < val) {
if (IS_VALLEYVIEW(dev)) if (IS_VALLEYVIEW(dev))
valleyview_set_rps(dev, val); valleyview_set_rps(dev, val);
else else
gen6_set_rps(dev_priv->dev, val); gen6_set_rps(dev, val);
} }
dev_priv->rps.min_delay = val;
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->rps.hw_lock);
return count; return count;
......
drivers/gpu/drm/i915/i915_ums.c
View file @ da32cc90
...@@ -270,6 +270,18 @@ void i915_save_display_reg(struct drm_device *dev) ...@@ -270,6 +270,18 @@ void i915_save_display_reg(struct drm_device *dev)
} }
/* FIXME: regfile.save TV & SDVO state */ /* FIXME: regfile.save TV & SDVO state */
/* Backlight */
if (HAS_PCH_SPLIT(dev)) {
dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
} else {
dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
if (INTEL_INFO(dev)->gen >= 4)
dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
}
return; return;
} }
...@@ -280,6 +292,21 @@ void i915_restore_display_reg(struct drm_device *dev) ...@@ -280,6 +292,21 @@ void i915_restore_display_reg(struct drm_device *dev)
int dpll_b_reg, fpb0_reg, fpb1_reg; int dpll_b_reg, fpb0_reg, fpb1_reg;
int i; int i;
/* Backlight */
if (HAS_PCH_SPLIT(dev)) {
I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->regfile.saveBLC_PWM_CTL);
I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
/* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2;
* otherwise we get blank eDP screen after S3 on some machines
*/
I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2);
I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL);
} else {
if (INTEL_INFO(dev)->gen >= 4)
I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
}
/* Display port ratios (must be done before clock is set) */ /* Display port ratios (must be done before clock is set) */
if (SUPPORTS_INTEGRATED_DP(dev)) { if (SUPPORTS_INTEGRATED_DP(dev)) {
I915_WRITE(_PIPEA_DATA_M_G4X, dev_priv->regfile.savePIPEA_GMCH_DATA_M); I915_WRITE(_PIPEA_DATA_M_G4X, dev_priv->regfile.savePIPEA_GMCH_DATA_M);
......
drivers/gpu/drm/i915/intel_crt.c
View file @ da32cc90
...@@ -222,8 +222,9 @@ static void intel_crt_dpms(struct drm_connector *connector, int mode) ...@@ -222,8 +222,9 @@ static void intel_crt_dpms(struct drm_connector *connector, int mode)
intel_modeset_check_state(connector->dev); intel_modeset_check_state(connector->dev);
} }
static int intel_crt_mode_valid(struct drm_connector *connector, static enum drm_mode_status
struct drm_display_mode *mode) intel_crt_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
{ {
struct drm_device *dev = connector->dev; struct drm_device *dev = connector->dev;
......
drivers/gpu/drm/i915/intel_ddi.c
View file @ da32cc90
...@@ -713,8 +713,6 @@ bool intel_ddi_pll_mode_set(struct drm_crtc *crtc) ...@@ -713,8 +713,6 @@ bool intel_ddi_pll_mode_set(struct drm_crtc *crtc)
uint32_t reg, val; uint32_t reg, val;
int clock = intel_crtc->config.port_clock; int clock = intel_crtc->config.port_clock;
/* TODO: reuse PLLs when possible (compare values) */
intel_ddi_put_crtc_pll(crtc); intel_ddi_put_crtc_pll(crtc);
if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
...@@ -742,31 +740,40 @@ bool intel_ddi_pll_mode_set(struct drm_crtc *crtc) ...@@ -742,31 +740,40 @@ bool intel_ddi_pll_mode_set(struct drm_crtc *crtc)
} else if (type == INTEL_OUTPUT_HDMI) { } else if (type == INTEL_OUTPUT_HDMI) {
unsigned p, n2, r2; unsigned p, n2, r2;
if (plls->wrpll1_refcount == 0) { intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
WRPLL_DIVIDER_POST(p);
if (val == I915_READ(WRPLL_CTL1)) {
DRM_DEBUG_KMS("Reusing WRPLL 1 on pipe %c\n",
pipe_name(pipe));
reg = WRPLL_CTL1;
} else if (val == I915_READ(WRPLL_CTL2)) {
DRM_DEBUG_KMS("Reusing WRPLL 2 on pipe %c\n",
pipe_name(pipe));
reg = WRPLL_CTL2;
} else if (plls->wrpll1_refcount == 0) {
DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n", DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
pipe_name(pipe)); pipe_name(pipe));
plls->wrpll1_refcount++;
reg = WRPLL_CTL1; reg = WRPLL_CTL1;
intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
} else if (plls->wrpll2_refcount == 0) { } else if (plls->wrpll2_refcount == 0) {
DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n", DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
pipe_name(pipe)); pipe_name(pipe));
plls->wrpll2_refcount++;
reg = WRPLL_CTL2; reg = WRPLL_CTL2;
intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
} else { } else {
DRM_ERROR("No WRPLLs available!\n"); DRM_ERROR("No WRPLLs available!\n");
return false; return false;
} }
WARN(I915_READ(reg) & WRPLL_PLL_ENABLE, if (reg == WRPLL_CTL1) {
"WRPLL already enabled\n"); plls->wrpll1_refcount++;
intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); } else {
plls->wrpll2_refcount++;
val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | }
WRPLL_DIVIDER_POST(p);
} else if (type == INTEL_OUTPUT_ANALOG) { } else if (type == INTEL_OUTPUT_ANALOG) {
if (plls->spll_refcount == 0) { if (plls->spll_refcount == 0) {
......
drivers/gpu/drm/i915/intel_display.c
View file @ da32cc90
This diff is collapsed.
drivers/gpu/drm/i915/intel_dp.c
View file @ da32cc90
...@@ -142,7 +142,7 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes) ...@@ -142,7 +142,7 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
return (max_link_clock * max_lanes * 8) / 10; return (max_link_clock * max_lanes * 8) / 10;
} }
static int static enum drm_mode_status
intel_dp_mode_valid(struct drm_connector *connector, intel_dp_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode) struct drm_display_mode *mode)
{ {
...@@ -404,7 +404,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, ...@@ -404,7 +404,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
int i, ret, recv_bytes; int i, ret, recv_bytes;
uint32_t status; uint32_t status;
int try, precharge, clock = 0; int try, precharge, clock = 0;
bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev); bool has_aux_irq = true;
uint32_t timeout; uint32_t timeout;
/* dp aux is extremely sensitive to irq latency, hence request the /* dp aux is extremely sensitive to irq latency, hence request the
...@@ -1845,23 +1845,23 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder) ...@@ -1845,23 +1845,23 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder)
struct drm_device *dev = encoder->base.dev; struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
int port = vlv_dport_to_channel(dport); enum dpio_channel port = vlv_dport_to_channel(dport);
int pipe = intel_crtc->pipe; int pipe = intel_crtc->pipe;
struct edp_power_seq power_seq; struct edp_power_seq power_seq;
u32 val; u32 val;
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->dpio_lock);
val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port)); val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
val = 0; val = 0;
if (pipe) if (pipe)
val |= (1<<21); val |= (1<<21);
else else
val &= ~(1<<21); val &= ~(1<<21);
val |= 0x001000c4; val |= 0x001000c4;
vlv_dpio_write(dev_priv, pipe, DPIO_DATA_CHANNEL(port), val); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF0(port), 0x00760018); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF8(port), 0x00400888); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->dpio_lock);
...@@ -1872,7 +1872,7 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder) ...@@ -1872,7 +1872,7 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder)
intel_enable_dp(encoder); intel_enable_dp(encoder);
vlv_wait_port_ready(dev_priv, port); vlv_wait_port_ready(dev_priv, dport);
} }
static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
...@@ -1882,24 +1882,24 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) ...@@ -1882,24 +1882,24 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = struct intel_crtc *intel_crtc =
to_intel_crtc(encoder->base.crtc); to_intel_crtc(encoder->base.crtc);
int port = vlv_dport_to_channel(dport); enum dpio_channel port = vlv_dport_to_channel(dport);
int pipe = intel_crtc->pipe; int pipe = intel_crtc->pipe;
/* Program Tx lane resets to default */ /* Program Tx lane resets to default */
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->dpio_lock);
vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port), vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE2_RESET |
DPIO_PCS_TX_LANE1_RESET); DPIO_PCS_TX_LANE1_RESET);
vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port), vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
(1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
DPIO_PCS_CLK_SOFT_RESET); DPIO_PCS_CLK_SOFT_RESET);
/* Fix up inter-pair skew failure */ /* Fix up inter-pair skew failure */
vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER1(port), 0x00750f00); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
vlv_dpio_write(dev_priv, pipe, DPIO_TX_CTL(port), 0x00001500); vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
vlv_dpio_write(dev_priv, pipe, DPIO_TX_LANE(port), 0x40400000); vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->dpio_lock);
} }
...@@ -2050,7 +2050,7 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) ...@@ -2050,7 +2050,7 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
unsigned long demph_reg_value, preemph_reg_value, unsigned long demph_reg_value, preemph_reg_value,
uniqtranscale_reg_value; uniqtranscale_reg_value;
uint8_t train_set = intel_dp->train_set[0]; uint8_t train_set = intel_dp->train_set[0];
int port = vlv_dport_to_channel(dport); enum dpio_channel port = vlv_dport_to_channel(dport);
int pipe = intel_crtc->pipe; int pipe = intel_crtc->pipe;
switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
...@@ -2127,14 +2127,14 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) ...@@ -2127,14 +2127,14 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
} }
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->dpio_lock);
vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x00000000); vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL4(port), demph_reg_value); vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL2(port), vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
uniqtranscale_reg_value); uniqtranscale_reg_value);
vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL3(port), 0x0C782040); vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER0(port), 0x00030000); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port), preemph_reg_value); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x80000000); vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->dpio_lock);
return 0; return 0;
......
drivers/gpu/drm/i915/intel_drv.h
View file @ da32cc90
...@@ -156,6 +156,17 @@ struct intel_encoder { ...@@ -156,6 +156,17 @@ struct intel_encoder {
struct intel_panel { struct intel_panel {
struct drm_display_mode *fixed_mode; struct drm_display_mode *fixed_mode;
int fitting_mode; int fitting_mode;
/* backlight */
struct {
bool present;
u32 level;
u32 max;
bool enabled;
bool combination_mode; /* gen 2/4 only */
bool active_low_pwm;
struct backlight_device *device;
} backlight;
}; };
struct intel_connector { struct intel_connector {
...@@ -490,9 +501,9 @@ vlv_dport_to_channel(struct intel_digital_port *dport) ...@@ -490,9 +501,9 @@ vlv_dport_to_channel(struct intel_digital_port *dport)
{ {
switch (dport->port) { switch (dport->port) {
case PORT_B: case PORT_B:
return 0; return DPIO_CH0;
case PORT_C: case PORT_C:
return 1; return DPIO_CH1;
default: default:
BUG(); BUG();
} }
...@@ -638,7 +649,8 @@ enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, ...@@ -638,7 +649,8 @@ enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
void intel_wait_for_vblank(struct drm_device *dev, int pipe); void intel_wait_for_vblank(struct drm_device *dev, int pipe);
void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port); void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
struct intel_digital_port *dport);
bool intel_get_load_detect_pipe(struct drm_connector *connector, bool intel_get_load_detect_pipe(struct drm_connector *connector,
struct drm_display_mode *mode, struct drm_display_mode *mode,
struct intel_load_detect_pipe *old); struct intel_load_detect_pipe *old);
...@@ -694,7 +706,7 @@ void i915_disable_vga_mem(struct drm_device *dev); ...@@ -694,7 +706,7 @@ void i915_disable_vga_mem(struct drm_device *dev);
void hsw_enable_ips(struct intel_crtc *crtc); void hsw_enable_ips(struct intel_crtc *crtc);
void hsw_disable_ips(struct intel_crtc *crtc); void hsw_disable_ips(struct intel_crtc *crtc);
void intel_display_set_init_power(struct drm_device *dev, bool enable); void intel_display_set_init_power(struct drm_device *dev, bool enable);
int valleyview_get_vco(struct drm_i915_private *dev_priv);
/* intel_dp.c */ /* intel_dp.c */
void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
...@@ -808,7 +820,8 @@ void intel_panel_set_backlight(struct intel_connector *connector, u32 level, ...@@ -808,7 +820,8 @@ void intel_panel_set_backlight(struct intel_connector *connector, u32 level,
int intel_panel_setup_backlight(struct drm_connector *connector); int intel_panel_setup_backlight(struct drm_connector *connector);
void intel_panel_enable_backlight(struct intel_connector *connector); void intel_panel_enable_backlight(struct intel_connector *connector);
void intel_panel_disable_backlight(struct intel_connector *connector); void intel_panel_disable_backlight(struct intel_connector *connector);
void intel_panel_destroy_backlight(struct drm_device *dev); void intel_panel_destroy_backlight(struct drm_connector *connector);
void intel_panel_init_backlight_funcs(struct drm_device *dev);
enum drm_connector_status intel_panel_detect(struct drm_device *dev); enum drm_connector_status intel_panel_detect(struct drm_device *dev);
...@@ -829,6 +842,8 @@ int intel_power_domains_init(struct drm_device *dev); ...@@ -829,6 +842,8 @@ int intel_power_domains_init(struct drm_device *dev);
void intel_power_domains_remove(struct drm_device *dev); void intel_power_domains_remove(struct drm_device *dev);
bool intel_display_power_enabled(struct drm_device *dev, bool intel_display_power_enabled(struct drm_device *dev,
enum intel_display_power_domain domain); enum intel_display_power_domain domain);
bool intel_display_power_enabled_sw(struct drm_device *dev,
enum intel_display_power_domain domain);
void intel_display_power_get(struct drm_device *dev, void intel_display_power_get(struct drm_device *dev,
enum intel_display_power_domain domain); enum intel_display_power_domain domain);
void intel_display_power_put(struct drm_device *dev, void intel_display_power_put(struct drm_device *dev,
......
drivers/gpu/drm/i915/intel_dsi.c
View file @ da32cc90
...@@ -251,8 +251,9 @@ static void intel_dsi_get_config(struct intel_encoder *encoder, ...@@ -251,8 +251,9 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
/* XXX: read flags, set to adjusted_mode */ /* XXX: read flags, set to adjusted_mode */
} }
static int intel_dsi_mode_valid(struct drm_connector *connector, static enum drm_mode_status
struct drm_display_mode *mode) intel_dsi_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
{ {
struct intel_connector *intel_connector = to_intel_connector(connector); struct intel_connector *intel_connector = to_intel_connector(connector);
struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
......
drivers/gpu/drm/i915/intel_dvo.c
View file @ da32cc90
...@@ -234,8 +234,9 @@ static void intel_dvo_dpms(struct drm_connector *connector, int mode) ...@@ -234,8 +234,9 @@ static void intel_dvo_dpms(struct drm_connector *connector, int mode)
intel_modeset_check_state(connector->dev); intel_modeset_check_state(connector->dev);
} }
static int intel_dvo_mode_valid(struct drm_connector *connector, static enum drm_mode_status
struct drm_display_mode *mode) intel_dvo_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
{ {
struct intel_dvo *intel_dvo = intel_attached_dvo(connector); struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
......
drivers/gpu/drm/i915/intel_fbdev.c
View file @ da32cc90
...@@ -57,18 +57,14 @@ static struct fb_ops intelfb_ops = { ...@@ -57,18 +57,14 @@ static struct fb_ops intelfb_ops = {
.fb_debug_leave = drm_fb_helper_debug_leave, .fb_debug_leave = drm_fb_helper_debug_leave,
}; };
static int intelfb_create(struct drm_fb_helper *helper, static int intelfb_alloc(struct drm_fb_helper *helper,
struct drm_fb_helper_surface_size *sizes) struct drm_fb_helper_surface_size *sizes)
{ {
struct intel_fbdev *ifbdev = struct intel_fbdev *ifbdev =
container_of(helper, struct intel_fbdev, helper); container_of(helper, struct intel_fbdev, helper);
struct drm_device *dev = helper->dev; struct drm_device *dev = helper->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct fb_info *info;
struct drm_framebuffer *fb;
struct drm_mode_fb_cmd2 mode_cmd = {}; struct drm_mode_fb_cmd2 mode_cmd = {};
struct drm_i915_gem_object *obj; struct drm_i915_gem_object *obj;
struct device *device = &dev->pdev->dev;
int size, ret; int size, ret;
/* we don't do packed 24bpp */ /* we don't do packed 24bpp */
...@@ -94,8 +90,6 @@ static int intelfb_create(struct drm_fb_helper *helper, ...@@ -94,8 +90,6 @@ static int intelfb_create(struct drm_fb_helper *helper,
goto out; goto out;
} }
mutex_lock(&dev->struct_mutex);
/* Flush everything out, we'll be doing GTT only from now on */ /* Flush everything out, we'll be doing GTT only from now on */
ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
if (ret) { if (ret) {
...@@ -103,7 +97,50 @@ static int intelfb_create(struct drm_fb_helper *helper, ...@@ -103,7 +97,50 @@ static int intelfb_create(struct drm_fb_helper *helper,
goto out_unref; goto out_unref;
} }
info = framebuffer_alloc(0, device); ret = intel_framebuffer_init(dev, &ifbdev->ifb, &mode_cmd, obj);
if (ret)
goto out_unpin;
return 0;
out_unpin:
i915_gem_object_unpin(obj);
out_unref:
drm_gem_object_unreference(&obj->base);
out:
return ret;
}
static int intelfb_create(struct drm_fb_helper *helper,
struct drm_fb_helper_surface_size *sizes)
{
struct intel_fbdev *ifbdev =
container_of(helper, struct intel_fbdev, helper);
struct intel_framebuffer *intel_fb = &ifbdev->ifb;
struct drm_device *dev = helper->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct fb_info *info;
struct drm_framebuffer *fb;
struct drm_i915_gem_object *obj;
int size, ret;
mutex_lock(&dev->struct_mutex);
if (!intel_fb->obj) {
DRM_DEBUG_KMS("no BIOS fb, allocating a new one\n");
ret = intelfb_alloc(helper, sizes);
if (ret)
goto out_unlock;
} else {
DRM_DEBUG_KMS("re-using BIOS fb\n");
sizes->fb_width = intel_fb->base.width;
sizes->fb_height = intel_fb->base.height;
}
obj = intel_fb->obj;
size = obj->base.size;
info = framebuffer_alloc(0, &dev->pdev->dev);
if (!info) { if (!info) {
ret = -ENOMEM; ret = -ENOMEM;
goto out_unpin; goto out_unpin;
...@@ -111,10 +148,6 @@ static int intelfb_create(struct drm_fb_helper *helper, ...@@ -111,10 +148,6 @@ static int intelfb_create(struct drm_fb_helper *helper,
info->par = helper; info->par = helper;
ret = intel_framebuffer_init(dev, &ifbdev->ifb, &mode_cmd, obj);
if (ret)
goto out_unpin;
fb = &ifbdev->ifb.base; fb = &ifbdev->ifb.base;
ifbdev->helper.fb = fb; ifbdev->helper.fb = fb;
...@@ -170,17 +203,15 @@ static int intelfb_create(struct drm_fb_helper *helper, ...@@ -170,17 +203,15 @@ static int intelfb_create(struct drm_fb_helper *helper,
fb->width, fb->height, fb->width, fb->height,
i915_gem_obj_ggtt_offset(obj), obj); i915_gem_obj_ggtt_offset(obj), obj);
mutex_unlock(&dev->struct_mutex); mutex_unlock(&dev->struct_mutex);
vga_switcheroo_client_fb_set(dev->pdev, info); vga_switcheroo_client_fb_set(dev->pdev, info);
return 0; return 0;
out_unpin: out_unpin:
i915_gem_object_unpin(obj); i915_gem_object_unpin(obj);
out_unref:
drm_gem_object_unreference(&obj->base); drm_gem_object_unreference(&obj->base);
out_unlock:
mutex_unlock(&dev->struct_mutex); mutex_unlock(&dev->struct_mutex);
out:
return ret; return ret;
} }
......
drivers/gpu/drm/i915/intel_hdmi.c
View file @ da32cc90
...@@ -853,8 +853,9 @@ static int hdmi_portclock_limit(struct intel_hdmi *hdmi) ...@@ -853,8 +853,9 @@ static int hdmi_portclock_limit(struct intel_hdmi *hdmi)
return 225000; return 225000;
} }
static int intel_hdmi_mode_valid(struct drm_connector *connector, static enum drm_mode_status
struct drm_display_mode *mode) intel_hdmi_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
{ {
if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector))) if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector)))
return MODE_CLOCK_HIGH; return MODE_CLOCK_HIGH;
...@@ -1081,7 +1082,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) ...@@ -1081,7 +1082,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = struct intel_crtc *intel_crtc =
to_intel_crtc(encoder->base.crtc); to_intel_crtc(encoder->base.crtc);
int port = vlv_dport_to_channel(dport); enum dpio_channel port = vlv_dport_to_channel(dport);
int pipe = intel_crtc->pipe; int pipe = intel_crtc->pipe;
u32 val; u32 val;
...@@ -1090,41 +1091,33 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) ...@@ -1090,41 +1091,33 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
/* Enable clock channels for this port */ /* Enable clock channels for this port */
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->dpio_lock);
val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port)); val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
val = 0; val = 0;
if (pipe) if (pipe)
val |= (1<<21); val |= (1<<21);
else else
val &= ~(1<<21); val &= ~(1<<21);
val |= 0x001000c4; val |= 0x001000c4;
vlv_dpio_write(dev_priv, pipe, DPIO_DATA_CHANNEL(port), val); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
/* HDMI 1.0V-2dB */ /* HDMI 1.0V-2dB */
vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0); vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL4(port), vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
0x2b245f5f); vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL2(port), vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
0x5578b83a); vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL3(port), vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
0x0c782040); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
vlv_dpio_write(dev_priv, pipe, DPIO_TX3_SWING_CTL4(port), vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
0x2b247878);
vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER0(port), 0x00030000);
vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port),
0x00002000);
vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port),
DPIO_TX_OCALINIT_EN);
/* Program lane clock */ /* Program lane clock */
vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF0(port), vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
0x00760018); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF8(port),
0x00400888);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->dpio_lock);
intel_enable_hdmi(encoder); intel_enable_hdmi(encoder);
vlv_wait_port_ready(dev_priv, port); vlv_wait_port_ready(dev_priv, dport);
} }
static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
...@@ -1134,7 +1127,7 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) ...@@ -1134,7 +1127,7 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = struct intel_crtc *intel_crtc =
to_intel_crtc(encoder->base.crtc); to_intel_crtc(encoder->base.crtc);
int port = vlv_dport_to_channel(dport); enum dpio_channel port = vlv_dport_to_channel(dport);
int pipe = intel_crtc->pipe; int pipe = intel_crtc->pipe;
if (!IS_VALLEYVIEW(dev)) if (!IS_VALLEYVIEW(dev))
...@@ -1142,24 +1135,22 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) ...@@ -1142,24 +1135,22 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
/* Program Tx lane resets to default */ /* Program Tx lane resets to default */
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->dpio_lock);
vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port), vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE2_RESET |
DPIO_PCS_TX_LANE1_RESET); DPIO_PCS_TX_LANE1_RESET);
vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port), vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
(1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
DPIO_PCS_CLK_SOFT_RESET); DPIO_PCS_CLK_SOFT_RESET);
/* Fix up inter-pair skew failure */ /* Fix up inter-pair skew failure */
vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER1(port), 0x00750f00); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
vlv_dpio_write(dev_priv, pipe, DPIO_TX_CTL(port), 0x00001500); vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
vlv_dpio_write(dev_priv, pipe, DPIO_TX_LANE(port), 0x40400000); vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port), vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
0x00002000); vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port),
DPIO_TX_OCALINIT_EN);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->dpio_lock);
} }
...@@ -1169,13 +1160,13 @@ static void vlv_hdmi_post_disable(struct intel_encoder *encoder) ...@@ -1169,13 +1160,13 @@ static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_crtc *intel_crtc = struct intel_crtc *intel_crtc =
to_intel_crtc(encoder->base.crtc); to_intel_crtc(encoder->base.crtc);
int port = vlv_dport_to_channel(dport); enum dpio_channel port = vlv_dport_to_channel(dport);
int pipe = intel_crtc->pipe; int pipe = intel_crtc->pipe;
/* Reset lanes to avoid HDMI flicker (VLV w/a) */ /* Reset lanes to avoid HDMI flicker (VLV w/a) */
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->dpio_lock);
vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port), 0x00000000); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port), 0x00e00060); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->dpio_lock);
} }
......
drivers/gpu/drm/i915/intel_i2c.c
View file @ da32cc90
...@@ -82,20 +82,11 @@ static int get_disp_clk_div(struct drm_i915_private *dev_priv, ...@@ -82,20 +82,11 @@ static int get_disp_clk_div(struct drm_i915_private *dev_priv,
static void gmbus_set_freq(struct drm_i915_private *dev_priv) static void gmbus_set_freq(struct drm_i915_private *dev_priv)
{ {
int vco_freq[] = { 800, 1600, 2000, 2400 }; int vco, gmbus_freq = 0, cdclk_div;
int gmbus_freq = 0, cdclk_div, hpll_freq;
BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
/* Skip setting the gmbus freq if BIOS has already programmed it */ vco = valleyview_get_vco(dev_priv);
if (I915_READ(GMBUSFREQ_VLV) != 0xA0)
return;
/* Obtain SKU information */
mutex_lock(&dev_priv->dpio_lock);
hpll_freq =
vlv_cck_read(dev_priv, CCK_FUSE_REG) & CCK_FUSE_HPLL_FREQ_MASK;
mutex_unlock(&dev_priv->dpio_lock);
/* Get the CDCLK divide ratio */ /* Get the CDCLK divide ratio */
cdclk_div = get_disp_clk_div(dev_priv, CDCLK); cdclk_div = get_disp_clk_div(dev_priv, CDCLK);
...@@ -106,7 +97,7 @@ static void gmbus_set_freq(struct drm_i915_private *dev_priv) ...@@ -106,7 +97,7 @@ static void gmbus_set_freq(struct drm_i915_private *dev_priv)
* in fact 1MHz is the correct frequency. * in fact 1MHz is the correct frequency.
*/ */
if (cdclk_div) if (cdclk_div)
gmbus_freq = (vco_freq[hpll_freq] << 1) / cdclk_div; gmbus_freq = (vco << 1) / cdclk_div;
if (WARN_ON(gmbus_freq == 0)) if (WARN_ON(gmbus_freq == 0))
return; return;
......
drivers/gpu/drm/i915/intel_lvds.c
View file @ da32cc90
...@@ -256,8 +256,9 @@ static void intel_disable_lvds(struct intel_encoder *encoder) ...@@ -256,8 +256,9 @@ static void intel_disable_lvds(struct intel_encoder *encoder)
POSTING_READ(lvds_encoder->reg); POSTING_READ(lvds_encoder->reg);
} }
static int intel_lvds_mode_valid(struct drm_connector *connector, static enum drm_mode_status
struct drm_display_mode *mode) intel_lvds_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
{ {
struct intel_connector *intel_connector = to_intel_connector(connector); struct intel_connector *intel_connector = to_intel_connector(connector);
struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
......
drivers/gpu/drm/i915/intel_opregion.c
View file @ da32cc90
...@@ -396,13 +396,10 @@ int intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) ...@@ -396,13 +396,10 @@ int intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
static u32 asle_set_backlight(struct drm_device *dev, u32 bclp) static u32 asle_set_backlight(struct drm_device *dev, u32 bclp)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_encoder *encoder;
struct drm_connector *connector; struct drm_connector *connector;
struct intel_connector *intel_connector = NULL; struct intel_connector *intel_connector;
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[0]; struct intel_panel *panel;
struct opregion_asle __iomem *asle = dev_priv->opregion.asle; struct opregion_asle __iomem *asle = dev_priv->opregion.asle;
u32 ret = 0;
bool found = false;
DRM_DEBUG_DRIVER("bclp = 0x%08x\n", bclp); DRM_DEBUG_DRIVER("bclp = 0x%08x\n", bclp);
...@@ -414,38 +411,24 @@ static u32 asle_set_backlight(struct drm_device *dev, u32 bclp) ...@@ -414,38 +411,24 @@ static u32 asle_set_backlight(struct drm_device *dev, u32 bclp)
return ASLC_BACKLIGHT_FAILED; return ASLC_BACKLIGHT_FAILED;
mutex_lock(&dev->mode_config.mutex); mutex_lock(&dev->mode_config.mutex);
/* /*
* Could match the OpRegion connector here instead, but we'd also need * Update backlight on all connectors that support backlight (usually
* to verify the connector could handle a backlight call. * only one).
*/ */
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
if (encoder->crtc == crtc) {
found = true;
break;
}
if (!found) {
ret = ASLC_BACKLIGHT_FAILED;
goto out;
}
list_for_each_entry(connector, &dev->mode_config.connector_list, head)
if (connector->encoder == encoder)
intel_connector = to_intel_connector(connector);
if (!intel_connector) {
ret = ASLC_BACKLIGHT_FAILED;
goto out;
}
DRM_DEBUG_KMS("updating opregion backlight %d/255\n", bclp); DRM_DEBUG_KMS("updating opregion backlight %d/255\n", bclp);
intel_panel_set_backlight(intel_connector, bclp, 255); list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
intel_connector = to_intel_connector(connector);
panel = &intel_connector->panel;
if (panel->backlight.present)
intel_panel_set_backlight(intel_connector, bclp, 255);
}
iowrite32(DIV_ROUND_UP(bclp * 100, 255) | ASLE_CBLV_VALID, &asle->cblv); iowrite32(DIV_ROUND_UP(bclp * 100, 255) | ASLE_CBLV_VALID, &asle->cblv);
out:
mutex_unlock(&dev->mode_config.mutex); mutex_unlock(&dev->mode_config.mutex);
return ret;
return 0;
} }
static u32 asle_set_als_illum(struct drm_device *dev, u32 alsi) static u32 asle_set_als_illum(struct drm_device *dev, u32 alsi)
......
drivers/gpu/drm/i915/intel_panel.c
View file @ da32cc90
This diff is collapsed.
drivers/gpu/drm/i915/intel_pm.c
View file @ da32cc90
This diff is collapsed.
drivers/gpu/drm/i915/intel_ringbuffer.c
View file @ da32cc90
...@@ -285,14 +285,16 @@ static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value) ...@@ -285,14 +285,16 @@ static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value)
if (!ring->fbc_dirty) if (!ring->fbc_dirty)
return 0; return 0;
ret = intel_ring_begin(ring, 4); ret = intel_ring_begin(ring, 6);
if (ret) if (ret)
return ret; return ret;
intel_ring_emit(ring, MI_NOOP);
/* WaFbcNukeOn3DBlt:ivb/hsw */ /* WaFbcNukeOn3DBlt:ivb/hsw */
intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
intel_ring_emit(ring, MSG_FBC_REND_STATE); intel_ring_emit(ring, MSG_FBC_REND_STATE);
intel_ring_emit(ring, value); intel_ring_emit(ring, value);
intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
intel_ring_emit(ring, MSG_FBC_REND_STATE);
intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
intel_ring_advance(ring); intel_ring_advance(ring);
ring->fbc_dirty = false; ring->fbc_dirty = false;
...@@ -354,7 +356,7 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring, ...@@ -354,7 +356,7 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring,
intel_ring_emit(ring, 0); intel_ring_emit(ring, 0);
intel_ring_advance(ring); intel_ring_advance(ring);
if (flush_domains) if (!invalidate_domains && flush_domains)
return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
return 0; return 0;
...@@ -436,7 +438,7 @@ static int init_ring_common(struct intel_ring_buffer *ring) ...@@ -436,7 +438,7 @@ static int init_ring_common(struct intel_ring_buffer *ring)
int ret = 0; int ret = 0;
u32 head; u32 head;
gen6_gt_force_wake_get(dev_priv); gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
if (I915_NEED_GFX_HWS(dev)) if (I915_NEED_GFX_HWS(dev))
intel_ring_setup_status_page(ring); intel_ring_setup_status_page(ring);
...@@ -509,7 +511,7 @@ static int init_ring_common(struct intel_ring_buffer *ring) ...@@ -509,7 +511,7 @@ static int init_ring_common(struct intel_ring_buffer *ring)
memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
out: out:
gen6_gt_force_wake_put(dev_priv); gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
return ret; return ret;
} }
...@@ -965,6 +967,7 @@ void intel_ring_setup_status_page(struct intel_ring_buffer *ring) ...@@ -965,6 +967,7 @@ void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
} else if (IS_GEN6(ring->dev)) { } else if (IS_GEN6(ring->dev)) {
mmio = RING_HWS_PGA_GEN6(ring->mmio_base); mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
} else { } else {
/* XXX: gen8 returns to sanity */
mmio = RING_HWS_PGA(ring->mmio_base); mmio = RING_HWS_PGA(ring->mmio_base);
} }
...@@ -1029,11 +1032,6 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring) ...@@ -1029,11 +1032,6 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring)
if (!dev->irq_enabled) if (!dev->irq_enabled)
return false; return false;
/* It looks like we need to prevent the gt from suspending while waiting
* for an notifiy irq, otherwise irqs seem to get lost on at least the
* blt/bsd rings on ivb. */
gen6_gt_force_wake_get(dev_priv);
spin_lock_irqsave(&dev_priv->irq_lock, flags); spin_lock_irqsave(&dev_priv->irq_lock, flags);
if (ring->irq_refcount++ == 0) { if (ring->irq_refcount++ == 0) {
if (HAS_L3_DPF(dev) && ring->id == RCS) if (HAS_L3_DPF(dev) && ring->id == RCS)
...@@ -1065,8 +1063,6 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring) ...@@ -1065,8 +1063,6 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring)
ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask); ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
} }
spin_unlock_irqrestore(&dev_priv->irq_lock, flags); spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
gen6_gt_force_wake_put(dev_priv);
} }
static bool static bool
...@@ -1837,7 +1833,7 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring, ...@@ -1837,7 +1833,7 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring,
} }
intel_ring_advance(ring); intel_ring_advance(ring);
if (IS_GEN7(dev) && flush) if (IS_GEN7(dev) && !invalidate && flush)
return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN); return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
return 0; return 0;
......
drivers/gpu/drm/i915/intel_sdvo.c
View file @ da32cc90
This diff is collapsed.
drivers/gpu/drm/i915/intel_sideband.c
View file @ da32cc90
...@@ -90,6 +90,22 @@ void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val) ...@@ -90,6 +90,22 @@ void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->dpio_lock);
} }
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg)
{
u32 val = 0;
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT,
PUNIT_OPCODE_REG_READ, reg, &val);
return val;
}
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
{
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT,
PUNIT_OPCODE_REG_WRITE, reg, &val);
}
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr) u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
{ {
u32 val = 0; u32 val = 0;
...@@ -160,27 +176,18 @@ void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) ...@@ -160,27 +176,18 @@ void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
PUNIT_OPCODE_REG_WRITE, reg, &val); PUNIT_OPCODE_REG_WRITE, reg, &val);
} }
static u32 vlv_get_phy_port(enum pipe pipe)
{
u32 port = IOSF_PORT_DPIO;
WARN_ON ((pipe != PIPE_A) && (pipe != PIPE_B));
return port;
}
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg) u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
{ {
u32 val = 0; u32 val = 0;
vlv_sideband_rw(dev_priv, DPIO_DEVFN, vlv_get_phy_port(pipe), vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
DPIO_OPCODE_REG_READ, reg, &val); DPIO_OPCODE_REG_READ, reg, &val);
return val; return val;
} }
void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val) void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val)
{ {
vlv_sideband_rw(dev_priv, DPIO_DEVFN, vlv_get_phy_port(pipe), vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
DPIO_OPCODE_REG_WRITE, reg, &val); DPIO_OPCODE_REG_WRITE, reg, &val);
} }
......
drivers/gpu/drm/i915/intel_sprite.c
View file @ da32cc90
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drivers/gpu/drm/i915/intel_uncore.c
View file @ da32cc90
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include/uapi/drm/i915_drm.h
View file @ da32cc90
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