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Commit da4c99c2 authored by Fabio Aiuto's avatar Fabio Aiuto Committed by Greg Kroah-Hartman
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staging: rtl8723bs: remove RF_*TX enum 

remove RF_*TX enum, its only used value is RF_1TX.
So remove it and remove all indexes and loop over
these enum items.
Signed-off-by: default avatarFabio Aiuto <fabioaiuto83@gmail.com>
Link: https://lore.kernel.org/r/3acc624742a933d90e83a83babb4eecb193cf869.1628329348.git.fabioaiuto83@gmail.comSigned-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 1b09e388
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Showing with 64 additions and 112 deletions
drivers/staging/rtl8723bs/hal/HalHWImg8723B_BB.c
View file @ da4c99c2
...@@ -543,12 +543,12 @@ void ODM_ReadAndConfig_MP_8723B_PHY_REG(struct dm_odm_t *pDM_Odm) ...@@ -543,12 +543,12 @@ void ODM_ReadAndConfig_MP_8723B_PHY_REG(struct dm_odm_t *pDM_Odm)
******************************************************************************/ ******************************************************************************/
static u32 Array_MP_8723B_PHY_REG_PG[] = { static u32 Array_MP_8723B_PHY_REG_PG[] = {
0, 0, 0x00000e08, 0x0000ff00, 0x00003800, 0, 0x00000e08, 0x0000ff00, 0x00003800,
0, 0, 0x0000086c, 0xffffff00, 0x32343600, 0, 0x0000086c, 0xffffff00, 0x32343600,
0, 0, 0x00000e00, 0xffffffff, 0x40424444, 0, 0x00000e00, 0xffffffff, 0x40424444,
0, 0, 0x00000e04, 0xffffffff, 0x28323638, 0, 0x00000e04, 0xffffffff, 0x28323638,
0, 0, 0x00000e10, 0xffffffff, 0x38404244, 0, 0x00000e10, 0xffffffff, 0x38404244,
0, 0, 0x00000e14, 0xffffffff, 0x26303436 0, 0x00000e14, 0xffffffff, 0x26303436
}; };
void ODM_ReadAndConfig_MP_8723B_PHY_REG_PG(struct dm_odm_t *pDM_Odm) void ODM_ReadAndConfig_MP_8723B_PHY_REG_PG(struct dm_odm_t *pDM_Odm)
...@@ -559,13 +559,12 @@ void ODM_ReadAndConfig_MP_8723B_PHY_REG_PG(struct dm_odm_t *pDM_Odm) ...@@ -559,13 +559,12 @@ void ODM_ReadAndConfig_MP_8723B_PHY_REG_PG(struct dm_odm_t *pDM_Odm)
pDM_Odm->PhyRegPgVersion = 1; pDM_Odm->PhyRegPgVersion = 1;
pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE;
for (i = 0; i < ARRAY_SIZE(Array_MP_8723B_PHY_REG_PG); i += 5) { for (i = 0; i < ARRAY_SIZE(Array_MP_8723B_PHY_REG_PG); i += 4) {
u32 v1 = Array[i]; u32 v1 = Array[i];
u32 v2 = Array[i+1]; u32 v2 = Array[i+1];
u32 v3 = Array[i+2]; u32 v3 = Array[i+2];
u32 v4 = Array[i+3]; u32 v4 = Array[i+3];
u32 v5 = Array[i+4];
odm_ConfigBB_PHY_REG_PG_8723B(pDM_Odm, v1, v2, v3, v4, v5); odm_ConfigBB_PHY_REG_PG_8723B(pDM_Odm, v1, v2, v3, v4);
} }
} }
drivers/staging/rtl8723bs/hal/hal_com_phycfg.c
View file @ da4c99c2
...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
#include <linux/kernel.h> #include <linux/kernel.h>
u8 PHY_GetTxPowerByRateBase(struct adapter *Adapter, u8 RfPath, u8 PHY_GetTxPowerByRateBase(struct adapter *Adapter, u8 RfPath,
u8 TxNum, enum rate_section RateSection) enum rate_section RateSection)
{ {
struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
u8 value = 0; u8 value = 0;
...@@ -21,13 +21,13 @@ u8 PHY_GetTxPowerByRateBase(struct adapter *Adapter, u8 RfPath, ...@@ -21,13 +21,13 @@ u8 PHY_GetTxPowerByRateBase(struct adapter *Adapter, u8 RfPath,
switch (RateSection) { switch (RateSection) {
case CCK: case CCK:
value = pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][0]; value = pHalData->TxPwrByRateBase2_4G[RfPath][0];
break; break;
case OFDM: case OFDM:
value = pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][1]; value = pHalData->TxPwrByRateBase2_4G[RfPath][1];
break; break;
case HT_MCS0_MCS7: case HT_MCS0_MCS7:
value = pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][2]; value = pHalData->TxPwrByRateBase2_4G[RfPath][2];
break; break;
default: default:
break; break;
...@@ -37,13 +37,8 @@ u8 PHY_GetTxPowerByRateBase(struct adapter *Adapter, u8 RfPath, ...@@ -37,13 +37,8 @@ u8 PHY_GetTxPowerByRateBase(struct adapter *Adapter, u8 RfPath,
} }
static void static void
phy_SetTxPowerByRateBase( phy_SetTxPowerByRateBase(struct adapter *Adapter, u8 RfPath,
struct adapter *Adapter, enum rate_section RateSection, u8 Value)
u8 RfPath,
enum rate_section RateSection,
u8 TxNum,
u8 Value
)
{ {
struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
...@@ -52,13 +47,13 @@ phy_SetTxPowerByRateBase( ...@@ -52,13 +47,13 @@ phy_SetTxPowerByRateBase(
switch (RateSection) { switch (RateSection) {
case CCK: case CCK:
pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][0] = Value; pHalData->TxPwrByRateBase2_4G[RfPath][0] = Value;
break; break;
case OFDM: case OFDM:
pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][1] = Value; pHalData->TxPwrByRateBase2_4G[RfPath][1] = Value;
break; break;
case HT_MCS0_MCS7: case HT_MCS0_MCS7:
pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][2] = Value; pHalData->TxPwrByRateBase2_4G[RfPath][2] = Value;
break; break;
default: default:
break; break;
...@@ -73,14 +68,14 @@ struct adapter *padapter ...@@ -73,14 +68,14 @@ struct adapter *padapter
u8 path, base; u8 path, base;
for (path = RF_PATH_A; path <= RF_PATH_B; ++path) { for (path = RF_PATH_A; path <= RF_PATH_B; ++path) {
base = PHY_GetTxPowerByRate(padapter, path, RF_1TX, MGN_11M); base = PHY_GetTxPowerByRate(padapter, path, MGN_11M);
phy_SetTxPowerByRateBase(padapter, path, CCK, RF_1TX, base); phy_SetTxPowerByRateBase(padapter, path, CCK, base);
base = PHY_GetTxPowerByRate(padapter, path, RF_1TX, MGN_54M); base = PHY_GetTxPowerByRate(padapter, path, MGN_54M);
phy_SetTxPowerByRateBase(padapter, path, OFDM, RF_1TX, base); phy_SetTxPowerByRateBase(padapter, path, OFDM, base);
base = PHY_GetTxPowerByRate(padapter, path, RF_1TX, MGN_MCS7); base = PHY_GetTxPowerByRate(padapter, path, MGN_MCS7);
phy_SetTxPowerByRateBase(padapter, path, HT_MCS0_MCS7, RF_1TX, base); phy_SetTxPowerByRateBase(padapter, path, HT_MCS0_MCS7, base);
} }
} }
...@@ -320,14 +315,8 @@ PHY_GetRateValuesOfTxPowerByRate( ...@@ -320,14 +315,8 @@ PHY_GetRateValuesOfTxPowerByRate(
} }
} }
static void PHY_StoreTxPowerByRateNew( static void PHY_StoreTxPowerByRateNew(struct adapter *padapter, u32 RfPath,
struct adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data)
u32 RfPath,
u32 TxNum,
u32 RegAddr,
u32 BitMask,
u32 Data
)
{ {
struct hal_com_data *pHalData = GET_HAL_DATA(padapter); struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
u8 i = 0, rateIndex[4] = {0}, rateNum = 0; u8 i = 0, rateIndex[4] = {0}, rateNum = 0;
...@@ -338,11 +327,8 @@ static void PHY_StoreTxPowerByRateNew( ...@@ -338,11 +327,8 @@ static void PHY_StoreTxPowerByRateNew(
if (RfPath >= RF_PATH_MAX) if (RfPath >= RF_PATH_MAX)
return; return;
if (TxNum > RF_MAX_TX_NUM)
return;
for (i = 0; i < rateNum; ++i) { for (i = 0; i < rateNum; ++i) {
pHalData->TxPwrByRateOffset[RfPath][TxNum][rateIndex[i]] = PwrByRateVal[i]; pHalData->TxPwrByRateOffset[RfPath][rateIndex[i]] = PwrByRateVal[i];
} }
} }
...@@ -359,18 +345,16 @@ static void PHY_StoreTxPowerByRateOld( ...@@ -359,18 +345,16 @@ static void PHY_StoreTxPowerByRateOld(
void PHY_InitTxPowerByRate(struct adapter *padapter) void PHY_InitTxPowerByRate(struct adapter *padapter)
{ {
struct hal_com_data *pHalData = GET_HAL_DATA(padapter); struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
u8 rfPath, TxNum, rate; u8 rfPath, rate;
for (rfPath = 0; rfPath < TX_PWR_BY_RATE_NUM_RF; ++rfPath) for (rfPath = 0; rfPath < TX_PWR_BY_RATE_NUM_RF; ++rfPath)
for (TxNum = 0; TxNum < TX_PWR_BY_RATE_NUM_RF; ++TxNum) for (rate = 0; rate < TX_PWR_BY_RATE_NUM_RATE; ++rate)
for (rate = 0; rate < TX_PWR_BY_RATE_NUM_RATE; ++rate) pHalData->TxPwrByRateOffset[rfPath][rate] = 0;
pHalData->TxPwrByRateOffset[rfPath][TxNum][rate] = 0;
} }
void PHY_StoreTxPowerByRate( void PHY_StoreTxPowerByRate(
struct adapter *padapter, struct adapter *padapter,
u32 RfPath, u32 RfPath,
u32 TxNum,
u32 RegAddr, u32 RegAddr,
u32 BitMask, u32 BitMask,
u32 Data u32 Data
...@@ -380,7 +364,7 @@ void PHY_StoreTxPowerByRate( ...@@ -380,7 +364,7 @@ void PHY_StoreTxPowerByRate(
struct dm_odm_t *pDM_Odm = &pHalData->odmpriv; struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
if (pDM_Odm->PhyRegPgVersion > 0) if (pDM_Odm->PhyRegPgVersion > 0)
PHY_StoreTxPowerByRateNew(padapter, RfPath, TxNum, RegAddr, BitMask, Data); PHY_StoreTxPowerByRateNew(padapter, RfPath, RegAddr, BitMask, Data);
else if (pDM_Odm->PhyRegPgVersion == 0) { else if (pDM_Odm->PhyRegPgVersion == 0) {
PHY_StoreTxPowerByRateOld(padapter, RegAddr, BitMask, Data); PHY_StoreTxPowerByRateOld(padapter, RegAddr, BitMask, Data);
} }
...@@ -391,7 +375,7 @@ phy_ConvertTxPowerByRateInDbmToRelativeValues( ...@@ -391,7 +375,7 @@ phy_ConvertTxPowerByRateInDbmToRelativeValues(
struct adapter *padapter struct adapter *padapter
) )
{ {
u8 base = 0, i = 0, value = 0, path = 0, txNum = 0; u8 base = 0, i = 0, value = 0, path = 0;
u8 cckRates[4] = { u8 cckRates[4] = {
MGN_1M, MGN_2M, MGN_5_5M, MGN_11M MGN_1M, MGN_2M, MGN_5_5M, MGN_11M
}; };
...@@ -402,28 +386,25 @@ struct adapter *padapter ...@@ -402,28 +386,25 @@ struct adapter *padapter
MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7 MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7
}; };
for (path = RF_PATH_A; path < RF_PATH_MAX; ++path) { for (path = RF_PATH_A; path < RF_PATH_MAX; ++path) {
for (txNum = RF_1TX; txNum < RF_MAX_TX_NUM; ++txNum) { /* CCK */
/* CCK */ base = PHY_GetTxPowerByRate(padapter, path, MGN_11M);
base = PHY_GetTxPowerByRate(padapter, path, txNum, MGN_11M); for (i = 0; i < ARRAY_SIZE(cckRates); ++i) {
for (i = 0; i < ARRAY_SIZE(cckRates); ++i) { value = PHY_GetTxPowerByRate(padapter, path, cckRates[i]);
value = PHY_GetTxPowerByRate(padapter, path, txNum, cckRates[i]); PHY_SetTxPowerByRate(padapter, path, cckRates[i], value - base);
PHY_SetTxPowerByRate(padapter, path, txNum, cckRates[i], value - base); }
}
/* OFDM */
base = PHY_GetTxPowerByRate(padapter, path, txNum, MGN_54M);
for (i = 0; i < sizeof(ofdmRates); ++i) {
value = PHY_GetTxPowerByRate(padapter, path, txNum, ofdmRates[i]);
PHY_SetTxPowerByRate(padapter, path, txNum, ofdmRates[i], value - base);
}
/* HT MCS0~7 */ /* OFDM */
base = PHY_GetTxPowerByRate(padapter, path, txNum, MGN_MCS7); base = PHY_GetTxPowerByRate(padapter, path, MGN_54M);
for (i = 0; i < sizeof(mcs0_7Rates); ++i) { for (i = 0; i < sizeof(ofdmRates); ++i) {
value = PHY_GetTxPowerByRate(padapter, path, txNum, mcs0_7Rates[i]); value = PHY_GetTxPowerByRate(padapter, path, ofdmRates[i]);
PHY_SetTxPowerByRate(padapter, path, txNum, mcs0_7Rates[i], value - base); PHY_SetTxPowerByRate(padapter, path, ofdmRates[i], value - base);
} }
/* HT MCS0~7 */
base = PHY_GetTxPowerByRate(padapter, path, MGN_MCS7);
for (i = 0; i < sizeof(mcs0_7Rates); ++i) {
value = PHY_GetTxPowerByRate(padapter, path, mcs0_7Rates[i]);
PHY_SetTxPowerByRate(padapter, path, mcs0_7Rates[i], value - base);
} }
} }
} }
...@@ -590,9 +571,7 @@ u8 PHY_GetRateIndexOfTxPowerByRate(u8 Rate) ...@@ -590,9 +571,7 @@ u8 PHY_GetRateIndexOfTxPowerByRate(u8 Rate)
return index; return index;
} }
s8 PHY_GetTxPowerByRate( s8 PHY_GetTxPowerByRate(struct adapter *padapter, u8 RFPath, u8 Rate)
struct adapter *padapter, u8 RFPath, u8 TxNum, u8 Rate
)
{ {
struct hal_com_data *pHalData = GET_HAL_DATA(padapter); struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
s8 value = 0; s8 value = 0;
...@@ -605,20 +584,16 @@ s8 PHY_GetTxPowerByRate( ...@@ -605,20 +584,16 @@ s8 PHY_GetTxPowerByRate(
if (RFPath >= RF_PATH_MAX) if (RFPath >= RF_PATH_MAX)
return value; return value;
if (TxNum >= RF_MAX_TX_NUM)
return value;
if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE)
return value; return value;
return pHalData->TxPwrByRateOffset[RFPath][TxNum][rateIndex]; return pHalData->TxPwrByRateOffset[RFPath][rateIndex];
} }
void PHY_SetTxPowerByRate( void PHY_SetTxPowerByRate(
struct adapter *padapter, struct adapter *padapter,
u8 RFPath, u8 RFPath,
u8 TxNum,
u8 Rate, u8 Rate,
s8 Value s8 Value
) )
...@@ -629,13 +604,10 @@ void PHY_SetTxPowerByRate( ...@@ -629,13 +604,10 @@ void PHY_SetTxPowerByRate(
if (RFPath >= RF_PATH_MAX) if (RFPath >= RF_PATH_MAX)
return; return;
if (TxNum >= RF_MAX_TX_NUM)
return;
if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE)
return; return;
pHalData->TxPwrByRateOffset[RFPath][TxNum][rateIndex] = Value; pHalData->TxPwrByRateOffset[RFPath][rateIndex] = Value;
} }
void PHY_SetTxPowerLevelByPath(struct adapter *Adapter, u8 channel, u8 path) void PHY_SetTxPowerLevelByPath(struct adapter *Adapter, u8 channel, u8 path)
...@@ -797,11 +769,11 @@ void PHY_ConvertTxPowerLimitToPowerIndex(struct adapter *Adapter) ...@@ -797,11 +769,11 @@ void PHY_ConvertTxPowerLimitToPowerIndex(struct adapter *Adapter)
for (rfPath = RF_PATH_A; rfPath < MAX_RF_PATH_NUM; ++rfPath) { for (rfPath = RF_PATH_A; rfPath < MAX_RF_PATH_NUM; ++rfPath) {
if (pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_EXACT_VALUE) { if (pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_EXACT_VALUE) {
if (rateSection == 2) /* HT 1T */ if (rateSection == 2) /* HT 1T */
BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, rfPath, RF_1TX, HT_MCS0_MCS7); BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, rfPath, HT_MCS0_MCS7);
else if (rateSection == 1) /* OFDM */ else if (rateSection == 1) /* OFDM */
BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, rfPath, RF_1TX, OFDM); BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, rfPath, OFDM);
else if (rateSection == 0) /* CCK */ else if (rateSection == 0) /* CCK */
BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, rfPath, RF_1TX, CCK); BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, rfPath, CCK);
} else } else
BW40PwrBasedBm2_4G = Adapter->registrypriv.RegPowerBase * 2; BW40PwrBasedBm2_4G = Adapter->registrypriv.RegPowerBase * 2;
......
drivers/staging/rtl8723bs/hal/odm_RegConfig8723B.c
View file @ da4c99c2
...@@ -118,7 +118,6 @@ void odm_ConfigBB_AGC_8723B( ...@@ -118,7 +118,6 @@ void odm_ConfigBB_AGC_8723B(
void odm_ConfigBB_PHY_REG_PG_8723B( void odm_ConfigBB_PHY_REG_PG_8723B(
struct dm_odm_t *pDM_Odm, struct dm_odm_t *pDM_Odm,
u32 RfPath, u32 RfPath,
u32 TxNum,
u32 Addr, u32 Addr,
u32 Bitmask, u32 Bitmask,
u32 Data u32 Data
...@@ -127,7 +126,7 @@ void odm_ConfigBB_PHY_REG_PG_8723B( ...@@ -127,7 +126,7 @@ void odm_ConfigBB_PHY_REG_PG_8723B(
if (Addr == 0xfe || Addr == 0xffe) if (Addr == 0xfe || Addr == 0xffe)
msleep(50); msleep(50);
else { else {
PHY_StoreTxPowerByRate(pDM_Odm->Adapter, RfPath, TxNum, Addr, Bitmask, Data); PHY_StoreTxPowerByRate(pDM_Odm->Adapter, RfPath, Addr, Bitmask, Data);
} }
} }
......
drivers/staging/rtl8723bs/hal/odm_RegConfig8723B.h
View file @ da4c99c2
...@@ -24,13 +24,8 @@ void odm_ConfigBB_AGC_8723B(struct dm_odm_t *pDM_Odm, ...@@ -24,13 +24,8 @@ void odm_ConfigBB_AGC_8723B(struct dm_odm_t *pDM_Odm,
u32 Data u32 Data
); );
void odm_ConfigBB_PHY_REG_PG_8723B(struct dm_odm_t *pDM_Odm, void odm_ConfigBB_PHY_REG_PG_8723B(struct dm_odm_t *pDM_Odm, u32 RfPath, u32 Addr,
u32 RfPath, u32 Bitmask, u32 Data);
u32 TxNum,
u32 Addr,
u32 Bitmask,
u32 Data
);
void odm_ConfigBB_PHY_8723B(struct dm_odm_t *pDM_Odm, void odm_ConfigBB_PHY_8723B(struct dm_odm_t *pDM_Odm,
u32 Addr, u32 Addr,
......
drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
View file @ da4c99c2
...@@ -538,7 +538,7 @@ u8 PHY_GetTxPowerIndex( ...@@ -538,7 +538,7 @@ u8 PHY_GetTxPowerIndex(
s8 txPower = 0, powerDiffByRate = 0, limit = 0; s8 txPower = 0, powerDiffByRate = 0, limit = 0;
txPower = (s8) PHY_GetTxPowerIndexBase(padapter, RFPath, Rate, BandWidth, Channel); txPower = (s8) PHY_GetTxPowerIndexBase(padapter, RFPath, Rate, BandWidth, Channel);
powerDiffByRate = PHY_GetTxPowerByRate(padapter, RF_PATH_A, RF_1TX, Rate); powerDiffByRate = PHY_GetTxPowerByRate(padapter, RF_PATH_A, Rate);
limit = phy_get_tx_pwr_lmt( limit = phy_get_tx_pwr_lmt(
padapter, padapter,
......
drivers/staging/rtl8723bs/include/hal_com_phycfg.h
View file @ da4c99c2
...@@ -18,15 +18,6 @@ enum rate_section { ...@@ -18,15 +18,6 @@ enum rate_section {
HT_MCS0_MCS7, HT_MCS0_MCS7,
}; };
enum {
RF_1TX = 0,
RF_2TX,
RF_3TX,
RF_4TX,
RF_MAX_TX_NUM,
RF_TX_NUM_NONIMPLEMENT,
};
#define MAX_POWER_INDEX 0x3F #define MAX_POWER_INDEX 0x3F
enum { enum {
...@@ -63,7 +54,7 @@ struct bb_register_def { ...@@ -63,7 +54,7 @@ struct bb_register_def {
}; };
u8 PHY_GetTxPowerByRateBase(struct adapter *Adapter, u8 RfPath, u8 TxNum, u8 PHY_GetTxPowerByRateBase(struct adapter *Adapter, u8 RfPath,
enum rate_section RateSection); enum rate_section RateSection);
u8 PHY_GetRateSectionIndexOfTxPowerByRate(struct adapter *padapter, u32 RegAddr, u8 PHY_GetRateSectionIndexOfTxPowerByRate(struct adapter *padapter, u32 RegAddr,
...@@ -78,9 +69,9 @@ u8 PHY_GetRateIndexOfTxPowerByRate(u8 Rate); ...@@ -78,9 +69,9 @@ u8 PHY_GetRateIndexOfTxPowerByRate(u8 Rate);
void PHY_SetTxPowerIndexByRateSection(struct adapter *padapter, u8 RFPath, u8 Channel, void PHY_SetTxPowerIndexByRateSection(struct adapter *padapter, u8 RFPath, u8 Channel,
u8 RateSection); u8 RateSection);
s8 PHY_GetTxPowerByRate(struct adapter *padapter, u8 RFPath, u8 TxNum, u8 RateIndex); s8 PHY_GetTxPowerByRate(struct adapter *padapter, u8 RFPath, u8 RateIndex);
void PHY_SetTxPowerByRate(struct adapter *padapter, u8 RFPath, u8 TxNum, u8 Rate, void PHY_SetTxPowerByRate(struct adapter *padapter, u8 RFPath, u8 Rate,
s8 Value); s8 Value);
void PHY_SetTxPowerLevelByPath(struct adapter *Adapter, u8 channel, u8 path); void PHY_SetTxPowerLevelByPath(struct adapter *Adapter, u8 channel, u8 path);
...@@ -91,7 +82,7 @@ void PHY_SetTxPowerIndexByRateArray(struct adapter *padapter, u8 RFPath, ...@@ -91,7 +82,7 @@ void PHY_SetTxPowerIndexByRateArray(struct adapter *padapter, u8 RFPath,
void PHY_InitTxPowerByRate(struct adapter *padapter); void PHY_InitTxPowerByRate(struct adapter *padapter);
void PHY_StoreTxPowerByRate(struct adapter *padapter, u32 RfPath, u32 TxNum, void PHY_StoreTxPowerByRate(struct adapter *padapter, u32 RfPath,
u32 RegAddr, u32 BitMask, u32 Data); u32 RegAddr, u32 BitMask, u32 Data);
void PHY_TxPowerByRateConfiguration(struct adapter *padapter); void PHY_TxPowerByRateConfiguration(struct adapter *padapter);
......
drivers/staging/rtl8723bs/include/hal_data.h
View file @ da4c99c2
...@@ -241,9 +241,7 @@ struct hal_com_data { ...@@ -241,9 +241,7 @@ struct hal_com_data {
/* CCK = 0 OFDM = 1/2 HT-MCS 0-15 =3/4/56 VHT =7/8/9/10/11 */ /* CCK = 0 OFDM = 1/2 HT-MCS 0-15 =3/4/56 VHT =7/8/9/10/11 */
u8 TxPwrByRateTable; u8 TxPwrByRateTable;
u8 TxPwrByRateBand; u8 TxPwrByRateBand;
s8 TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_RF] s8 TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_RF][TX_PWR_BY_RATE_NUM_RATE];
[TX_PWR_BY_RATE_NUM_RF]
[TX_PWR_BY_RATE_NUM_RATE];
/* */ /* */
/* 2 Power Limit Table */ /* 2 Power Limit Table */
...@@ -261,9 +259,7 @@ struct hal_com_data { ...@@ -261,9 +259,7 @@ struct hal_com_data {
[MAX_RF_PATH_NUM]; [MAX_RF_PATH_NUM];
/* Store the original power by rate value of the base of each rate section of rf path A & B */ /* Store the original power by rate value of the base of each rate section of rf path A & B */
u8 TxPwrByRateBase2_4G[TX_PWR_BY_RATE_NUM_RF] u8 TxPwrByRateBase2_4G[TX_PWR_BY_RATE_NUM_RF][MAX_BASE_NUM_IN_PHY_REG_PG_2_4G];
[TX_PWR_BY_RATE_NUM_RF]
[MAX_BASE_NUM_IN_PHY_REG_PG_2_4G];
/* For power group */ /* For power group */
u8 PwrGroupHT20[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; u8 PwrGroupHT20[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];
......
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