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Commit da98d99b authored by Luben Tuikov's avatar Luben Tuikov Committed by Alex Deucher
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drm/amd/pm: Simplify managed I2C transfer of Aldebaran 

Simplify Aldebaran managed I2C transfer function
to correctly play with the upper I2C layers.

This gets it in line with Navi10, Acturus, and
Sienna Cichlid.

Cc: Alexander Deucher <Alexander.Deucher@amd.com>
Cc: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Cc: Lijo Lazar <Lijo.Lazar@amd.com>
Cc: John Clements <john.clements@amd.com>
Cc: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarLuben Tuikov <luben.tuikov@amd.com>
Reviewed-by: default avatarAlexander Deucher <Alexander.Deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9de96f3f
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Showing with 55 additions and 175 deletions
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
View file @ da98d99b
......@@ -1425,197 +1425,77 @@ static bool aldebaran_is_dpm_running(struct smu_context *smu)
return !!(feature_enabled & SMC_DPM_FEATURE);
}
static void aldebaran_fill_i2c_req(SwI2cRequest_t *req, bool write,
uint8_t address, uint32_t numbytes,
uint8_t *data)
{
int i;
req->I2CcontrollerPort = 0;
req->I2CSpeed = 2;
req->SlaveAddress = address;
req->NumCmds = numbytes;
for (i = 0; i < numbytes; i++) {
SwI2cCmd_t *cmd = &req->SwI2cCmds[i];
/* First 2 bytes are always write for lower 2b EEPROM address */
if (i < 2)
cmd->CmdConfig = CMDCONFIG_READWRITE_MASK;
else
cmd->CmdConfig = write ? CMDCONFIG_READWRITE_MASK : 0;
/* Add RESTART for read after address filled */
cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
/* Add STOP in the end */
cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
/* Fill with data regardless if read or write to simplify code */
cmd->ReadWriteData = data[i];
}
}
static int aldebaran_i2c_read_data(struct i2c_adapter *control,
uint8_t address,
uint8_t *data,
uint32_t numbytes)
static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap,
struct i2c_msg *msg, int num_msgs)
{
uint32_t i, ret = 0;
SwI2cRequest_t req;
struct amdgpu_device *adev = to_amdgpu_device(control);
struct amdgpu_device *adev = to_amdgpu_device(i2c_adap);
struct smu_table_context *smu_table = &adev->smu.smu_table;
struct smu_table *table = &smu_table->driver_table;
SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
int i, j, r, c;
u16 dir;
if (numbytes > MAX_SW_I2C_COMMANDS) {
dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
numbytes, MAX_SW_I2C_COMMANDS);
return -EINVAL;
}
memset(&req, 0, sizeof(req));
aldebaran_fill_i2c_req(&req, false, address, numbytes, data);
mutex_lock(&adev->smu.mutex);
/* Now read data starting with that address */
ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
true);
mutex_unlock(&adev->smu.mutex);
if (!ret) {
SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
/* Assume SMU fills res.SwI2cCmds[i].Data with read bytes */
for (i = 0; i < numbytes; i++)
data[i] = res->SwI2cCmds[i].ReadWriteData;
dev_dbg(adev->dev, "aldebaran_i2c_read_data, address = %x, bytes = %d, data :",
(uint16_t)address, numbytes);
print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
8, 1, data, numbytes, false);
} else
dev_err(adev->dev, "aldebaran_i2c_read_data - error occurred :%x", ret);
req = kzalloc(sizeof(*req), GFP_KERNEL);
if (!req)
return -ENOMEM;
return ret;
}
req->I2CcontrollerPort = 0;
req->I2CSpeed = I2C_SPEED_FAST_400K;
req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
dir = msg[0].flags & I2C_M_RD;
for (c = i = 0; i < num_msgs; i++) {
for (j = 0; j < msg[i].len; j++, c++) {
SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
if (!(msg[i].flags & I2C_M_RD)) {
/* write */
cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
cmd->ReadWriteData = msg[i].buf[j];
}
static int aldebaran_i2c_write_data(struct i2c_adapter *control,
uint8_t address,
uint8_t *data,
uint32_t numbytes)
{
uint32_t ret;
SwI2cRequest_t req;
struct amdgpu_device *adev = to_amdgpu_device(control);
if ((dir ^ msg[i].flags) & I2C_M_RD) {
/* The direction changes.
*/
dir = msg[i].flags & I2C_M_RD;
cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
}
if (numbytes > MAX_SW_I2C_COMMANDS) {
dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
numbytes, MAX_SW_I2C_COMMANDS);
return -EINVAL;
req->NumCmds++;
/*
* Insert STOP if we are at the last byte of either last
* message for the transaction or the client explicitly
* requires a STOP at this particular message.
*/
if ((j == msg[i].len - 1) &&
((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
}
}
}
memset(&req, 0, sizeof(req));
aldebaran_fill_i2c_req(&req, true, address, numbytes, data);
mutex_lock(&adev->smu.mutex);
ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
mutex_unlock(&adev->smu.mutex);
if (r)
goto fail;
if (!ret) {
dev_dbg(adev->dev, "aldebaran_i2c_write(), address = %x, bytes = %d , data: ",
(uint16_t)address, numbytes);
print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
8, 1, data, numbytes, false);
/*
* According to EEPROM spec there is a MAX of 10 ms required for
* EEPROM to flush internal RX buffer after STOP was issued at the
* end of write transaction. During this time the EEPROM will not be
* responsive to any more commands - so wait a bit more.
*/
msleep(10);
} else
dev_err(adev->dev, "aldebaran_i2c_write- error occurred :%x", ret);
return ret;
}
static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap,
struct i2c_msg *msgs, int num)
{
uint32_t i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
for (i = 0; i < num; i++) {
/*
* SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
* once and hence the data needs to be spliced into chunks and sent each
* chunk separately
*/
data_size = msgs[i].len - 2;
data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
data_ptr = msgs[i].buf + 2;
for (j = 0; j < data_size / data_chunk_size; j++) {
/* Insert the EEPROM dest addess, bits 0-15 */
data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
data_chunk[1] = (next_eeprom_addr & 0xff);
if (msgs[i].flags & I2C_M_RD) {
ret = aldebaran_i2c_read_data(i2c_adap,
(uint8_t)msgs[i].addr,
data_chunk, MAX_SW_I2C_COMMANDS);
memcpy(data_ptr, data_chunk + 2, data_chunk_size);
} else {
memcpy(data_chunk + 2, data_ptr, data_chunk_size);
ret = aldebaran_i2c_write_data(i2c_adap,
(uint8_t)msgs[i].addr,
data_chunk, MAX_SW_I2C_COMMANDS);
}
if (ret) {
num = -EIO;
goto fail;
}
next_eeprom_addr += data_chunk_size;
data_ptr += data_chunk_size;
for (c = i = 0; i < num_msgs; i++) {
if (!(msg[i].flags & I2C_M_RD)) {
c += msg[i].len;
continue;
}
for (j = 0; j < msg[i].len; j++, c++) {
SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
if (data_size % data_chunk_size) {
data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
data_chunk[1] = (next_eeprom_addr & 0xff);
if (msgs[i].flags & I2C_M_RD) {
ret = aldebaran_i2c_read_data(i2c_adap,
(uint8_t)msgs[i].addr,
data_chunk, (data_size % data_chunk_size) + 2);
memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
} else {
memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
ret = aldebaran_i2c_write_data(i2c_adap,
(uint8_t)msgs[i].addr,
data_chunk, (data_size % data_chunk_size) + 2);
}
if (ret) {
num = -EIO;
goto fail;
}
msg[i].buf[j] = cmd->ReadWriteData;
}
}
r = num_msgs;
fail:
return num;
kfree(req);
return r;
}
static u32 aldebaran_i2c_func(struct i2c_adapter *adap)
......
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