Commit dadf7956 authored by Thierry Reding's avatar Thierry Reding

Merge branch 'for-5.7/dt-bindings' into for-5.7/arm64/dt

parents bb6d3fb3 cd88f167
...@@ -228,6 +228,8 @@ ...@@ -228,6 +228,8 @@
#define TEGRA114_CLK_CLK_M 201 #define TEGRA114_CLK_CLK_M 201
#define TEGRA114_CLK_CLK_M_DIV2 202 #define TEGRA114_CLK_CLK_M_DIV2 202
#define TEGRA114_CLK_CLK_M_DIV4 203 #define TEGRA114_CLK_CLK_M_DIV4 203
#define TEGRA114_CLK_OSC_DIV2 202
#define TEGRA114_CLK_OSC_DIV4 203
#define TEGRA114_CLK_PLL_REF 204 #define TEGRA114_CLK_PLL_REF 204
#define TEGRA114_CLK_PLL_C 205 #define TEGRA114_CLK_PLL_C 205
#define TEGRA114_CLK_PLL_C_OUT1 206 #define TEGRA114_CLK_PLL_C_OUT1 206
...@@ -274,7 +276,7 @@ ...@@ -274,7 +276,7 @@
#define TEGRA114_CLK_CLK_OUT_2 246 #define TEGRA114_CLK_CLK_OUT_2 246
#define TEGRA114_CLK_CLK_OUT_3 247 #define TEGRA114_CLK_CLK_OUT_3 247
#define TEGRA114_CLK_BLINK 248 #define TEGRA114_CLK_BLINK 248
/* 249 */ #define TEGRA114_CLK_OSC 249
/* 250 */ /* 250 */
/* 251 */ /* 251 */
#define TEGRA114_CLK_XUSB_HOST_SRC 252 #define TEGRA114_CLK_XUSB_HOST_SRC 252
......
...@@ -227,6 +227,8 @@ ...@@ -227,6 +227,8 @@
#define TEGRA124_CLK_CLK_M 201 #define TEGRA124_CLK_CLK_M 201
#define TEGRA124_CLK_CLK_M_DIV2 202 #define TEGRA124_CLK_CLK_M_DIV2 202
#define TEGRA124_CLK_CLK_M_DIV4 203 #define TEGRA124_CLK_CLK_M_DIV4 203
#define TEGRA124_CLK_OSC_DIV2 202
#define TEGRA124_CLK_OSC_DIV4 203
#define TEGRA124_CLK_PLL_REF 204 #define TEGRA124_CLK_PLL_REF 204
#define TEGRA124_CLK_PLL_C 205 #define TEGRA124_CLK_PLL_C 205
#define TEGRA124_CLK_PLL_C_OUT1 206 #define TEGRA124_CLK_PLL_C_OUT1 206
...@@ -273,7 +275,7 @@ ...@@ -273,7 +275,7 @@
#define TEGRA124_CLK_CLK_OUT_2 246 #define TEGRA124_CLK_CLK_OUT_2 246
#define TEGRA124_CLK_CLK_OUT_3 247 #define TEGRA124_CLK_CLK_OUT_3 247
#define TEGRA124_CLK_BLINK 248 #define TEGRA124_CLK_BLINK 248
/* 249 */ #define TEGRA124_CLK_OSC 249
/* 250 */ /* 250 */
/* 251 */ /* 251 */
#define TEGRA124_CLK_XUSB_HOST_SRC 252 #define TEGRA124_CLK_XUSB_HOST_SRC 252
......
...@@ -262,6 +262,8 @@ ...@@ -262,6 +262,8 @@
#define TEGRA210_CLK_CLK_M 233 #define TEGRA210_CLK_CLK_M 233
#define TEGRA210_CLK_CLK_M_DIV2 234 #define TEGRA210_CLK_CLK_M_DIV2 234
#define TEGRA210_CLK_CLK_M_DIV4 235 #define TEGRA210_CLK_CLK_M_DIV4 235
#define TEGRA210_CLK_OSC_DIV2 234
#define TEGRA210_CLK_OSC_DIV4 235
#define TEGRA210_CLK_PLL_REF 236 #define TEGRA210_CLK_PLL_REF 236
#define TEGRA210_CLK_PLL_C 237 #define TEGRA210_CLK_PLL_C 237
#define TEGRA210_CLK_PLL_C_OUT1 238 #define TEGRA210_CLK_PLL_C_OUT1 238
...@@ -355,7 +357,7 @@ ...@@ -355,7 +357,7 @@
#define TEGRA210_CLK_PLL_A_OUT_ADSP 323 #define TEGRA210_CLK_PLL_A_OUT_ADSP 323
#define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324 #define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324
/* 325 */ /* 325 */
/* 326 */ #define TEGRA210_CLK_OSC 326
/* 327 */ /* 327 */
/* 328 */ /* 328 */
/* 329 */ /* 329 */
......
...@@ -196,6 +196,8 @@ ...@@ -196,6 +196,8 @@
#define TEGRA30_CLK_CLK_M 171 #define TEGRA30_CLK_CLK_M 171
#define TEGRA30_CLK_CLK_M_DIV2 172 #define TEGRA30_CLK_CLK_M_DIV2 172
#define TEGRA30_CLK_CLK_M_DIV4 173 #define TEGRA30_CLK_CLK_M_DIV4 173
#define TEGRA30_CLK_OSC_DIV2 172
#define TEGRA30_CLK_OSC_DIV4 173
#define TEGRA30_CLK_PLL_REF 174 #define TEGRA30_CLK_PLL_REF 174
#define TEGRA30_CLK_PLL_C 175 #define TEGRA30_CLK_PLL_C 175
#define TEGRA30_CLK_PLL_C_OUT1 176 #define TEGRA30_CLK_PLL_C_OUT1 176
...@@ -243,7 +245,7 @@ ...@@ -243,7 +245,7 @@
#define TEGRA30_CLK_HCLK 217 #define TEGRA30_CLK_HCLK 217
#define TEGRA30_CLK_PCLK 218 #define TEGRA30_CLK_PCLK 218
/* 219 */ /* 219 */
/* 220 */ #define TEGRA30_CLK_OSC 220
/* 221 */ /* 221 */
/* 222 */ /* 222 */
/* 223 */ /* 223 */
......
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef _DT_BINDINGS_SOC_TEGRA_PMC_H
#define _DT_BINDINGS_SOC_TEGRA_PMC_H
#define TEGRA_PMC_CLK_OUT_1 0
#define TEGRA_PMC_CLK_OUT_2 1
#define TEGRA_PMC_CLK_OUT_3 2
#define TEGRA_PMC_CLK_BLINK 3
#define TEGRA_PMC_CLK_MAX 4
#endif /* _DT_BINDINGS_SOC_TEGRA_PMC_H */
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