Commit dae751f4 authored by Matt Roper's avatar Matt Roper

drm/i915/dg1: Use revid->stepping tables

Switch DG1 to use a revid->stepping table as we're trying to do on all
platforms going forward.

This removes the last use of IS_REVID() and REVID_FOREVER, so remove
those now-unused macros as well to prevent their accidental use on
future platforms.

v2:
 - Use COMMON_STEP() macro in table.  (Anusha)

Bspec: 44463
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarAnusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210713193635.3390052-11-matthew.d.roper@intel.com
parent 97cf9b58
...@@ -5798,7 +5798,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) ...@@ -5798,7 +5798,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
int config, i; int config, i;
if (IS_ALDERLAKE_S(dev_priv) || if (IS_ALDERLAKE_S(dev_priv) ||
IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) || IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
/* Wa_1409767108:tgl,dg1,adl-s */ /* Wa_1409767108:tgl,dg1,adl-s */
table = wa_1409767108_buddy_page_masks; table = wa_1409767108_buddy_page_masks;
......
...@@ -157,7 +157,7 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt) ...@@ -157,7 +157,7 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt)
static bool get_legacy_lowmem_region(struct intel_uncore *uncore, static bool get_legacy_lowmem_region(struct intel_uncore *uncore,
u64 *start, u32 *size) u64 *start, u32 *size)
{ {
if (!IS_DG1_REVID(uncore->i915, DG1_REVID_A0, DG1_REVID_B0)) if (!IS_DG1_GT_STEP(uncore->i915, STEP_A0, STEP_B0))
return false; return false;
*start = 0; *start = 0;
......
...@@ -1146,7 +1146,7 @@ dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) ...@@ -1146,7 +1146,7 @@ dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
gen12_gt_workarounds_init(i915, wal); gen12_gt_workarounds_init(i915, wal);
/* Wa_1607087056:dg1 */ /* Wa_1607087056:dg1 */
if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0)) if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0))
wa_write_or(wal, wa_write_or(wal,
SLICE_UNIT_LEVEL_CLKGATE, SLICE_UNIT_LEVEL_CLKGATE,
L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
...@@ -1542,7 +1542,7 @@ static void dg1_whitelist_build(struct intel_engine_cs *engine) ...@@ -1542,7 +1542,7 @@ static void dg1_whitelist_build(struct intel_engine_cs *engine)
tgl_whitelist_build(engine); tgl_whitelist_build(engine);
/* GEN:BUG:1409280441:dg1 */ /* GEN:BUG:1409280441:dg1 */
if (IS_DG1_REVID(engine->i915, DG1_REVID_A0, DG1_REVID_A0) && if (IS_DG1_GT_STEP(engine->i915, STEP_A0, STEP_A0) &&
(engine->class == RENDER_CLASS || (engine->class == RENDER_CLASS ||
engine->class == COPY_ENGINE_CLASS)) engine->class == COPY_ENGINE_CLASS))
whitelist_reg_ext(w, RING_ID(engine->mmio_base), whitelist_reg_ext(w, RING_ID(engine->mmio_base),
...@@ -1612,7 +1612,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) ...@@ -1612,7 +1612,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{ {
struct drm_i915_private *i915 = engine->i915; struct drm_i915_private *i915 = engine->i915;
if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) || if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) { IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) {
/* /*
* Wa_1607138336:tgl[a0],dg1[a0] * Wa_1607138336:tgl[a0],dg1[a0]
...@@ -1656,7 +1656,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) ...@@ -1656,7 +1656,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
FF_DOP_CLOCK_GATE_DISABLE); FF_DOP_CLOCK_GATE_DISABLE);
} }
if (IS_ALDERLAKE_S(i915) || IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) || if (IS_ALDERLAKE_S(i915) ||
IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
/* Wa_1409804808:tgl,rkl,dg1[a0],adl-s */ /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s */
wa_masked_en(wal, GEN7_ROW_CHICKEN2, wa_masked_en(wal, GEN7_ROW_CHICKEN2,
...@@ -1670,7 +1671,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) ...@@ -1670,7 +1671,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
} }
if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) || if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
/* /*
* Wa_1607030317:tgl * Wa_1607030317:tgl
......
...@@ -1264,19 +1264,10 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) ...@@ -1264,19 +1264,10 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
#define IS_DISPLAY_VER(i915, from, until) \ #define IS_DISPLAY_VER(i915, from, until) \
(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
#define REVID_FOREVER 0xff
#define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision) #define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision)
#define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb) #define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb)
/*
* Return true if revision is in range [since,until] inclusive.
*
* Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
*/
#define IS_REVID(p, since, until) \
(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
#define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step) #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
#define INTEL_GT_STEP(__i915) (RUNTIME_INFO(__i915)->step.gt_step) #define INTEL_GT_STEP(__i915) (RUNTIME_INFO(__i915)->step.gt_step)
...@@ -1493,11 +1484,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, ...@@ -1493,11 +1484,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_RKL_DISPLAY_STEP(p, since, until) \ #define IS_RKL_DISPLAY_STEP(p, since, until) \
(IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until)) (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
#define DG1_REVID_A0 0x0 #define IS_DG1_GT_STEP(p, since, until) \
#define DG1_REVID_B0 0x1 (IS_DG1(p) && IS_GT_STEP(p, since, until))
#define IS_DG1_DISPLAY_STEP(p, since, until) \
#define IS_DG1_REVID(p, since, until) \ (IS_DG1(p) && IS_DISPLAY_STEP(p, since, until))
(IS_DG1(p) && IS_REVID(p, since, until))
#define IS_ADLS_DISPLAY_STEP(__i915, since, until) \ #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
(IS_ALDERLAKE_S(__i915) && \ (IS_ALDERLAKE_S(__i915) && \
......
...@@ -7383,7 +7383,7 @@ static void dg1_init_clock_gating(struct drm_i915_private *dev_priv) ...@@ -7383,7 +7383,7 @@ static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
gen12lp_init_clock_gating(dev_priv); gen12lp_init_clock_gating(dev_priv);
/* Wa_1409836686:dg1[a0] */ /* Wa_1409836686:dg1[a0] */
if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0)) if (IS_DG1_GT_STEP(dev_priv, STEP_A0, STEP_A0))
intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) | intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
DPT_GATING_DIS); DPT_GATING_DIS);
} }
......
...@@ -81,6 +81,11 @@ static const struct intel_step_info rkl_revids[] = { ...@@ -81,6 +81,11 @@ static const struct intel_step_info rkl_revids[] = {
[4] = { COMMON_STEP(C0) }, [4] = { COMMON_STEP(C0) },
}; };
static const struct intel_step_info dg1_revids[] = {
[0] = { COMMON_STEP(A0) },
[1] = { COMMON_STEP(B0) },
};
static const struct intel_step_info adls_revids[] = { static const struct intel_step_info adls_revids[] = {
[0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 }, [0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
[0x1] = { .gt_step = STEP_A0, .display_step = STEP_A2 }, [0x1] = { .gt_step = STEP_A0, .display_step = STEP_A2 },
...@@ -109,6 +114,9 @@ void intel_step_init(struct drm_i915_private *i915) ...@@ -109,6 +114,9 @@ void intel_step_init(struct drm_i915_private *i915)
} else if (IS_ALDERLAKE_S(i915)) { } else if (IS_ALDERLAKE_S(i915)) {
revids = adls_revids; revids = adls_revids;
size = ARRAY_SIZE(adls_revids); size = ARRAY_SIZE(adls_revids);
} else if (IS_DG1(i915)) {
revids = dg1_revids;
size = ARRAY_SIZE(dg1_revids);
} else if (IS_ROCKETLAKE(i915)) { } else if (IS_ROCKETLAKE(i915)) {
revids = rkl_revids; revids = rkl_revids;
size = ARRAY_SIZE(rkl_revids); size = ARRAY_SIZE(rkl_revids);
......
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