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Commit dafc9543 authored by Boojin Kim's avatar Boojin Kim Committed by Vinod Koul
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ARM: S5PV210: Use generic DMA PL330 driver 

This patch makes Samsung S5PV210 to use DMA PL330 driver
on DMADEVICE. The S5PV210 uses DMA generic APIs instead of
SAMSUNG specific S3C-PL330 APIs.
Signed-off-by: default avatarBoojin Kim <boojin.kim@samsung.com>
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Acked-by: default avatarVinod Koul <vinod.koul@intel.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
parent bf856fbb
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Showing with 214 additions and 116 deletions
arch/arm/mach-s5pv210/Kconfig
View file @ dafc9543
...@@ -11,7 +11,7 @@ if ARCH_S5PV210 ...@@ -11,7 +11,7 @@ if ARCH_S5PV210
config CPU_S5PV210 config CPU_S5PV210
bool bool
select S3C_PL330_DMA select SAMSUNG_DMADEV
select S5P_EXT_INT select S5P_EXT_INT
select S5P_HRT select S5P_HRT
select S5PV210_PM if PM select S5PV210_PM if PM
......
arch/arm/mach-s5pv210/clock.c
View file @ dafc9543
...@@ -203,6 +203,11 @@ static struct clk clk_pcmcdclk2 = { ...@@ -203,6 +203,11 @@ static struct clk clk_pcmcdclk2 = {
.name = "pcmcdclk", .name = "pcmcdclk",
}; };
static struct clk dummy_apb_pclk = {
.name = "apb_pclk",
.id = -1,
};
static struct clk *clkset_vpllsrc_list[] = { static struct clk *clkset_vpllsrc_list[] = {
[0] = &clk_fin_vpll, [0] = &clk_fin_vpll,
[1] = &clk_sclk_hdmi27m, [1] = &clk_sclk_hdmi27m,
...@@ -289,13 +294,13 @@ static struct clk_ops clk_fout_apll_ops = { ...@@ -289,13 +294,13 @@ static struct clk_ops clk_fout_apll_ops = {
static struct clk init_clocks_off[] = { static struct clk init_clocks_off[] = {
{ {
.name = "pdma", .name = "dma",
.devname = "s3c-pl330.0", .devname = "s3c-pl330.0",
.parent = &clk_hclk_psys.clk, .parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip0_ctrl, .enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, { }, {
.name = "pdma", .name = "dma",
.devname = "s3c-pl330.1", .devname = "s3c-pl330.1",
.parent = &clk_hclk_psys.clk, .parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip0_ctrl, .enable = s5pv210_clk_ip0_ctrl,
...@@ -1161,5 +1166,6 @@ void __init s5pv210_register_clocks(void) ...@@ -1161,5 +1166,6 @@ void __init s5pv210_register_clocks(void)
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c24xx_register_clock(&dummy_apb_pclk);
s3c_pwmclk_init(); s3c_pwmclk_init();
} }
arch/arm/mach-s5pv210/dma.c
View file @ dafc9543
/* /* linux/arch/arm/mach-s5pv210/dma.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright (C) 2010 Samsung Electronics Co. Ltd. * Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com> * Jaswinder Singh <jassi.brar@samsung.com>
* *
...@@ -17,151 +21,239 @@ ...@@ -17,151 +21,239 @@
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#include <linux/platform_device.h>
#include <linux/dma-mapping.h> #include <linux/dma-mapping.h>
#include <linux/amba/bus.h>
#include <linux/amba/pl330.h>
#include <asm/irq.h>
#include <plat/devs.h> #include <plat/devs.h>
#include <plat/irqs.h> #include <plat/irqs.h>
#include <mach/map.h> #include <mach/map.h>
#include <mach/irqs.h> #include <mach/irqs.h>
#include <mach/dma.h>
#include <plat/s3c-pl330-pdata.h>
static u64 dma_dmamask = DMA_BIT_MASK(32); static u64 dma_dmamask = DMA_BIT_MASK(32);
static struct resource s5pv210_pdma0_resource[] = { struct dma_pl330_peri pdma0_peri[28] = {
[0] = { {
.start = S5PV210_PA_PDMA0, .peri_id = (u8)DMACH_UART0_RX,
.end = S5PV210_PA_PDMA0 + SZ_4K, .rqtype = DEVTOMEM,
.flags = IORESOURCE_MEM, }, {
}, .peri_id = (u8)DMACH_UART0_TX,
[1] = { .rqtype = MEMTODEV,
.start = IRQ_PDMA0, }, {
.end = IRQ_PDMA0, .peri_id = (u8)DMACH_UART1_RX,
.flags = IORESOURCE_IRQ, .rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_UART1_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = (u8)DMACH_UART2_RX,
.rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_UART2_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = (u8)DMACH_UART3_RX,
.rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_UART3_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = DMACH_MAX,
}, {
.peri_id = (u8)DMACH_I2S0_RX,
.rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_I2S0_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = (u8)DMACH_I2S0S_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = (u8)DMACH_I2S1_RX,
.rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_I2S1_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = (u8)DMACH_MAX,
}, {
.peri_id = (u8)DMACH_MAX,
}, {
.peri_id = (u8)DMACH_SPI0_RX,
.rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_SPI0_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = (u8)DMACH_SPI1_RX,
.rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_SPI1_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = (u8)DMACH_MAX,
}, {
.peri_id = (u8)DMACH_MAX,
}, {
.peri_id = (u8)DMACH_AC97_MICIN,
.rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_AC97_PCMIN,
.rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_AC97_PCMOUT,
.rqtype = MEMTODEV,
}, {
.peri_id = (u8)DMACH_MAX,
}, {
.peri_id = (u8)DMACH_PWM,
}, {
.peri_id = (u8)DMACH_SPDIF,
.rqtype = MEMTODEV,
}, },
}; };
static struct s3c_pl330_platdata s5pv210_pdma0_pdata = { struct dma_pl330_platdata s5pv210_pdma0_pdata = {
.peri = { .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
[0] = DMACH_UART0_RX, .peri = pdma0_peri,
[1] = DMACH_UART0_TX,
[2] = DMACH_UART1_RX,
[3] = DMACH_UART1_TX,
[4] = DMACH_UART2_RX,
[5] = DMACH_UART2_TX,
[6] = DMACH_UART3_RX,
[7] = DMACH_UART3_TX,
[8] = DMACH_MAX,
[9] = DMACH_I2S0_RX,
[10] = DMACH_I2S0_TX,
[11] = DMACH_I2S0S_TX,
[12] = DMACH_I2S1_RX,
[13] = DMACH_I2S1_TX,
[14] = DMACH_MAX,
[15] = DMACH_MAX,
[16] = DMACH_SPI0_RX,
[17] = DMACH_SPI0_TX,
[18] = DMACH_SPI1_RX,
[19] = DMACH_SPI1_TX,
[20] = DMACH_MAX,
[21] = DMACH_MAX,
[22] = DMACH_AC97_MICIN,
[23] = DMACH_AC97_PCMIN,
[24] = DMACH_AC97_PCMOUT,
[25] = DMACH_MAX,
[26] = DMACH_PWM,
[27] = DMACH_SPDIF,
[28] = DMACH_MAX,
[29] = DMACH_MAX,
[30] = DMACH_MAX,
[31] = DMACH_MAX,
},
}; };
static struct platform_device s5pv210_device_pdma0 = { struct amba_device s5pv210_device_pdma0 = {
.name = "s3c-pl330", .dev = {
.id = 0, .init_name = "dma-pl330.0",
.num_resources = ARRAY_SIZE(s5pv210_pdma0_resource),
.resource = s5pv210_pdma0_resource,
.dev = {
.dma_mask = &dma_dmamask, .dma_mask = &dma_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32), .coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &s5pv210_pdma0_pdata, .platform_data = &s5pv210_pdma0_pdata,
}, },
}; .res = {
.start = S5PV210_PA_PDMA0,
static struct resource s5pv210_pdma1_resource[] = { .end = S5PV210_PA_PDMA0 + SZ_4K,
[0] = {
.start = S5PV210_PA_PDMA1,
.end = S5PV210_PA_PDMA1 + SZ_4K,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { .irq = {IRQ_PDMA0, NO_IRQ},
.start = IRQ_PDMA1, .periphid = 0x00041330,
.end = IRQ_PDMA1,
.flags = IORESOURCE_IRQ,
},
}; };
static struct s3c_pl330_platdata s5pv210_pdma1_pdata = { struct dma_pl330_peri pdma1_peri[32] = {
.peri = { {
[0] = DMACH_UART0_RX, .peri_id = (u8)DMACH_UART0_RX,
[1] = DMACH_UART0_TX, .rqtype = DEVTOMEM,
[2] = DMACH_UART1_RX, }, {
[3] = DMACH_UART1_TX, .peri_id = (u8)DMACH_UART0_TX,
[4] = DMACH_UART2_RX, .rqtype = MEMTODEV,
[5] = DMACH_UART2_TX, }, {
[6] = DMACH_UART3_RX, .peri_id = (u8)DMACH_UART1_RX,
[7] = DMACH_UART3_TX, .rqtype = DEVTOMEM,
[8] = DMACH_MAX, }, {
[9] = DMACH_I2S0_RX, .peri_id = (u8)DMACH_UART1_TX,
[10] = DMACH_I2S0_TX, .rqtype = MEMTODEV,
[11] = DMACH_I2S0S_TX, }, {
[12] = DMACH_I2S1_RX, .peri_id = (u8)DMACH_UART2_RX,
[13] = DMACH_I2S1_TX, .rqtype = DEVTOMEM,
[14] = DMACH_I2S2_RX, }, {
[15] = DMACH_I2S2_TX, .peri_id = (u8)DMACH_UART2_TX,
[16] = DMACH_SPI0_RX, .rqtype = MEMTODEV,
[17] = DMACH_SPI0_TX, }, {
[18] = DMACH_SPI1_RX, .peri_id = (u8)DMACH_UART3_RX,
[19] = DMACH_SPI1_TX, .rqtype = DEVTOMEM,
[20] = DMACH_MAX, }, {
[21] = DMACH_MAX, .peri_id = (u8)DMACH_UART3_TX,
[22] = DMACH_PCM0_RX, .rqtype = MEMTODEV,
[23] = DMACH_PCM0_TX, }, {
[24] = DMACH_PCM1_RX, .peri_id = DMACH_MAX,
[25] = DMACH_PCM1_TX, }, {
[26] = DMACH_MSM_REQ0, .peri_id = (u8)DMACH_I2S0_RX,
[27] = DMACH_MSM_REQ1, .rqtype = DEVTOMEM,
[28] = DMACH_MSM_REQ2, }, {
[29] = DMACH_MSM_REQ3, .peri_id = (u8)DMACH_I2S0_TX,
[30] = DMACH_PCM2_RX, .rqtype = MEMTODEV,
[31] = DMACH_PCM2_TX, }, {
.peri_id = (u8)DMACH_I2S0S_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = (u8)DMACH_I2S1_RX,
.rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_I2S1_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = (u8)DMACH_I2S2_RX,
.rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_I2S2_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = (u8)DMACH_SPI0_RX,
.rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_SPI0_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = (u8)DMACH_SPI1_RX,
.rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_SPI1_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = (u8)DMACH_MAX,
}, {
.peri_id = (u8)DMACH_MAX,
}, {
.peri_id = (u8)DMACH_PCM0_RX,
.rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_PCM0_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = (u8)DMACH_PCM1_RX,
.rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_PCM1_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = (u8)DMACH_MSM_REQ0,
}, {
.peri_id = (u8)DMACH_MSM_REQ1,
}, {
.peri_id = (u8)DMACH_MSM_REQ2,
}, {
.peri_id = (u8)DMACH_MSM_REQ3,
}, {
.peri_id = (u8)DMACH_PCM2_RX,
.rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_PCM2_TX,
.rqtype = MEMTODEV,
}, },
}; };
static struct platform_device s5pv210_device_pdma1 = { struct dma_pl330_platdata s5pv210_pdma1_pdata = {
.name = "s3c-pl330", .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
.id = 1, .peri = pdma1_peri,
.num_resources = ARRAY_SIZE(s5pv210_pdma1_resource), };
.resource = s5pv210_pdma1_resource,
.dev = { struct amba_device s5pv210_device_pdma1 = {
.dev = {
.init_name = "dma-pl330.1",
.dma_mask = &dma_dmamask, .dma_mask = &dma_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32), .coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &s5pv210_pdma1_pdata, .platform_data = &s5pv210_pdma1_pdata,
}, },
}; .res = {
.start = S5PV210_PA_PDMA1,
static struct platform_device *s5pv210_dmacs[] __initdata = { .end = S5PV210_PA_PDMA1 + SZ_4K,
&s5pv210_device_pdma0, .flags = IORESOURCE_MEM,
&s5pv210_device_pdma1, },
.irq = {IRQ_PDMA1, NO_IRQ},
.periphid = 0x00041330,
}; };
static int __init s5pv210_dma_init(void) static int __init s5pv210_dma_init(void)
{ {
platform_add_devices(s5pv210_dmacs, ARRAY_SIZE(s5pv210_dmacs)); amba_device_register(&s5pv210_device_pdma0, &iomem_resource);
return 0; return 0;
} }
......
arch/arm/mach-s5pv210/include/mach/dma.h
View file @ dafc9543
...@@ -20,7 +20,7 @@ ...@@ -20,7 +20,7 @@
#ifndef __MACH_DMA_H #ifndef __MACH_DMA_H
#define __MACH_DMA_H #define __MACH_DMA_H
/* This platform uses the common S3C DMA API driver for PL330 */ /* This platform uses the common DMA API driver for PL330 */
#include <plat/dma-pl330.h> #include <plat/dma-pl330.h>
#endif /* __MACH_DMA_H */ #endif /* __MACH_DMA_H */
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