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Commit db1003a7 authored by Daniel J Blueman's avatar Daniel J Blueman Committed by Thomas Gleixner
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x86/numachip: Cleanup Numachip support 

Drop unused code and includes in Numachip header files and APIC driver.

Additionally, use the 'numachip1' prefix on Numachip1-specific functions;
this prepares for adding Numachip2 support in later patches.
Signed-off-by: default avatarDaniel J Blueman <daniel@numascale.com>
Acked-by: default avatarSteffen Persvold <sp@numascale.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: http://lkml.kernel.org/r/1442768522-19217-1-git-send-email-daniel@numascale.comSigned-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 1f93e4a9
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Showing with 44 additions and 178 deletions
arch/x86/include/asm/numachip/numachip_csr.h
View file @ db1003a7
......@@ -14,12 +14,7 @@
#ifndef _ASM_X86_NUMACHIP_NUMACHIP_CSR_H
#define _ASM_X86_NUMACHIP_NUMACHIP_CSR_H
#include <linux/numa.h>
#include <linux/percpu.h>
#include <linux/io.h>
#include <linux/swab.h>
#include <asm/types.h>
#include <asm/processor.h>
#define CSR_NODE_SHIFT 16
#define CSR_NODE_BITS(p) (((unsigned long)(p)) << CSR_NODE_SHIFT)
......@@ -27,11 +22,8 @@
/* 32K CSR space, b15 indicates geo/non-geo */
#define CSR_OFFSET_MASK 0x7fffUL
/* Global CSR space covers all 4K possible nodes with 64K CSR space per node */
#define NUMACHIP_GCSR_BASE 0x3fff00000000ULL
#define NUMACHIP_GCSR_LIM 0x3fff0fffffffULL
#define NUMACHIP_GCSR_SIZE (NUMACHIP_GCSR_LIM - NUMACHIP_GCSR_BASE + 1)
#define CSR_G0_NODE_IDS (0x008 + (0 << 12))
#define CSR_G3_EXT_IRQ_GEN (0x030 + (3 << 12))
/*
* Local CSR space starts in global CSR space with "nodeid" = 0xfff0, however
......@@ -42,28 +34,12 @@
#define NUMACHIP_LCSR_LIM 0x3fffffffffffULL
#define NUMACHIP_LCSR_SIZE (NUMACHIP_LCSR_LIM - NUMACHIP_LCSR_BASE + 1)
static inline void *gcsr_address(int node, unsigned long offset)
{
return __va(NUMACHIP_GCSR_BASE | (1UL << 15) |
CSR_NODE_BITS(node & CSR_NODE_MASK) | (offset & CSR_OFFSET_MASK));
}
static inline void *lcsr_address(unsigned long offset)
{
return __va(NUMACHIP_LCSR_BASE | (1UL << 15) |
CSR_NODE_BITS(0xfff0) | (offset & CSR_OFFSET_MASK));
}
static inline unsigned int read_gcsr(int node, unsigned long offset)
{
return swab32(readl(gcsr_address(node, offset)));
}
static inline void write_gcsr(int node, unsigned long offset, unsigned int val)
{
writel(swab32(val), gcsr_address(node, offset));
}
static inline unsigned int read_lcsr(unsigned long offset)
{
return swab32(readl(lcsr_address(offset)));
......@@ -74,94 +50,4 @@ static inline void write_lcsr(unsigned long offset, unsigned int val)
writel(swab32(val), lcsr_address(offset));
}
/* ========================================================================= */
/* CSR_G0_STATE_CLEAR */
/* ========================================================================= */
#define CSR_G0_STATE_CLEAR (0x000 + (0 << 12))
union numachip_csr_g0_state_clear {
unsigned int v;
struct numachip_csr_g0_state_clear_s {
unsigned int _state:2;
unsigned int _rsvd_2_6:5;
unsigned int _lost:1;
unsigned int _rsvd_8_31:24;
} s;
};
/* ========================================================================= */
/* CSR_G0_NODE_IDS */
/* ========================================================================= */
#define CSR_G0_NODE_IDS (0x008 + (0 << 12))
union numachip_csr_g0_node_ids {
unsigned int v;
struct numachip_csr_g0_node_ids_s {
unsigned int _initialid:16;
unsigned int _nodeid:12;
unsigned int _rsvd_28_31:4;
} s;
};
/* ========================================================================= */
/* CSR_G3_EXT_IRQ_GEN */
/* ========================================================================= */
#define CSR_G3_EXT_IRQ_GEN (0x030 + (3 << 12))
union numachip_csr_g3_ext_irq_gen {
unsigned int v;
struct numachip_csr_g3_ext_irq_gen_s {
unsigned int _vector:8;
unsigned int _msgtype:3;
unsigned int _index:5;
unsigned int _destination_apic_id:16;
} s;
};
/* ========================================================================= */
/* CSR_G3_EXT_IRQ_STATUS */
/* ========================================================================= */
#define CSR_G3_EXT_IRQ_STATUS (0x034 + (3 << 12))
union numachip_csr_g3_ext_irq_status {
unsigned int v;
struct numachip_csr_g3_ext_irq_status_s {
unsigned int _result:32;
} s;
};
/* ========================================================================= */
/* CSR_G3_EXT_IRQ_DEST */
/* ========================================================================= */
#define CSR_G3_EXT_IRQ_DEST (0x038 + (3 << 12))
union numachip_csr_g3_ext_irq_dest {
unsigned int v;
struct numachip_csr_g3_ext_irq_dest_s {
unsigned int _irq:8;
unsigned int _rsvd_8_31:24;
} s;
};
/* ========================================================================= */
/* CSR_G3_NC_ATT_MAP_SELECT */
/* ========================================================================= */
#define CSR_G3_NC_ATT_MAP_SELECT (0x7fc + (3 << 12))
union numachip_csr_g3_nc_att_map_select {
unsigned int v;
struct numachip_csr_g3_nc_att_map_select_s {
unsigned int _upper_address_bits:4;
unsigned int _select_ram:4;
unsigned int _rsvd_8_31:24;
} s;
};
/* ========================================================================= */
/* CSR_G3_NC_ATT_MAP_SELECT_0-255 */
/* ========================================================================= */
#define CSR_G3_NC_ATT_MAP_SELECT_0 (0x800 + (3 << 12))
#endif /* _ASM_X86_NUMACHIP_NUMACHIP_CSR_H */
arch/x86/kernel/apic/apic_numachip.c
View file @ db1003a7
......@@ -11,30 +11,20 @@
*
*/
#include <linux/errno.h>
#include <linux/threads.h>
#include <linux/cpumask.h>
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/ctype.h>
#include <linux/init.h>
#include <linux/hardirq.h>
#include <linux/delay.h>
#include <asm/numachip/numachip.h>
#include <asm/numachip/numachip_csr.h>
#include <asm/smp.h>
#include <asm/apic.h>
#include <asm/ipi.h>
#include <asm/apic_flat_64.h>
#include <asm/pgtable.h>
#include <asm/pci_x86.h>
static int numachip_system __read_mostly;
u8 numachip_system __read_mostly;
static const struct apic apic_numachip1;
static void (*numachip_apic_icr_write)(int apicid, unsigned int val) __read_mostly;
static const struct apic apic_numachip;
static unsigned int get_apic_id(unsigned long x)
static unsigned int numachip1_get_apic_id(unsigned long x)
{
unsigned long value;
unsigned int id = (x >> 24) & 0xff;
......@@ -47,7 +37,7 @@ static unsigned int get_apic_id(unsigned long x)
return id;
}
static unsigned long set_apic_id(unsigned int id)
static unsigned long numachip1_set_apic_id(unsigned int id)
{
unsigned long x;
......@@ -55,11 +45,6 @@ static unsigned long set_apic_id(unsigned int id)
return x;
}
static unsigned int read_xapic_id(void)
{
return get_apic_id(apic_read(APIC_ID));
}
static int numachip_apic_id_valid(int apicid)
{
/* Trust what bootloader passes in MADT */
......@@ -68,7 +53,7 @@ static int numachip_apic_id_valid(int apicid)
static int numachip_apic_id_registered(void)
{
return physid_isset(read_xapic_id(), phys_cpu_present_map);
return 1;
}
static int numachip_phys_pkg_id(int initial_apic_id, int index_msb)
......@@ -76,36 +61,27 @@ static int numachip_phys_pkg_id(int initial_apic_id, int index_msb)
return initial_apic_id >> index_msb;
}
static int numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip)
static void numachip1_apic_icr_write(int apicid, unsigned int val)
{
union numachip_csr_g3_ext_irq_gen int_gen;
int_gen.s._destination_apic_id = phys_apicid;
int_gen.s._vector = 0;
int_gen.s._msgtype = APIC_DM_INIT >> 8;
int_gen.s._index = 0;
write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);
int_gen.s._msgtype = APIC_DM_STARTUP >> 8;
int_gen.s._vector = start_rip >> 12;
write_lcsr(CSR_G3_EXT_IRQ_GEN, (apicid << 16) | val);
}
write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);
static int numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip)
{
numachip_apic_icr_write(phys_apicid, APIC_DM_INIT);
numachip_apic_icr_write(phys_apicid, APIC_DM_STARTUP |
(start_rip >> 12));
return 0;
}
static void numachip_send_IPI_one(int cpu, int vector)
{
union numachip_csr_g3_ext_irq_gen int_gen;
int apicid = per_cpu(x86_cpu_to_apicid, cpu);
unsigned int dmode;
int_gen.s._destination_apic_id = apicid;
int_gen.s._vector = vector;
int_gen.s._msgtype = (vector == NMI_VECTOR ? APIC_DM_NMI : APIC_DM_FIXED) >> 8;
int_gen.s._index = 0;
write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);
dmode = (vector == NMI_VECTOR) ? APIC_DM_NMI : APIC_DM_FIXED;
numachip_apic_icr_write(apicid, dmode | vector);
}
static void numachip_send_IPI_mask(const struct cpumask *mask, int vector)
......@@ -149,9 +125,9 @@ static void numachip_send_IPI_self(int vector)
apic_write(APIC_SELF_IPI, vector);
}
static int __init numachip_probe(void)
static int __init numachip1_probe(void)
{
return apic == &apic_numachip;
return apic == &apic_numachip1;
}
static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
......@@ -172,34 +148,38 @@ static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
static int __init numachip_system_init(void)
{
if (!numachip_system)
/* Map the LCSR area and set up the apic_icr_write function */
switch (numachip_system) {
case 1:
init_extra_mapping_uc(NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_SIZE);
numachip_apic_icr_write = numachip1_apic_icr_write;
x86_init.pci.arch_init = pci_numachip_init;
break;
default:
return 0;
init_extra_mapping_uc(NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_SIZE);
init_extra_mapping_uc(NUMACHIP_GCSR_BASE, NUMACHIP_GCSR_SIZE);
}
x86_cpuinit.fixup_cpu_id = fixup_cpu_id;
x86_init.pci.arch_init = pci_numachip_init;
return 0;
}
early_initcall(numachip_system_init);
static int numachip_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
static int numachip1_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
{
if (!strncmp(oem_id, "NUMASC", 6)) {
numachip_system = 1;
return 1;
}
if ((strncmp(oem_id, "NUMASC", 6) != 0) ||
(strncmp(oem_table_id, "NCONNECT", 8) != 0))
return 0;
return 0;
}
numachip_system = 1;
static const struct apic apic_numachip __refconst = {
return 1;
}
static const struct apic apic_numachip1 __refconst = {
.name = "NumaConnect system",
.probe = numachip_probe,
.acpi_madt_oem_check = numachip_acpi_madt_oem_check,
.probe = numachip1_probe,
.acpi_madt_oem_check = numachip1_acpi_madt_oem_check,
.apic_id_valid = numachip_apic_id_valid,
.apic_id_registered = numachip_apic_id_registered,
......@@ -221,8 +201,8 @@ static const struct apic apic_numachip __refconst = {
.check_phys_apicid_present = default_check_phys_apicid_present,
.phys_pkg_id = numachip_phys_pkg_id,
.get_apic_id = get_apic_id,
.set_apic_id = set_apic_id,
.get_apic_id = numachip1_get_apic_id,
.set_apic_id = numachip1_set_apic_id,
.apic_id_mask = 0xffU << 24,
.cpu_mask_to_apicid_and = default_cpu_mask_to_apicid_and,
......@@ -244,5 +224,5 @@ static const struct apic apic_numachip __refconst = {
.wait_icr_idle = native_apic_wait_icr_idle,
.safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
};
apic_driver(apic_numachip);
apic_driver(apic_numachip1);
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