Commit db90a441 authored by Sourav Poddar's avatar Sourav Poddar Committed by Mark Brown

spi: conditional checking of mode and transfer bits.

There is a bug in the following patch:
http://comments.gmane.org/gmane.linux.kernel.spi.devel/14420

spi: DUAL and QUAD support

    fix the previous patch some mistake below:
    1. DT in slave node, use "spi-tx-nbits = <1/2/4>" in place of using
       "spi-tx-dual, spi-tx-quad" directly, same to rx. So correct the
       previous way to get the property in @of_register_spi_devices().
    2. Change the value of transfer bit macro(SPI_NBITS_SINGLE, SPI_NBITS_DUAL
       SPI_NBITS_QUAD) to 0x01, 0x02 and 0x04 to match the actual wires.
    3. Add the following check
       (1)keep the tx_nbits and rx_nbits in spi_transfer is not beyond the
          single, dual and quad.
       (2)keep tx_nbits and rx_nbits are contained by @spi_device->mode
          example: if @spi_device->mode = DUAL, then tx/rx_nbits can not be set
                   to QUAD(SPI_NBITS_QUAD)
       (3)if "@spi_device->mode & SPI_3WIRE", then tx/rx_nbits should be in
          single(SPI_NBITS_SINGLE)

Checking of the tx/rx transfer bits and mode bits should be done conditionally
based on type of buffer filled else EINVAL condition will
always get hit either for rx or tx.
Signed-off-by: default avatarSourav Poddar <sourav.poddar@ti.com>
Signed-off-by: default avatarMark Brown <broonie@linaro.org>
parent f477b7fb
...@@ -1473,33 +1473,37 @@ static int __spi_async(struct spi_device *spi, struct spi_message *message) ...@@ -1473,33 +1473,37 @@ static int __spi_async(struct spi_device *spi, struct spi_message *message)
* 2. keep tx/rx_nbits is contained by mode in spi_device * 2. keep tx/rx_nbits is contained by mode in spi_device
* 3. if SPI_3WIRE, tx/rx_nbits should be in single * 3. if SPI_3WIRE, tx/rx_nbits should be in single
*/ */
if (xfer->tx_nbits != SPI_NBITS_SINGLE && if (xfer->tx_buf) {
xfer->tx_nbits != SPI_NBITS_DUAL && if (xfer->tx_nbits != SPI_NBITS_SINGLE &&
xfer->tx_nbits != SPI_NBITS_QUAD) xfer->tx_nbits != SPI_NBITS_DUAL &&
return -EINVAL; xfer->tx_nbits != SPI_NBITS_QUAD)
if ((xfer->tx_nbits == SPI_NBITS_DUAL) && return -EINVAL;
!(spi->mode & (SPI_TX_DUAL | SPI_TX_QUAD))) if ((xfer->tx_nbits == SPI_NBITS_DUAL) &&
return -EINVAL; !(spi->mode & (SPI_TX_DUAL | SPI_TX_QUAD)))
if ((xfer->tx_nbits == SPI_NBITS_QUAD) && return -EINVAL;
!(spi->mode & SPI_TX_QUAD)) if ((xfer->tx_nbits == SPI_NBITS_QUAD) &&
return -EINVAL; !(spi->mode & SPI_TX_QUAD))
if ((spi->mode & SPI_3WIRE) && return -EINVAL;
(xfer->tx_nbits != SPI_NBITS_SINGLE)) if ((spi->mode & SPI_3WIRE) &&
return -EINVAL; (xfer->tx_nbits != SPI_NBITS_SINGLE))
return -EINVAL;
}
/* check transfer rx_nbits */ /* check transfer rx_nbits */
if (xfer->rx_nbits != SPI_NBITS_SINGLE && if (xfer->rx_buf) {
xfer->rx_nbits != SPI_NBITS_DUAL && if (xfer->rx_nbits != SPI_NBITS_SINGLE &&
xfer->rx_nbits != SPI_NBITS_QUAD) xfer->rx_nbits != SPI_NBITS_DUAL &&
return -EINVAL; xfer->rx_nbits != SPI_NBITS_QUAD)
if ((xfer->rx_nbits == SPI_NBITS_DUAL) && return -EINVAL;
!(spi->mode & (SPI_RX_DUAL | SPI_RX_QUAD))) if ((xfer->rx_nbits == SPI_NBITS_DUAL) &&
return -EINVAL; !(spi->mode & (SPI_RX_DUAL | SPI_RX_QUAD)))
if ((xfer->rx_nbits == SPI_NBITS_QUAD) && return -EINVAL;
!(spi->mode & SPI_RX_QUAD)) if ((xfer->rx_nbits == SPI_NBITS_QUAD) &&
return -EINVAL; !(spi->mode & SPI_RX_QUAD))
if ((spi->mode & SPI_3WIRE) && return -EINVAL;
(xfer->rx_nbits != SPI_NBITS_SINGLE)) if ((spi->mode & SPI_3WIRE) &&
return -EINVAL; (xfer->rx_nbits != SPI_NBITS_SINGLE))
return -EINVAL;
}
} }
message->spi = spi; message->spi = spi;
......
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