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Commit dba4072a authored by Peter De Schrijver's avatar Peter De Schrijver Committed by Stephen Warren
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clk: tegra: Refactor PLL programming code 

Refactor the PLL programming code to make it useable by the new PLL types
introduced by Tegra114.

The following changes were done:

* Split programming the PLL into updating m,n,p and updating cpcon
* Move locking from _update_pll_cpcon() to clk_pll_set_rate()
* Introduce _get_pll_mnp() helper
* Move check for identical m,n,p values to clk_pll_set_rate()
* struct tegra_clk_pll_freq_table will always contain the values as defined
  by the hardware.
* Simplify the arguments to clk_pll_wait_for_lock()
* Split _tegra_clk_register_pll()
Signed-off-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: default avatarMike Turquette <mturquette@linaro.org>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent 6a676fa0
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Showing with 356 additions and 293 deletions
drivers/clk/tegra/clk-pll.c
View file @ dba4072a
This diff is collapsed.
drivers/clk/tegra/clk-tegra20.c
View file @ dba4072a
......@@ -248,125 +248,125 @@ static struct clk *clks[clk_max];
static struct clk_onecell_data clk_data;
static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
{ 12000000, 600000000, 600, 12, 1, 8 },
{ 13000000, 600000000, 600, 13, 1, 8 },
{ 19200000, 600000000, 500, 16, 1, 6 },
{ 26000000, 600000000, 600, 26, 1, 8 },
{ 12000000, 600000000, 600, 12, 0, 8 },
{ 13000000, 600000000, 600, 13, 0, 8 },
{ 19200000, 600000000, 500, 16, 0, 6 },
{ 26000000, 600000000, 600, 26, 0, 8 },
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
{ 12000000, 666000000, 666, 12, 1, 8},
{ 13000000, 666000000, 666, 13, 1, 8},
{ 19200000, 666000000, 555, 16, 1, 8},
{ 26000000, 666000000, 666, 26, 1, 8},
{ 12000000, 600000000, 600, 12, 1, 8},
{ 13000000, 600000000, 600, 13, 1, 8},
{ 19200000, 600000000, 375, 12, 1, 6},
{ 26000000, 600000000, 600, 26, 1, 8},
{ 12000000, 666000000, 666, 12, 0, 8},
{ 13000000, 666000000, 666, 13, 0, 8},
{ 19200000, 666000000, 555, 16, 0, 8},
{ 26000000, 666000000, 666, 26, 0, 8},
{ 12000000, 600000000, 600, 12, 0, 8},
{ 13000000, 600000000, 600, 13, 0, 8},
{ 19200000, 600000000, 375, 12, 0, 6},
{ 26000000, 600000000, 600, 26, 0, 8},
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
{ 12000000, 216000000, 432, 12, 2, 8},
{ 13000000, 216000000, 432, 13, 2, 8},
{ 19200000, 216000000, 90, 4, 2, 1},
{ 26000000, 216000000, 432, 26, 2, 8},
{ 12000000, 432000000, 432, 12, 1, 8},
{ 13000000, 432000000, 432, 13, 1, 8},
{ 19200000, 432000000, 90, 4, 1, 1},
{ 26000000, 432000000, 432, 26, 1, 8},
{ 12000000, 216000000, 432, 12, 1, 8},
{ 13000000, 216000000, 432, 13, 1, 8},
{ 19200000, 216000000, 90, 4, 1, 1},
{ 26000000, 216000000, 432, 26, 1, 8},
{ 12000000, 432000000, 432, 12, 0, 8},
{ 13000000, 432000000, 432, 13, 0, 8},
{ 19200000, 432000000, 90, 4, 0, 1},
{ 26000000, 432000000, 432, 26, 0, 8},
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
{ 28800000, 56448000, 49, 25, 1, 1},
{ 28800000, 73728000, 64, 25, 1, 1},
{ 28800000, 24000000, 5, 6, 1, 1},
{ 28800000, 56448000, 49, 25, 0, 1},
{ 28800000, 73728000, 64, 25, 0, 1},
{ 28800000, 24000000, 5, 6, 0, 1},
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
{ 12000000, 216000000, 216, 12, 1, 4},
{ 13000000, 216000000, 216, 13, 1, 4},
{ 19200000, 216000000, 135, 12, 1, 3},
{ 26000000, 216000000, 216, 26, 1, 4},
{ 12000000, 216000000, 216, 12, 0, 4},
{ 13000000, 216000000, 216, 13, 0, 4},
{ 19200000, 216000000, 135, 12, 0, 3},
{ 26000000, 216000000, 216, 26, 0, 4},
{ 12000000, 594000000, 594, 12, 1, 8},
{ 13000000, 594000000, 594, 13, 1, 8},
{ 19200000, 594000000, 495, 16, 1, 8},
{ 26000000, 594000000, 594, 26, 1, 8},
{ 12000000, 594000000, 594, 12, 0, 8},
{ 13000000, 594000000, 594, 13, 0, 8},
{ 19200000, 594000000, 495, 16, 0, 8},
{ 26000000, 594000000, 594, 26, 0, 8},
{ 12000000, 1000000000, 1000, 12, 1, 12},
{ 13000000, 1000000000, 1000, 13, 1, 12},
{ 19200000, 1000000000, 625, 12, 1, 8},
{ 26000000, 1000000000, 1000, 26, 1, 12},
{ 12000000, 1000000000, 1000, 12, 0, 12},
{ 13000000, 1000000000, 1000, 13, 0, 12},
{ 19200000, 1000000000, 625, 12, 0, 8},
{ 26000000, 1000000000, 1000, 26, 0, 12},
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
{ 12000000, 480000000, 960, 12, 2, 0},
{ 13000000, 480000000, 960, 13, 2, 0},
{ 19200000, 480000000, 200, 4, 2, 0},
{ 26000000, 480000000, 960, 26, 2, 0},
{ 12000000, 480000000, 960, 12, 0, 0},
{ 13000000, 480000000, 960, 13, 0, 0},
{ 19200000, 480000000, 200, 4, 0, 0},
{ 26000000, 480000000, 960, 26, 0, 0},
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
/* 1 GHz */
{ 12000000, 1000000000, 1000, 12, 1, 12},
{ 13000000, 1000000000, 1000, 13, 1, 12},
{ 19200000, 1000000000, 625, 12, 1, 8},
{ 26000000, 1000000000, 1000, 26, 1, 12},
{ 12000000, 1000000000, 1000, 12, 0, 12},
{ 13000000, 1000000000, 1000, 13, 0, 12},
{ 19200000, 1000000000, 625, 12, 0, 8},
{ 26000000, 1000000000, 1000, 26, 0, 12},
/* 912 MHz */
{ 12000000, 912000000, 912, 12, 1, 12},
{ 13000000, 912000000, 912, 13, 1, 12},
{ 19200000, 912000000, 760, 16, 1, 8},
{ 26000000, 912000000, 912, 26, 1, 12},
{ 12000000, 912000000, 912, 12, 0, 12},
{ 13000000, 912000000, 912, 13, 0, 12},
{ 19200000, 912000000, 760, 16, 0, 8},
{ 26000000, 912000000, 912, 26, 0, 12},
/* 816 MHz */
{ 12000000, 816000000, 816, 12, 1, 12},
{ 13000000, 816000000, 816, 13, 1, 12},
{ 19200000, 816000000, 680, 16, 1, 8},
{ 26000000, 816000000, 816, 26, 1, 12},
{ 12000000, 816000000, 816, 12, 0, 12},
{ 13000000, 816000000, 816, 13, 0, 12},
{ 19200000, 816000000, 680, 16, 0, 8},
{ 26000000, 816000000, 816, 26, 0, 12},
/* 760 MHz */
{ 12000000, 760000000, 760, 12, 1, 12},
{ 13000000, 760000000, 760, 13, 1, 12},
{ 19200000, 760000000, 950, 24, 1, 8},
{ 26000000, 760000000, 760, 26, 1, 12},
{ 12000000, 760000000, 760, 12, 0, 12},
{ 13000000, 760000000, 760, 13, 0, 12},
{ 19200000, 760000000, 950, 24, 0, 8},
{ 26000000, 760000000, 760, 26, 0, 12},
/* 750 MHz */
{ 12000000, 750000000, 750, 12, 1, 12},
{ 13000000, 750000000, 750, 13, 1, 12},
{ 19200000, 750000000, 625, 16, 1, 8},
{ 26000000, 750000000, 750, 26, 1, 12},
{ 12000000, 750000000, 750, 12, 0, 12},
{ 13000000, 750000000, 750, 13, 0, 12},
{ 19200000, 750000000, 625, 16, 0, 8},
{ 26000000, 750000000, 750, 26, 0, 12},
/* 608 MHz */
{ 12000000, 608000000, 608, 12, 1, 12},
{ 13000000, 608000000, 608, 13, 1, 12},
{ 19200000, 608000000, 380, 12, 1, 8},
{ 26000000, 608000000, 608, 26, 1, 12},
{ 12000000, 608000000, 608, 12, 0, 12},
{ 13000000, 608000000, 608, 13, 0, 12},
{ 19200000, 608000000, 380, 12, 0, 8},
{ 26000000, 608000000, 608, 26, 0, 12},
/* 456 MHz */
{ 12000000, 456000000, 456, 12, 1, 12},
{ 13000000, 456000000, 456, 13, 1, 12},
{ 19200000, 456000000, 380, 16, 1, 8},
{ 26000000, 456000000, 456, 26, 1, 12},
{ 12000000, 456000000, 456, 12, 0, 12},
{ 13000000, 456000000, 456, 13, 0, 12},
{ 19200000, 456000000, 380, 16, 0, 8},
{ 26000000, 456000000, 456, 26, 0, 12},
/* 312 MHz */
{ 12000000, 312000000, 312, 12, 1, 12},
{ 13000000, 312000000, 312, 13, 1, 12},
{ 19200000, 312000000, 260, 16, 1, 8},
{ 26000000, 312000000, 312, 26, 1, 12},
{ 12000000, 312000000, 312, 12, 0, 12},
{ 13000000, 312000000, 312, 13, 0, 12},
{ 19200000, 312000000, 260, 16, 0, 8},
{ 26000000, 312000000, 312, 26, 0, 12},
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
{ 12000000, 100000000, 200, 24, 1, 0 },
{ 12000000, 100000000, 200, 24, 0, 0 },
{ 0, 0, 0, 0, 0, 0 },
};
......
drivers/clk/tegra/clk-tegra30.c
View file @ dba4072a
This diff is collapsed.
drivers/clk/tegra/clk.h
View file @ dba4072a
......@@ -182,12 +182,14 @@ struct tegra_clk_pll_params {
* TEGRA_PLL_FIXED - We are not supposed to change output frequency
* of some plls.
* TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
* TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
* base register.
*/
struct tegra_clk_pll {
struct clk_hw hw;
void __iomem *clk_base;
void __iomem *pmc;
u8 flags;
u32 flags;
unsigned long fixed_rate;
spinlock_t *lock;
u8 divn_shift;
......@@ -210,18 +212,19 @@ struct tegra_clk_pll {
#define TEGRA_PLLM BIT(5)
#define TEGRA_PLL_FIXED BIT(6)
#define TEGRA_PLLE_CONFIGURE BIT(7)
#define TEGRA_PLL_LOCK_MISC BIT(8)
extern const struct clk_ops tegra_clk_pll_ops;
extern const struct clk_ops tegra_clk_plle_ops;
struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
void __iomem *clk_base, void __iomem *pmc,
unsigned long flags, unsigned long fixed_rate,
struct tegra_clk_pll_params *pll_params, u8 pll_flags,
struct tegra_clk_pll_params *pll_params, u32 pll_flags,
struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
void __iomem *clk_base, void __iomem *pmc,
unsigned long flags, unsigned long fixed_rate,
struct tegra_clk_pll_params *pll_params, u8 pll_flags,
struct tegra_clk_pll_params *pll_params, u32 pll_flags,
struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
/**
......
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