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Commit dba50728 authored by Ben Skeggs's avatar Ben Skeggs
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drm/nvc4/gr: update initial register/context values 

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 58ef2305
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Inline Side-by-side
Showing with 62 additions and 9 deletions
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
View file @ dba50728
......@@ -1327,6 +1327,7 @@ nvc0_grctx_generate_9097(struct nvc0_graph_priv *priv)
switch (nv_device(priv)->chipset) {
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
case 0xd9:
case 0xd7:
......@@ -1476,6 +1477,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
default:
break;
......@@ -1498,6 +1500,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv)
switch (nv_device(priv)->chipset) {
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
case 0xd9:
case 0xd7:
......@@ -1527,6 +1530,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
default:
nv_wr32(priv, 0x404174, 0x00000000);
......@@ -1671,6 +1675,7 @@ nvc0_grctx_generate_shaders(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
default:
nv_wr32(priv, 0x405800, 0x078000bf);
nv_wr32(priv, 0x405830, 0x02180000);
......@@ -1713,6 +1718,7 @@ nvc0_grctx_generate_unk64xx(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
default:
break;
......@@ -1726,6 +1732,7 @@ nvc0_grctx_generate_unk64xx(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
default:
break;
}
......@@ -1766,6 +1773,7 @@ nvc0_grctx_generate_rop(struct nvc0_graph_priv *priv)
switch (nv_device(priv)->chipset) {
case 0xc0:
case 0xc3:
case 0xc4:
nv_wr32(priv, 0x408808, 0x0003e00d);
nv_wr32(priv, 0x408900, 0x3080b801);
nv_wr32(priv, 0x408904, 0x02000001);
......@@ -1810,6 +1818,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
default:
nv_wr32(priv, 0x418408, 0x00000000);
......@@ -1824,6 +1833,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
default:
nv_wr32(priv, 0x418414, 0x00200fff);
......@@ -1850,6 +1860,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
default:
nv_wr32(priv, 0x41870c, 0x07c80000);
......@@ -1863,6 +1874,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
default:
nv_wr32(priv, 0x418800, 0x0006860a);
......@@ -1880,6 +1892,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
default:
nv_wr32(priv, 0x418830, 0x00000001);
break;
......@@ -1901,6 +1914,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
default:
nv_wr32(priv, 0x4188fc, 0x00100000);
break;
......@@ -1925,6 +1939,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
default:
nv_wr32(priv, 0x418b00, 0x00000000);
......@@ -1954,6 +1969,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
default:
break;
}
......@@ -1980,6 +1996,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
default:
nv_wr32(priv, 0x419864, 0x0000012a);
break;
......@@ -1995,6 +2012,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
case 0xc0:
break;
case 0xc3:
case 0xc4:
case 0xc1:
default:
nv_wr32(priv, 0x419a1c, 0x00000000);
......@@ -2010,6 +2028,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x00419ac4, 0x0017f440);
break;
case 0xc3:
case 0xc4:
case 0xc1:
default:
nv_wr32(priv, 0x00419ac4, 0x0007f440);
......@@ -2030,6 +2049,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
default:
nv_wr32(priv, 0x419be0, 0x00000001);
break;
......@@ -2042,6 +2062,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
default:
nv_wr32(priv, 0x419c00, 0x00000002);
......@@ -2052,6 +2073,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x419c20, 0x00000000);
switch (nv_device(priv)->chipset) {
case 0xc3:
case 0xc4:
case 0xc1:
case 0xce:
case 0xcf:
......@@ -2078,6 +2100,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
default:
nv_wr32(priv, 0x419d20, 0x02180000);
break;
......@@ -2091,6 +2114,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
default:
break;
}
......@@ -2128,6 +2152,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x419ee0, 0x00010110);
break;
case 0xc3:
case 0xc4:
case 0xc1:
default:
nv_wr32(priv, 0x419ee0, 0x00011110);
......@@ -2140,6 +2165,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x419f54, 0x00000000);
break;
case 0xc3:
case 0xc4:
case 0xc1:
case 0xd9:
case 0xd7:
......@@ -2478,6 +2504,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
default:
break;
......@@ -2498,6 +2525,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
break;
default:
......@@ -3073,6 +3101,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
default:
break;
}
......@@ -3183,6 +3212,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
default:
break;
......@@ -3332,6 +3362,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
switch (nv_device(priv)->chipset) {
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
nv_mthd(priv, 0x902d, 0x3410, 0x00000000);
break;
......
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
View file @ dba50728
......@@ -63,10 +63,10 @@ chipsets:
.b16 #nnvc3_tpc_mmio_head
.b16 #nnvc3_tpc_mmio_tail
.b8 0xc4 0 0 0
.b16 #nvc0_gpc_mmio_head
.b16 #nvc0_gpc_mmio_tail
.b16 #nvc0_tpc_mmio_head
.b16 #nvc3_tpc_mmio_tail
.b16 #nnvc0_gpc_mmio_head
.b16 #nnvc0_gpc_mmio_tail
.b16 #nnvc3_tpc_mmio_head
.b16 #nnvc3_tpc_mmio_tail
.b8 0xc8 0 0 0
.b16 #nvc0_gpc_mmio_head
.b16 #nvc0_gpc_mmio_tail
......
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
View file @ dba50728
......@@ -43,8 +43,8 @@ uint32_t nvc0_grgpc_data[] = {
0x01940134,
0x030402ac,
0x000000c4,
0x013400d4,
0x02600200,
0x01940134,
0x030402ac,
0x000000c8,
0x013400d4,
0x02500200,
......
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
View file @ dba50728
......@@ -57,8 +57,8 @@ chipsets:
.b16 #nnvc0_hub_mmio_head
.b16 #nnvc0_hub_mmio_tail
.b8 0xc4 0 0 0
.b16 #nvc0_hub_mmio_head
.b16 #nvc0_hub_mmio_tail
.b16 #nnvc0_hub_mmio_head
.b16 #nnvc0_hub_mmio_tail
.b8 0xc8 0 0 0
.b16 #nvc0_hub_mmio_head
.b16 #nvc0_hub_mmio_tail
......
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
View file @ dba50728
......@@ -209,7 +209,7 @@ uint32_t nvc0_grhub_data[] = {
0x000000c3,
0x048403e8,
0x000000c4,
0x03e8034c,
0x048403e8,
0x000000c8,
0x03e8034c,
0x000000ce,
......
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
View file @ dba50728
......@@ -754,6 +754,7 @@ nvc0_graph_init_unk64xx(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
default:
break;
......@@ -767,6 +768,7 @@ nvc0_graph_init_unk58xx(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x405850, 0x00000000);
switch (nv_device(priv)->chipset) {
case 0xc3:
case 0xc4:
case 0xc1:
case 0xd9:
case 0xd7:
......@@ -785,6 +787,7 @@ nvc0_graph_init_unk58xx(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
default:
break;
......@@ -807,6 +810,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
default:
break;
......@@ -820,6 +824,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
default:
break;
......@@ -834,6 +839,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
default:
nv_wr32(priv, 0x418714, 0x80000000);
break;
......@@ -851,6 +857,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
default:
nv_wr32(priv, 0x4188c8, 0x80000000);
break;
......@@ -874,6 +881,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
default:
break;
......@@ -887,6 +895,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
default:
break;
......@@ -901,6 +910,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
default:
break;
......@@ -917,6 +927,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
default:
nv_wr32(priv, 0x418e00, 0x00000050);
break;
......@@ -930,6 +941,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
default:
break;
......@@ -947,6 +959,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x419ab0, 0x00000000);
switch (nv_device(priv)->chipset) {
case 0xc3:
case 0xc4:
case 0xc1:
case 0xd9:
case 0xd7:
......@@ -967,6 +980,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
default:
nv_wr32(priv, 0x41980c, 0x00000000);
......@@ -981,6 +995,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
default:
nv_wr32(priv, 0x419814, 0x00000000);
break;
......@@ -993,6 +1008,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
default:
nv_wr32(priv, 0x41984c, 0x00005bc5);
......@@ -1004,6 +1020,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x41985c, 0x00000000);
switch (nv_device(priv)->chipset) {
case 0xc3:
case 0xc4:
case 0xc1:
case 0xd9:
case 0xd7:
......@@ -1030,6 +1047,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
default:
break;
......@@ -1043,6 +1061,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
default:
break;
......@@ -1058,6 +1077,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
default:
nv_wr32(priv, 0x419ea8, 0x00001100);
......@@ -1071,6 +1091,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x419ec0, 0x00000000);
switch (nv_device(priv)->chipset) {
case 0xc3:
case 0xc4:
case 0xc1:
case 0xd9:
case 0xd7:
......@@ -1355,6 +1376,7 @@ nvc0_graph_init(struct nouveau_object *object)
switch (nv_device(priv)->chipset) {
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc1:
case 0xd9:
case 0xd7:
......
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