Commit dbadbbe2 authored by Jacob Keller's avatar Jacob Keller Committed by Jeff Kirsher

i40e/i40evf: always set the CLEARPBA flag when re-enabling interrupts

In the past we changed driver behavior to not clear the PBA when
re-enabling interrupts. This change was motivated by the flawed belief
that clearing the PBA would cause a lost interrupt if a receive
interrupt occurred while interrupts were disabled.

According to empirical testing this isn't the case. Additionally, the
data sheet specifically says that we should set the CLEARPBA bit when
re-enabling interrupts in a polling setup.

This reverts commit 40d72a50 ("i40e/i40evf: don't lose interrupts")
Signed-off-by: default avatarJacob Keller <jacob.e.keller@intel.com>
Tested-by: default avatarAndrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 42702559
...@@ -949,9 +949,6 @@ static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector) ...@@ -949,9 +949,6 @@ static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
struct i40e_hw *hw = &pf->hw; struct i40e_hw *hw = &pf->hw;
u32 val; u32 val;
/* definitely clear the PBA here, as this function is meant to
* clean out all previous interrupts AND enable the interrupt
*/
val = I40E_PFINT_DYN_CTLN_INTENA_MASK | val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
(I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
...@@ -960,7 +957,7 @@ static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector) ...@@ -960,7 +957,7 @@ static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
} }
void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf); void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf, bool clearpba); void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf);
int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd); int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
int i40e_open(struct net_device *netdev); int i40e_open(struct net_device *netdev);
int i40e_close(struct net_device *netdev); int i40e_close(struct net_device *netdev);
......
...@@ -3403,15 +3403,14 @@ void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf) ...@@ -3403,15 +3403,14 @@ void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
/** /**
* i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
* @pf: board private structure * @pf: board private structure
* @clearpba: true when all pending interrupt events should be cleared
**/ **/
void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf, bool clearpba) void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
{ {
struct i40e_hw *hw = &pf->hw; struct i40e_hw *hw = &pf->hw;
u32 val; u32 val;
val = I40E_PFINT_DYN_CTL0_INTENA_MASK | val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
(clearpba ? I40E_PFINT_DYN_CTL0_CLEARPBA_MASK : 0) | I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
(I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT); (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
wr32(hw, I40E_PFINT_DYN_CTL0, val); wr32(hw, I40E_PFINT_DYN_CTL0, val);
...@@ -3597,7 +3596,7 @@ static int i40e_vsi_enable_irq(struct i40e_vsi *vsi) ...@@ -3597,7 +3596,7 @@ static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
for (i = 0; i < vsi->num_q_vectors; i++) for (i = 0; i < vsi->num_q_vectors; i++)
i40e_irq_dynamic_enable(vsi, i); i40e_irq_dynamic_enable(vsi, i);
} else { } else {
i40e_irq_dynamic_enable_icr0(pf, true); i40e_irq_dynamic_enable_icr0(pf);
} }
i40e_flush(&pf->hw); i40e_flush(&pf->hw);
...@@ -3746,7 +3745,7 @@ static irqreturn_t i40e_intr(int irq, void *data) ...@@ -3746,7 +3745,7 @@ static irqreturn_t i40e_intr(int irq, void *data)
wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask); wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
if (!test_bit(__I40E_DOWN, pf->state)) { if (!test_bit(__I40E_DOWN, pf->state)) {
i40e_service_event_schedule(pf); i40e_service_event_schedule(pf);
i40e_irq_dynamic_enable_icr0(pf, false); i40e_irq_dynamic_enable_icr0(pf);
} }
return ret; return ret;
...@@ -8455,7 +8454,7 @@ static int i40e_setup_misc_vector(struct i40e_pf *pf) ...@@ -8455,7 +8454,7 @@ static int i40e_setup_misc_vector(struct i40e_pf *pf)
i40e_flush(hw); i40e_flush(hw);
i40e_irq_dynamic_enable_icr0(pf, true); i40e_irq_dynamic_enable_icr0(pf);
return err; return err;
} }
......
...@@ -2202,9 +2202,7 @@ static u32 i40e_buildreg_itr(const int type, const u16 itr) ...@@ -2202,9 +2202,7 @@ static u32 i40e_buildreg_itr(const int type, const u16 itr)
u32 val; u32 val;
val = I40E_PFINT_DYN_CTLN_INTENA_MASK | val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
/* Don't clear PBA because that can cause lost interrupts that I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
* came in while we were cleaning/polling
*/
(type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) | (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
(itr << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT); (itr << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT);
...@@ -2241,7 +2239,7 @@ static inline void i40e_update_enable_itr(struct i40e_vsi *vsi, ...@@ -2241,7 +2239,7 @@ static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
/* If we don't have MSIX, then we only need to re-enable icr0 */ /* If we don't have MSIX, then we only need to re-enable icr0 */
if (!(vsi->back->flags & I40E_FLAG_MSIX_ENABLED)) { if (!(vsi->back->flags & I40E_FLAG_MSIX_ENABLED)) {
i40e_irq_dynamic_enable_icr0(vsi->back, false); i40e_irq_dynamic_enable_icr0(vsi->back);
return; return;
} }
......
...@@ -1358,7 +1358,7 @@ int i40e_alloc_vfs(struct i40e_pf *pf, u16 num_alloc_vfs) ...@@ -1358,7 +1358,7 @@ int i40e_alloc_vfs(struct i40e_pf *pf, u16 num_alloc_vfs)
i40e_free_vfs(pf); i40e_free_vfs(pf);
err_iov: err_iov:
/* Re-enable interrupt 0. */ /* Re-enable interrupt 0. */
i40e_irq_dynamic_enable_icr0(pf, false); i40e_irq_dynamic_enable_icr0(pf);
return ret; return ret;
} }
......
...@@ -1409,9 +1409,7 @@ static u32 i40e_buildreg_itr(const int type, const u16 itr) ...@@ -1409,9 +1409,7 @@ static u32 i40e_buildreg_itr(const int type, const u16 itr)
u32 val; u32 val;
val = I40E_VFINT_DYN_CTLN1_INTENA_MASK | val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
/* Don't clear PBA because that can cause lost interrupts that I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
* came in while we were cleaning/polling
*/
(type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) | (type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
(itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT); (itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
......
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