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Commit dbc0fd48 authored by Jakub Kicinski's avatar Jakub Kicinski
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Merge branch 'intel-wired-lan-driver-updates-for-2023-10-25-ice' 

Jacob Keller says:

====================
Intel Wired LAN Driver Updates for 2023-10-25 (ice)

This series extends the ice driver with basic support for the E830 device
line. It does not include support for all device features, but enables basic
functionality to load and pass traffic.

Alice adds the 200G speed and PHY types supported by E830 hardware.

Dan extends the DDP package logic to support the E830 package segment.

Paul adds the basic registers and macros used by E830 hardware, and adds
support for handling variable length link status information from firmware.

Pawel removes some redundant zeroing of the PCI IDs list, and extends the
list to include the E830 device IDs.
====================

Link: https://lore.kernel.org/r/20231025214157.1222758-1-jacob.e.keller@intel.comSigned-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents edd68156 ba20ecb1
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Showing with 650 additions and 171 deletions
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
View file @ dbc0fd48
......@@ -1099,7 +1099,15 @@ struct ice_aqc_get_phy_caps {
#define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
#define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
#define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
#define ICE_PHY_TYPE_HIGH_MAX_INDEX 4
#define ICE_PHY_TYPE_HIGH_200G_CR4_PAM4 BIT_ULL(5)
#define ICE_PHY_TYPE_HIGH_200G_SR4 BIT_ULL(6)
#define ICE_PHY_TYPE_HIGH_200G_FR4 BIT_ULL(7)
#define ICE_PHY_TYPE_HIGH_200G_LR4 BIT_ULL(8)
#define ICE_PHY_TYPE_HIGH_200G_DR4 BIT_ULL(9)
#define ICE_PHY_TYPE_HIGH_200G_KR4_PAM4 BIT_ULL(10)
#define ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC BIT_ULL(11)
#define ICE_PHY_TYPE_HIGH_200G_AUI4 BIT_ULL(12)
#define ICE_PHY_TYPE_HIGH_MAX_INDEX 12
struct ice_aqc_get_phy_caps_data {
__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
......@@ -1319,11 +1327,41 @@ struct ice_aqc_get_link_status_data {
#define ICE_AQ_LINK_SPEED_40GB BIT(8)
#define ICE_AQ_LINK_SPEED_50GB BIT(9)
#define ICE_AQ_LINK_SPEED_100GB BIT(10)
#define ICE_AQ_LINK_SPEED_200GB BIT(11)
#define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)
__le32 reserved3; /* Aligns next field to 8-byte boundary */
__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
__le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
};
/* Aligns next field to 8-byte boundary */
__le16 reserved3;
u8 ext_fec_status;
/* RS 272 FEC enabled */
#define ICE_AQ_LINK_RS_272_FEC_EN BIT(0)
u8 reserved4;
/* Use values from ICE_PHY_TYPE_LOW_* */
__le64 phy_type_low;
/* Use values from ICE_PHY_TYPE_HIGH_* */
__le64 phy_type_high;
#define ICE_AQC_LS_DATA_SIZE_V1 \
offsetofend(struct ice_aqc_get_link_status_data, phy_type_high)
/* Get link status v2 link partner data */
__le64 lp_phy_type_low;
__le64 lp_phy_type_high;
u8 lp_fec_adv;
#define ICE_AQ_LINK_LP_10G_KR_FEC_CAP BIT(0)
#define ICE_AQ_LINK_LP_25G_KR_FEC_CAP BIT(1)
#define ICE_AQ_LINK_LP_RS_528_FEC_CAP BIT(2)
#define ICE_AQ_LINK_LP_50G_KR_272_FEC_CAP BIT(3)
#define ICE_AQ_LINK_LP_100G_KR_272_FEC_CAP BIT(4)
#define ICE_AQ_LINK_LP_200G_KR_272_FEC_CAP BIT(5)
u8 lp_fec_req;
#define ICE_AQ_LINK_LP_10G_KR_FEC_REQ BIT(0)
#define ICE_AQ_LINK_LP_25G_KR_FEC_REQ BIT(1)
#define ICE_AQ_LINK_LP_RS_528_FEC_REQ BIT(2)
#define ICE_AQ_LINK_LP_KR_272_FEC_REQ BIT(3)
u8 lp_flowcontrol;
#define ICE_AQ_LINK_LP_PAUSE_ADV BIT(0)
#define ICE_AQ_LINK_LP_ASM_DIR_ADV BIT(1)
#define ICE_AQC_LS_DATA_SIZE_V2 \
offsetofend(struct ice_aqc_get_link_status_data, lp_flowcontrol)
} __packed;
/* Set event mask command (direct 0x0613) */
struct ice_aqc_set_event_mask {
......
drivers/net/ethernet/intel/ice/ice_common.c
View file @ dbc0fd48
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2018, Intel Corporation. */
/* Copyright (c) 2018-2023, Intel Corporation. */
#include "ice_common.h"
#include "ice_sched.h"
......@@ -154,6 +154,12 @@ static int ice_set_mac_type(struct ice_hw *hw)
case ICE_DEV_ID_E823L_SFP:
hw->mac_type = ICE_MAC_GENERIC;
break;
case ICE_DEV_ID_E830_BACKPLANE:
case ICE_DEV_ID_E830_QSFP56:
case ICE_DEV_ID_E830_SFP:
case ICE_DEV_ID_E830_SFP_DD:
hw->mac_type = ICE_MAC_E830;
break;
default:
hw->mac_type = ICE_MAC_UNKNOWN;
break;
......@@ -645,6 +651,24 @@ static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
return ICE_MEDIA_UNKNOWN;
}
/**
* ice_get_link_status_datalen
* @hw: pointer to the HW struct
*
* Returns datalength for the Get Link Status AQ command, which is bigger for
* newer adapter families handled by ice driver.
*/
static u16 ice_get_link_status_datalen(struct ice_hw *hw)
{
switch (hw->mac_type) {
case ICE_MAC_E830:
return ICE_AQC_LS_DATA_SIZE_V2;
case ICE_MAC_E810:
default:
return ICE_AQC_LS_DATA_SIZE_V1;
}
}
/**
* ice_aq_get_link_info
* @pi: port information structure
......@@ -683,8 +707,8 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
resp->cmd_flags = cpu_to_le16(cmd_flags);
resp->lport_num = pi->lport;
status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
status = ice_aq_send_cmd(hw, &desc, &link_data,
ice_get_link_status_datalen(hw), cd);
if (status)
return status;
......@@ -759,8 +783,7 @@ static void
ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
struct ice_aqc_set_mac_cfg *cmd)
{
u16 fc_thres_val, tx_timer_val;
u32 val;
u32 val, fc_thres_m;
/* We read back the transmit timer and FC threshold value of
* LFC. Thus, we will use index =
......@@ -769,19 +792,32 @@ ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
* Also, because we are operating on transmit timer and FC
* threshold of LFC, we don't turn on any bit in tx_tmr_priority
*/
#define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
/* Retrieve the transmit timer */
val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
tx_timer_val = val &
PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
cmd->tx_tmr_value = cpu_to_le16(tx_timer_val);
/* Retrieve the FC threshold */
val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M;
cmd->fc_refresh_threshold = cpu_to_le16(fc_thres_val);
#define E800_IDX_OF_LFC E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX
#define E800_REFRESH_TMR E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR
if (hw->mac_type == ICE_MAC_E830) {
/* Retrieve the transmit timer */
val = rd32(hw, E830_PRTMAC_CL01_PS_QNT);
cmd->tx_tmr_value =
le16_encode_bits(val, E830_PRTMAC_CL01_PS_QNT_CL0_M);
/* Retrieve the fc threshold */
val = rd32(hw, E830_PRTMAC_CL01_QNT_THR);
fc_thres_m = E830_PRTMAC_CL01_QNT_THR_CL0_M;
} else {
/* Retrieve the transmit timer */
val = rd32(hw,
E800_PRTMAC_HSEC_CTL_TX_PS_QNT(E800_IDX_OF_LFC));
cmd->tx_tmr_value =
le16_encode_bits(val,
E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M);
/* Retrieve the fc threshold */
val = rd32(hw,
E800_REFRESH_TMR(E800_IDX_OF_LFC));
fc_thres_m = E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M;
}
cmd->fc_refresh_threshold = le16_encode_bits(val, fc_thres_m);
}
/**
......@@ -2464,16 +2500,21 @@ ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
static void
ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p)
{
u32 reg_val, val;
u32 reg_val, gsize, bsize;
reg_val = rd32(hw, GLQF_FD_SIZE);
val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
GLQF_FD_SIZE_FD_GSIZE_S;
func_p->fd_fltr_guar =
ice_get_num_per_func(hw, val);
val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
GLQF_FD_SIZE_FD_BSIZE_S;
func_p->fd_fltr_best_effort = val;
switch (hw->mac_type) {
case ICE_MAC_E830:
gsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_GSIZE_M, reg_val);
bsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_BSIZE_M, reg_val);
break;
case ICE_MAC_E810:
default:
gsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_GSIZE_M, reg_val);
bsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_BSIZE_M, reg_val);
}
func_p->fd_fltr_guar = ice_get_num_per_func(hw, gsize);
func_p->fd_fltr_best_effort = bsize;
ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n",
func_p->fd_fltr_guar);
......@@ -6069,6 +6110,7 @@ static const u32 ice_aq_to_link_speed[] = {
SPEED_40000,
SPEED_50000,
SPEED_100000, /* BIT(10) */
SPEED_200000,
};
/**
......
drivers/net/ethernet/intel/ice/ice_ddp.c
View file @ dbc0fd48
This diff is collapsed.
drivers/net/ethernet/intel/ice/ice_ddp.h
View file @ dbc0fd48
......@@ -98,10 +98,21 @@ struct ice_pkg_hdr {
__le32 seg_offset[];
};
/* Package signing algorithm types */
#define SEGMENT_SIGN_TYPE_INVALID 0x00000000
#define SEGMENT_SIGN_TYPE_RSA2K 0x00000001
#define SEGMENT_SIGN_TYPE_RSA3K 0x00000002
#define SEGMENT_SIGN_TYPE_RSA3K_SBB 0x00000003 /* Secure Boot Block */
#define SEGMENT_SIGN_TYPE_RSA3K_E825 0x00000005
/* generic segment */
struct ice_generic_seg_hdr {
#define SEGMENT_TYPE_METADATA 0x00000001
#define SEGMENT_TYPE_ICE 0x00000010
#define SEGMENT_TYPE_INVALID 0x00000000
#define SEGMENT_TYPE_METADATA 0x00000001
#define SEGMENT_TYPE_ICE_E810 0x00000010
#define SEGMENT_TYPE_SIGNING 0x00001001
#define SEGMENT_TYPE_ICE_RUN_TIME_CFG 0x00000020
#define SEGMENT_TYPE_ICE_E830 0x00000017
__le32 seg_type;
struct ice_pkg_ver seg_format_ver;
__le32 seg_size;
......@@ -163,6 +174,18 @@ struct ice_global_metadata_seg {
#define ICE_MIN_S_SZ 1
#define ICE_MAX_S_SZ 4084
struct ice_sign_seg {
struct ice_generic_seg_hdr hdr;
__le32 seg_id;
__le32 sign_type;
__le32 signed_seg_idx;
__le32 signed_buf_start;
__le32 signed_buf_count;
#define ICE_SIGN_SEG_RESERVED_COUNT 44
u8 reserved[ICE_SIGN_SEG_RESERVED_COUNT];
struct ice_buf_table buf_tbl;
};
/* section information */
struct ice_section_entry {
__le32 type;
......
drivers/net/ethernet/intel/ice/ice_devids.h
View file @ dbc0fd48
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2018, Intel Corporation. */
/* Copyright (c) 2018-2023, Intel Corporation. */
#ifndef _ICE_DEVIDS_H_
#define _ICE_DEVIDS_H_
......@@ -16,6 +16,14 @@
#define ICE_DEV_ID_E823L_1GBE 0x124F
/* Intel(R) Ethernet Connection E823-L for QSFP */
#define ICE_DEV_ID_E823L_QSFP 0x151D
/* Intel(R) Ethernet Controller E830-C for backplane */
#define ICE_DEV_ID_E830_BACKPLANE 0x12D1
/* Intel(R) Ethernet Controller E830-C for QSFP */
#define ICE_DEV_ID_E830_QSFP56 0x12D2
/* Intel(R) Ethernet Controller E830-C for SFP */
#define ICE_DEV_ID_E830_SFP 0x12D3
/* Intel(R) Ethernet Controller E830-C for SFP-DD */
#define ICE_DEV_ID_E830_SFP_DD 0x12D4
/* Intel(R) Ethernet Controller E810-C for backplane */
#define ICE_DEV_ID_E810C_BACKPLANE 0x1591
/* Intel(R) Ethernet Controller E810-C for QSFP */
......
drivers/net/ethernet/intel/ice/ice_ethtool.c
View file @ dbc0fd48
......@@ -400,6 +400,14 @@ static const u32 ice_adv_lnk_speed_100000[] __initconst = {
ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
};
static const u32 ice_adv_lnk_speed_200000[] __initconst = {
ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT,
};
static struct ethtool_forced_speed_map ice_adv_lnk_speed_maps[] __ro_after_init = {
ETHTOOL_FORCED_SPEED_MAP(ice_adv_lnk_speed, 100),
ETHTOOL_FORCED_SPEED_MAP(ice_adv_lnk_speed, 1000),
......@@ -410,6 +418,7 @@ static struct ethtool_forced_speed_map ice_adv_lnk_speed_maps[] __ro_after_init
ETHTOOL_FORCED_SPEED_MAP(ice_adv_lnk_speed, 40000),
ETHTOOL_FORCED_SPEED_MAP(ice_adv_lnk_speed, 50000),
ETHTOOL_FORCED_SPEED_MAP(ice_adv_lnk_speed, 100000),
ETHTOOL_FORCED_SPEED_MAP(ice_adv_lnk_speed, 200000),
};
void __init ice_adv_lnk_speed_maps_init(void)
......@@ -1712,6 +1721,15 @@ ice_get_ethtool_stats(struct net_device *netdev,
ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC | \
ICE_PHY_TYPE_HIGH_100G_AUI2)
#define ICE_PHY_TYPE_HIGH_MASK_200G (ICE_PHY_TYPE_HIGH_200G_CR4_PAM4 | \
ICE_PHY_TYPE_HIGH_200G_SR4 | \
ICE_PHY_TYPE_HIGH_200G_FR4 | \
ICE_PHY_TYPE_HIGH_200G_LR4 | \
ICE_PHY_TYPE_HIGH_200G_DR4 | \
ICE_PHY_TYPE_HIGH_200G_KR4_PAM4 | \
ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC | \
ICE_PHY_TYPE_HIGH_200G_AUI4)
/**
* ice_mask_min_supported_speeds
* @hw: pointer to the HW structure
......@@ -1726,8 +1744,9 @@ ice_mask_min_supported_speeds(struct ice_hw *hw,
u64 phy_types_high, u64 *phy_types_low)
{
/* if QSFP connection with 100G speed, minimum supported speed is 25G */
if (*phy_types_low & ICE_PHY_TYPE_LOW_MASK_100G ||
phy_types_high & ICE_PHY_TYPE_HIGH_MASK_100G)
if ((*phy_types_low & ICE_PHY_TYPE_LOW_MASK_100G) ||
(phy_types_high & ICE_PHY_TYPE_HIGH_MASK_100G) ||
(phy_types_high & ICE_PHY_TYPE_HIGH_MASK_200G))
*phy_types_low &= ~ICE_PHY_TYPE_LOW_MASK_MIN_25G;
else if (!ice_is_100m_speed_supported(hw))
*phy_types_low &= ~ICE_PHY_TYPE_LOW_MASK_MIN_1G;
......@@ -1870,6 +1889,9 @@ ice_get_settings_link_up(struct ethtool_link_ksettings *ks,
ice_phy_type_to_ethtool(netdev, ks);
switch (link_info->link_speed) {
case ICE_AQ_LINK_SPEED_200GB:
ks->base.speed = SPEED_200000;
break;
case ICE_AQ_LINK_SPEED_100GB:
ks->base.speed = SPEED_100000;
break;
......
drivers/net/ethernet/intel/ice/ice_ethtool.h
View file @ dbc0fd48
......@@ -100,6 +100,14 @@ phy_type_high_lkup[] = {
[2] = ICE_PHY_TYPE(100GB, 100000baseCR2_Full),
[3] = ICE_PHY_TYPE(100GB, 100000baseSR2_Full),
[4] = ICE_PHY_TYPE(100GB, 100000baseCR2_Full),
[5] = ICE_PHY_TYPE(200GB, 200000baseCR4_Full),
[6] = ICE_PHY_TYPE(200GB, 200000baseSR4_Full),
[7] = ICE_PHY_TYPE(200GB, 200000baseLR4_ER4_FR4_Full),
[8] = ICE_PHY_TYPE(200GB, 200000baseLR4_ER4_FR4_Full),
[9] = ICE_PHY_TYPE(200GB, 200000baseDR4_Full),
[10] = ICE_PHY_TYPE(200GB, 200000baseKR4_Full),
[11] = ICE_PHY_TYPE(200GB, 200000baseSR4_Full),
[12] = ICE_PHY_TYPE(200GB, 200000baseCR4_Full),
};
#endif /* !_ICE_ETHTOOL_H_ */
drivers/net/ethernet/intel/ice/ice_ethtool_fdir.c
View file @ dbc0fd48
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2018-2020, Intel Corporation. */
/* Copyright (C) 2018-2023, Intel Corporation. */
/* flow director ethtool support for ice */
......@@ -540,16 +540,24 @@ static int ice_fdir_num_avail_fltr(struct ice_hw *hw, struct ice_vsi *vsi)
/* total guaranteed filters assigned to this VSI */
num_guar = vsi->num_gfltr;
/* minus the guaranteed filters programed by this VSI */
num_guar -= (rd32(hw, VSIQF_FD_CNT(vsi_num)) &
VSIQF_FD_CNT_FD_GCNT_M) >> VSIQF_FD_CNT_FD_GCNT_S;
/* total global best effort filters */
num_be = hw->func_caps.fd_fltr_best_effort;
/* minus the global best effort filters programmed */
num_be -= (rd32(hw, GLQF_FD_CNT) & GLQF_FD_CNT_FD_BCNT_M) >>
GLQF_FD_CNT_FD_BCNT_S;
/* Subtract the number of programmed filters from the global values */
switch (hw->mac_type) {
case ICE_MAC_E830:
num_guar -= FIELD_GET(E830_VSIQF_FD_CNT_FD_GCNT_M,
rd32(hw, VSIQF_FD_CNT(vsi_num)));
num_be -= FIELD_GET(E830_GLQF_FD_CNT_FD_BCNT_M,
rd32(hw, GLQF_FD_CNT));
break;
case ICE_MAC_E810:
default:
num_guar -= FIELD_GET(E800_VSIQF_FD_CNT_FD_GCNT_M,
rd32(hw, VSIQF_FD_CNT(vsi_num)));
num_be -= FIELD_GET(E800_GLQF_FD_CNT_FD_BCNT_M,
rd32(hw, GLQF_FD_CNT));
}
return num_guar + num_be;
}
......
drivers/net/ethernet/intel/ice/ice_hw_autogen.h
View file @ dbc0fd48
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2018, Intel Corporation. */
/* Copyright (c) 2018-2023, Intel Corporation. */
/* Machine-generated file */
......@@ -285,11 +285,11 @@
#define VPLAN_TX_QBASE_VFNUMQ_M ICE_M(0xFF, 16)
#define VPLAN_TXQ_MAPENA(_VF) (0x00073800 + ((_VF) * 4))
#define VPLAN_TXQ_MAPENA_TX_ENA_M BIT(0)
#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i) (0x001E36E0 + ((_i) * 32))
#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 8
#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M ICE_M(0xFFFF, 0)
#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3800 + ((_i) * 32))
#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M ICE_M(0xFFFF, 0)
#define E800_PRTMAC_HSEC_CTL_TX_PS_QNT(_i) (0x001E36E0 + ((_i) * 32))
#define E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX 8
#define E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M GENMASK(15, 0)
#define E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR(_i) (0x001E3800 + ((_i) * 32))
#define E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M GENMASK(15, 0)
#define GL_MDCK_TX_TDPU 0x00049348
#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1)
#define GL_MDET_RX 0x00294C00
......@@ -312,7 +312,11 @@
#define GL_MDET_TX_PQM_MAL_TYPE_S 26
#define GL_MDET_TX_PQM_MAL_TYPE_M ICE_M(0x1F, 26)
#define GL_MDET_TX_PQM_VALID_M BIT(31)
#define GL_MDET_TX_TCLAN 0x000FC068
#define GL_MDET_TX_TCLAN_BY_MAC(hw) \
((hw)->mac_type == ICE_MAC_E830 ? E830_GL_MDET_TX_TCLAN : \
E800_GL_MDET_TX_TCLAN)
#define E800_GL_MDET_TX_TCLAN 0x000FC068
#define E830_GL_MDET_TX_TCLAN 0x000FCCC0
#define GL_MDET_TX_TCLAN_QNUM_S 0
#define GL_MDET_TX_TCLAN_QNUM_M ICE_M(0x7FFF, 0)
#define GL_MDET_TX_TCLAN_VF_NUM_S 15
......@@ -326,7 +330,11 @@
#define PF_MDET_RX_VALID_M BIT(0)
#define PF_MDET_TX_PQM 0x002D2C80
#define PF_MDET_TX_PQM_VALID_M BIT(0)
#define PF_MDET_TX_TCLAN 0x000FC000
#define PF_MDET_TX_TCLAN_BY_MAC(hw) \
((hw)->mac_type == ICE_MAC_E830 ? E830_PF_MDET_TX_TCLAN : \
E800_PF_MDET_TX_TCLAN)
#define E800_PF_MDET_TX_TCLAN 0x000FC000
#define E830_PF_MDET_TX_TCLAN 0x000FCC00
#define PF_MDET_TX_TCLAN_VALID_M BIT(0)
#define VP_MDET_RX(_VF) (0x00294400 + ((_VF) * 4))
#define VP_MDET_RX_VALID_M BIT(0)
......@@ -336,6 +344,8 @@
#define VP_MDET_TX_TCLAN_VALID_M BIT(0)
#define VP_MDET_TX_TDPU(_VF) (0x00040000 + ((_VF) * 4))
#define VP_MDET_TX_TDPU_VALID_M BIT(0)
#define E800_GL_MNG_FWSM_FW_MODES_M GENMASK(2, 0)
#define E830_GL_MNG_FWSM_FW_MODES_M GENMASK(1, 0)
#define GL_MNG_FWSM 0x000B6134
#define GL_MNG_FWSM_FW_LOADING_M BIT(30)
#define GLNVM_FLA 0x000B6108
......@@ -364,13 +374,18 @@
#define GL_PWR_MODE_CTL_CAR_MAX_BW_S 30
#define GL_PWR_MODE_CTL_CAR_MAX_BW_M ICE_M(0x3, 30)
#define GLQF_FD_CNT 0x00460018
#define E800_GLQF_FD_CNT_FD_GCNT_M GENMASK(14, 0)
#define E830_GLQF_FD_CNT_FD_GCNT_M GENMASK(15, 0)
#define GLQF_FD_CNT_FD_BCNT_S 16
#define GLQF_FD_CNT_FD_BCNT_M ICE_M(0x7FFF, 16)
#define E800_GLQF_FD_CNT_FD_BCNT_M GENMASK(30, 16)
#define E830_GLQF_FD_CNT_FD_BCNT_M GENMASK(31, 16)
#define GLQF_FD_SIZE 0x00460010
#define GLQF_FD_SIZE_FD_GSIZE_S 0
#define GLQF_FD_SIZE_FD_GSIZE_M ICE_M(0x7FFF, 0)
#define E800_GLQF_FD_SIZE_FD_GSIZE_M GENMASK(14, 0)
#define E830_GLQF_FD_SIZE_FD_GSIZE_M GENMASK(15, 0)
#define GLQF_FD_SIZE_FD_BSIZE_S 16
#define GLQF_FD_SIZE_FD_BSIZE_M ICE_M(0x7FFF, 16)
#define E800_GLQF_FD_SIZE_FD_BSIZE_M GENMASK(30, 16)
#define E830_GLQF_FD_SIZE_FD_BSIZE_M GENMASK(31, 16)
#define GLQF_FDINSET(_i, _j) (0x00412000 + ((_i) * 4 + (_j) * 512))
#define GLQF_FDMASK(_i) (0x00410800 + ((_i) * 4))
#define GLQF_FDMASK_MAX_INDEX 31
......@@ -389,6 +404,10 @@
#define GLQF_HMASK_SEL(_i) (0x00410000 + ((_i) * 4))
#define GLQF_HMASK_SEL_MAX_INDEX 127
#define GLQF_HMASK_SEL_MASK_SEL_S 0
#define E800_PFQF_FD_CNT_FD_GCNT_M GENMASK(14, 0)
#define E830_PFQF_FD_CNT_FD_GCNT_M GENMASK(15, 0)
#define E800_PFQF_FD_CNT_FD_BCNT_M GENMASK(30, 16)
#define E830_PFQF_FD_CNT_FD_BCNT_M GENMASK(31, 16)
#define PFQF_FD_ENA 0x0043A000
#define PFQF_FD_ENA_FD_ENA_M BIT(0)
#define PFQF_FD_SIZE 0x00460100
......@@ -479,6 +498,7 @@
#define GLTSYN_SYNC_DLAY 0x00088818
#define GLTSYN_TGT_H_0(_i) (0x00088930 + ((_i) * 4))
#define GLTSYN_TGT_L_0(_i) (0x00088928 + ((_i) * 4))
#define GLTSYN_TIME_0(_i) (0x000888C8 + ((_i) * 4))
#define GLTSYN_TIME_H(_i) (0x000888D8 + ((_i) * 4))
#define GLTSYN_TIME_L(_i) (0x000888D0 + ((_i) * 4))
#define PFHH_SEM 0x000A4200 /* Reset Source: PFR */
......@@ -487,9 +507,11 @@
#define PFTSYN_SEM_BUSY_M BIT(0)
#define VSIQF_FD_CNT(_VSI) (0x00464000 + ((_VSI) * 4))
#define VSIQF_FD_CNT_FD_GCNT_S 0
#define VSIQF_FD_CNT_FD_GCNT_M ICE_M(0x3FFF, 0)
#define E800_VSIQF_FD_CNT_FD_GCNT_M GENMASK(13, 0)
#define E830_VSIQF_FD_CNT_FD_GCNT_M GENMASK(15, 0)
#define VSIQF_FD_CNT_FD_BCNT_S 16
#define VSIQF_FD_CNT_FD_BCNT_M ICE_M(0x3FFF, 16)
#define E800_VSIQF_FD_CNT_FD_BCNT_M GENMASK(29, 16)
#define E830_VSIQF_FD_CNT_FD_BCNT_M GENMASK(31, 16)
#define VSIQF_FD_SIZE(_VSI) (0x00462000 + ((_VSI) * 4))
#define VSIQF_HKEY_MAX_INDEX 12
#define PFPM_APM 0x000B8080
......@@ -501,6 +523,10 @@
#define PFPM_WUS_MAG_M BIT(1)
#define PFPM_WUS_MNG_M BIT(3)
#define PFPM_WUS_FW_RST_WK_M BIT(31)
#define E830_PRTMAC_CL01_PS_QNT 0x001E32A0
#define E830_PRTMAC_CL01_PS_QNT_CL0_M GENMASK(15, 0)
#define E830_PRTMAC_CL01_QNT_THR 0x001E3320
#define E830_PRTMAC_CL01_QNT_THR_CL0_M GENMASK(15, 0)
#define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4))
#define VFINT_DYN_CTLN_CLEARPBA_M BIT(1)
......
drivers/net/ethernet/intel/ice/ice_main.c
View file @ dbc0fd48
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2018, Intel Corporation. */
/* Copyright (c) 2018-2023, Intel Corporation. */
/* Intel(R) Ethernet Connection E800 Series Linux Driver */
......@@ -1759,7 +1759,7 @@ static void ice_handle_mdd_event(struct ice_pf *pf)
wr32(hw, GL_MDET_TX_PQM, 0xffffffff);
}
reg = rd32(hw, GL_MDET_TX_TCLAN);
reg = rd32(hw, GL_MDET_TX_TCLAN_BY_MAC(hw));
if (reg & GL_MDET_TX_TCLAN_VALID_M) {
u8 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
GL_MDET_TX_TCLAN_PF_NUM_S;
......@@ -1773,7 +1773,7 @@ static void ice_handle_mdd_event(struct ice_pf *pf)
if (netif_msg_tx_err(pf))
dev_info(dev, "Malicious Driver Detection event %d on TX queue %d PF# %d VF# %d\n",
event, queue, pf_num, vf_num);
wr32(hw, GL_MDET_TX_TCLAN, 0xffffffff);
wr32(hw, GL_MDET_TX_TCLAN_BY_MAC(hw), U32_MAX);
}
reg = rd32(hw, GL_MDET_RX);
......@@ -1801,9 +1801,9 @@ static void ice_handle_mdd_event(struct ice_pf *pf)
dev_info(dev, "Malicious Driver Detection event TX_PQM detected on PF\n");
}
reg = rd32(hw, PF_MDET_TX_TCLAN);
reg = rd32(hw, PF_MDET_TX_TCLAN_BY_MAC(hw));
if (reg & PF_MDET_TX_TCLAN_VALID_M) {
wr32(hw, PF_MDET_TX_TCLAN, 0xFFFF);
wr32(hw, PF_MDET_TX_TCLAN_BY_MAC(hw), 0xffff);
if (netif_msg_tx_err(pf))
dev_info(dev, "Malicious Driver Detection event TX_TCLAN detected on PF\n");
}
......@@ -3871,7 +3871,8 @@ static void ice_set_pf_caps(struct ice_pf *pf)
}
clear_bit(ICE_FLAG_PTP_SUPPORTED, pf->flags);
if (func_caps->common_cap.ieee_1588)
if (func_caps->common_cap.ieee_1588 &&
!(pf->hw.mac_type == ICE_MAC_E830))
set_bit(ICE_FLAG_PTP_SUPPORTED, pf->flags);
pf->max_pf_txqs = func_caps->common_cap.num_txq;
......@@ -5584,34 +5585,38 @@ static void ice_pci_err_reset_done(struct pci_dev *pdev)
* Class, Class Mask, private data (not used) }
*/
static const struct pci_device_id ice_pci_tbl[] = {
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E810C_BACKPLANE), 0 },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E810C_QSFP), 0 },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E810C_SFP), 0 },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E810_XXV_BACKPLANE), 0 },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E810_XXV_QSFP), 0 },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E810_XXV_SFP), 0 },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E823C_BACKPLANE), 0 },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E823C_QSFP), 0 },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E823C_SFP), 0 },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E823C_10G_BASE_T), 0 },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E823C_SGMII), 0 },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E822C_BACKPLANE), 0 },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E822C_QSFP), 0 },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E822C_SFP), 0 },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E822C_10G_BASE_T), 0 },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E822C_SGMII), 0 },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E822L_BACKPLANE), 0 },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E822L_SFP), 0 },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E822L_10G_BASE_T), 0 },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E822L_SGMII), 0 },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E823L_BACKPLANE), 0 },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E823L_SFP), 0 },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E823L_10G_BASE_T), 0 },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E823L_1GBE), 0 },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E823L_QSFP), 0 },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E822_SI_DFLT), 0 },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E810C_BACKPLANE) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E810C_QSFP) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E810C_SFP) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E810_XXV_BACKPLANE) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E810_XXV_QSFP) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E810_XXV_SFP) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E823C_BACKPLANE) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E823C_QSFP) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E823C_SFP) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E823C_10G_BASE_T) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E823C_SGMII) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E822C_BACKPLANE) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E822C_QSFP) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E822C_SFP) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E822C_10G_BASE_T) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E822C_SGMII) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E822L_BACKPLANE) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E822L_SFP) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E822L_10G_BASE_T) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E822L_SGMII) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E823L_BACKPLANE) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E823L_SFP) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E823L_10G_BASE_T) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E823L_1GBE) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E823L_QSFP) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E822_SI_DFLT) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E830_BACKPLANE) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E830_QSFP56) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E830_SFP) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E830_SFP_DD) },
/* required last entry */
{ 0, }
{}
};
MODULE_DEVICE_TABLE(pci, ice_pci_tbl);
......
drivers/net/ethernet/intel/ice/ice_type.h
View file @ dbc0fd48
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2018, Intel Corporation. */
/* Copyright (c) 2018-2023, Intel Corporation. */
#ifndef _ICE_TYPE_H_
#define _ICE_TYPE_H_
......@@ -129,6 +129,7 @@ enum ice_set_fc_aq_failures {
enum ice_mac_type {
ICE_MAC_UNKNOWN = 0,
ICE_MAC_E810,
ICE_MAC_E830,
ICE_MAC_GENERIC,
};
......@@ -919,7 +920,10 @@ struct ice_hw {
/* Active package version (currently active) */
struct ice_pkg_ver active_pkg_ver;
u32 pkg_seg_id;
u32 pkg_sign_type;
u32 active_track_id;
u8 pkg_has_signing_seg:1;
u8 active_pkg_name[ICE_PKG_NAME_SIZE];
u8 active_pkg_in_nvm;
......
drivers/net/ethernet/intel/ice/ice_virtchnl_fdir.c
View file @ dbc0fd48
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2021, Intel Corporation. */
/* Copyright (C) 2021-2023, Intel Corporation. */
#include "ice.h"
#include "ice_base.h"
......@@ -1422,8 +1422,8 @@ ice_vc_fdir_irq_handler(struct ice_vsi *ctrl_vsi,
*/
static void ice_vf_fdir_dump_info(struct ice_vf *vf)
{
u32 fd_size, fd_cnt, fd_size_g, fd_cnt_g, fd_size_b, fd_cnt_b;
struct ice_vsi *vf_vsi;
u32 fd_size, fd_cnt;
struct device *dev;
struct ice_pf *pf;
struct ice_hw *hw;
......@@ -1442,12 +1442,25 @@ static void ice_vf_fdir_dump_info(struct ice_vf *vf)
fd_size = rd32(hw, VSIQF_FD_SIZE(vsi_num));
fd_cnt = rd32(hw, VSIQF_FD_CNT(vsi_num));
dev_dbg(dev, "VF %d: space allocated: guar:0x%x, be:0x%x, space consumed: guar:0x%x, be:0x%x\n",
vf->vf_id,
(fd_size & VSIQF_FD_CNT_FD_GCNT_M) >> VSIQF_FD_CNT_FD_GCNT_S,
(fd_size & VSIQF_FD_CNT_FD_BCNT_M) >> VSIQF_FD_CNT_FD_BCNT_S,
(fd_cnt & VSIQF_FD_CNT_FD_GCNT_M) >> VSIQF_FD_CNT_FD_GCNT_S,
(fd_cnt & VSIQF_FD_CNT_FD_BCNT_M) >> VSIQF_FD_CNT_FD_BCNT_S);
switch (hw->mac_type) {
case ICE_MAC_E830:
fd_size_g = FIELD_GET(E830_VSIQF_FD_CNT_FD_GCNT_M, fd_size);
fd_size_b = FIELD_GET(E830_VSIQF_FD_CNT_FD_BCNT_M, fd_size);
fd_cnt_g = FIELD_GET(E830_VSIQF_FD_CNT_FD_GCNT_M, fd_cnt);
fd_cnt_b = FIELD_GET(E830_VSIQF_FD_CNT_FD_BCNT_M, fd_cnt);
break;
case ICE_MAC_E810:
default:
fd_size_g = FIELD_GET(E800_VSIQF_FD_CNT_FD_GCNT_M, fd_size);
fd_size_b = FIELD_GET(E800_VSIQF_FD_CNT_FD_BCNT_M, fd_size);
fd_cnt_g = FIELD_GET(E800_VSIQF_FD_CNT_FD_GCNT_M, fd_cnt);
fd_cnt_b = FIELD_GET(E800_VSIQF_FD_CNT_FD_BCNT_M, fd_cnt);
}
dev_dbg(dev, "VF %d: Size in the FD table: guaranteed:0x%x, best effort:0x%x\n",
vf->vf_id, fd_size_g, fd_size_b);
dev_dbg(dev, "VF %d: Filter counter in the FD table: guaranteed:0x%x, best effort:0x%x\n",
vf->vf_id, fd_cnt_g, fd_cnt_b);
}
/**
......
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