Commit dbea3cea authored by Imre Deak's avatar Imre Deak Committed by Jani Nikula

drm/i915: sanitize RPS resetting during GPU reset

Atm, we don't disable RPS interrupts and related work items before
resetting the GPU. This may interfere with the following GPU
initialization and cause RPS interrupts to show up in PM_IIR too early
before calling gen6_enable_rps_interrupts() (triggering a WARN there).

Solve this by disabling RPS interrupts and flushing any related work
items before resetting the GPU.

v2:
- split out the common parts of the gt suspend and the new gt reset
  functions (Paulo)
v3:
- remove the check for UMS, it's a NOP nowadays (Daniel)
Reported-by: default avatarHe, Shuang <shuang.he@intel.com>
Testcase: igt/gem_reset_stats/ban-render
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86644Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 78e68d36
...@@ -811,6 +811,8 @@ int i915_reset(struct drm_device *dev) ...@@ -811,6 +811,8 @@ int i915_reset(struct drm_device *dev)
if (!i915.reset) if (!i915.reset)
return 0; return 0;
intel_reset_gt_powersave(dev);
mutex_lock(&dev->struct_mutex); mutex_lock(&dev->struct_mutex);
i915_gem_reset(dev); i915_gem_reset(dev);
...@@ -880,7 +882,7 @@ int i915_reset(struct drm_device *dev) ...@@ -880,7 +882,7 @@ int i915_reset(struct drm_device *dev)
* of re-init after reset. * of re-init after reset.
*/ */
if (INTEL_INFO(dev)->gen > 5) if (INTEL_INFO(dev)->gen > 5)
intel_reset_gt_powersave(dev); intel_enable_gt_powersave(dev);
} else { } else {
mutex_unlock(&dev->struct_mutex); mutex_unlock(&dev->struct_mutex);
} }
......
...@@ -6191,6 +6191,20 @@ void intel_cleanup_gt_powersave(struct drm_device *dev) ...@@ -6191,6 +6191,20 @@ void intel_cleanup_gt_powersave(struct drm_device *dev)
valleyview_cleanup_gt_powersave(dev); valleyview_cleanup_gt_powersave(dev);
} }
static void gen6_suspend_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
flush_delayed_work(&dev_priv->rps.delayed_resume_work);
/*
* TODO: disable RPS interrupts on GEN9+ too once RPS support
* is added for it.
*/
if (INTEL_INFO(dev)->gen < 9)
gen6_disable_rps_interrupts(dev);
}
/** /**
* intel_suspend_gt_powersave - suspend PM work and helper threads * intel_suspend_gt_powersave - suspend PM work and helper threads
* @dev: drm device * @dev: drm device
...@@ -6206,14 +6220,7 @@ void intel_suspend_gt_powersave(struct drm_device *dev) ...@@ -6206,14 +6220,7 @@ void intel_suspend_gt_powersave(struct drm_device *dev)
if (INTEL_INFO(dev)->gen < 6) if (INTEL_INFO(dev)->gen < 6)
return; return;
flush_delayed_work(&dev_priv->rps.delayed_resume_work); gen6_suspend_rps(dev);
/*
* TODO: disable RPS interrupts on GEN9+ too once RPS support
* is added for it.
*/
if (INTEL_INFO(dev)->gen < 9)
gen6_disable_rps_interrupts(dev);
/* Force GPU to min freq during suspend */ /* Force GPU to min freq during suspend */
gen6_rps_idle(dev_priv); gen6_rps_idle(dev_priv);
...@@ -6316,8 +6323,11 @@ void intel_reset_gt_powersave(struct drm_device *dev) ...@@ -6316,8 +6323,11 @@ void intel_reset_gt_powersave(struct drm_device *dev)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
if (INTEL_INFO(dev)->gen < 6)
return;
gen6_suspend_rps(dev);
dev_priv->rps.enabled = false; dev_priv->rps.enabled = false;
intel_enable_gt_powersave(dev);
} }
static void ibx_init_clock_gating(struct drm_device *dev) static void ibx_init_clock_gating(struct drm_device *dev)
......
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