drm/amd/display: Update driver and IPS interop

[Why]
Two issues fixed:

1. Currently, driver does not allow idle prior to PSR entry. Once
   PSR1+IPS is enabled, there is intermittent hang due to DCN access
from IrqMgr during IPS2.

2. Driver is sending multiple commands to PMFW and dmcub to exit IPS
   even during IPS0.

[How]
1. Set driver allow optimization prior to entering PSR mode with the
   condition for eDP display only.  Unregister all interrupts before
   allowing driver idle and re-register interrupts when exiting from
   idle. This will prevent IrqMgr to access DCN during IPS2.

2. Block sending PMFW and dmcub exit low power state commands when
   driver is not in idle state.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Jun Lei <jun.lei@amd.com>
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Duncan Ma <duncan.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

@@ -1110,6 +1110,10 @@ void dc_dmub_srv_exit_low_power_state(const struct dc *dc)
 {
 	if (dc->debug.dmcub_emulation)
 		return;
+
+	if (!dc->idle_optimizations_allowed)
+		return;
+
 	// Tell PMFW to exit low power state
 	if (dc->clk_mgr->funcs->exit_low_power_state)
 		dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hwseq.c

@@ -651,6 +651,8 @@ bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable)
 		// Tell PMFW to exit low power state
 		if (dc->clk_mgr->funcs->exit_low_power_state)
 			dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);
+
+		dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true);
 	}
 
 	dc_dmub_srv_notify_idle(dc, enable);