Commit dcac8eaa authored by Andrew Davis's avatar Andrew Davis Committed by Nishanth Menon

arm64: dts: ti: k3-am64: Enable ECAP nodes at the board level

ECAP nodes defined in the top-level AM64x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
information. (These and the EPWM nodes could be used to trigger internal
actions but they are not used like that currently)

As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.

Disable the ECAP nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: default avatarAndrew Davis <afd@ti.com>
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Reviewed-by: default avatarBryan Brattlof <bb@ti.com>
Acked-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20221017192532.23825-6-afd@ti.com
parent ebc0ed71
...@@ -988,6 +988,7 @@ ecap0: pwm@23100000 { ...@@ -988,6 +988,7 @@ ecap0: pwm@23100000 {
power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 51 0>; clocks = <&k3_clks 51 0>;
clock-names = "fck"; clock-names = "fck";
status = "disabled";
}; };
ecap1: pwm@23110000 { ecap1: pwm@23110000 {
...@@ -997,6 +998,7 @@ ecap1: pwm@23110000 { ...@@ -997,6 +998,7 @@ ecap1: pwm@23110000 {
power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 52 0>; clocks = <&k3_clks 52 0>;
clock-names = "fck"; clock-names = "fck";
status = "disabled";
}; };
ecap2: pwm@23120000 { ecap2: pwm@23120000 {
...@@ -1006,6 +1008,7 @@ ecap2: pwm@23120000 { ...@@ -1006,6 +1008,7 @@ ecap2: pwm@23120000 {
power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 53 0>; clocks = <&k3_clks 53 0>;
clock-names = "fck"; clock-names = "fck";
status = "disabled";
}; };
main_rti0: watchdog@e000000 { main_rti0: watchdog@e000000 {
......
...@@ -567,19 +567,12 @@ &pcie0_ep { ...@@ -567,19 +567,12 @@ &pcie0_ep {
}; };
&ecap0 { &ecap0 {
status = "okay";
/* PWM is available on Pin 1 of header J12 */ /* PWM is available on Pin 1 of header J12 */
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&main_ecap0_pins_default>; pinctrl-0 = <&main_ecap0_pins_default>;
}; };
&ecap1 {
status = "disabled";
};
&ecap2 {
status = "disabled";
};
&icssg0_mdio { &icssg0_mdio {
status = "disabled"; status = "disabled";
}; };
......
...@@ -566,19 +566,12 @@ &pcie0_ep { ...@@ -566,19 +566,12 @@ &pcie0_ep {
}; };
&ecap0 { &ecap0 {
status = "okay";
/* PWM is available on Pin 1 of header J3 */ /* PWM is available on Pin 1 of header J3 */
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&main_ecap0_pins_default>; pinctrl-0 = <&main_ecap0_pins_default>;
}; };
&ecap1 {
status = "disabled";
};
&ecap2 {
status = "disabled";
};
&icssg0_mdio { &icssg0_mdio {
status = "disabled"; status = "disabled";
}; };
......
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