Commit dd0a0281 authored by Manuel Lauss's avatar Manuel Lauss Committed by Ralf Baechle

MIPS: Alchemy: DB1200: Disable cascade IRQ in handler

Disable the cascade IRQ in the cascade handler.  This is required to
get the DB1300 working, and also gets rid of all spurious interrupts
previously observed on the DB1200; so Config[OD] can be disabled
again for better performance.
Signed-off-by: default avatarManuel Lauss <manuel.lauss@googlemail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/2708/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent b7867f1b
...@@ -89,8 +89,12 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d) ...@@ -89,8 +89,12 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d)
{ {
unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT); unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT);
disable_irq_nosync(irq);
for ( ; bisr; bisr &= bisr - 1) for ( ; bisr; bisr &= bisr - 1)
generic_handle_irq(bcsr_csc_base + __ffs(bisr)); generic_handle_irq(bcsr_csc_base + __ffs(bisr));
enable_irq(irq);
} }
/* NOTE: both the enable and mask bits must be cleared, otherwise the /* NOTE: both the enable and mask bits must be cleared, otherwise the
......
...@@ -23,13 +23,6 @@ void __init board_setup(void) ...@@ -23,13 +23,6 @@ void __init board_setup(void)
unsigned long freq0, clksrc, div, pfc; unsigned long freq0, clksrc, div, pfc;
unsigned short whoami; unsigned short whoami;
/* Set Config[OD] (disable overlapping bus transaction):
* This gets rid of a _lot_ of spurious interrupts (especially
* wrt. IDE); but incurs ~10% performance hit in some
* cpu-bound applications.
*/
set_c0_config(1 << 19);
bcsr_init(DB1200_BCSR_PHYS_ADDR, bcsr_init(DB1200_BCSR_PHYS_ADDR,
DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS); DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
......
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