Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Support
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in / Register
Toggle navigation
L
linux
Project overview
Project overview
Details
Activity
Releases
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Issues
0
Issues
0
List
Boards
Labels
Milestones
Merge Requests
0
Merge Requests
0
Analytics
Analytics
Repository
Value Stream
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Create a new issue
Commits
Issue Boards
Open sidebar
Kirill Smelkov
linux
Commits
dd67b155
Commit
dd67b155
authored
Oct 14, 2007
by
Ralf Baechle
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
[MIPS] IP32: Fix build by conversion to irq_cpu.c.
Signed-off-by:
Ralf Baechle
<
ralf@linux-mips.org
>
parent
65a6ec0d
Changes
4
Hide whitespace changes
Inline
Side-by-side
Showing
4 changed files
with
163 additions
and
160 deletions
+163
-160
arch/mips/Kconfig
arch/mips/Kconfig
+1
-0
arch/mips/sgi-ip32/ip32-irq.c
arch/mips/sgi-ip32/ip32-irq.c
+73
-89
arch/mips/sgi-ip32/ip32-setup.c
arch/mips/sgi-ip32/ip32-setup.c
+1
-1
include/asm-mips/ip32/ip32_ints.h
include/asm-mips/ip32/ip32_ints.h
+88
-70
No files found.
arch/mips/Kconfig
View file @
dd67b155
...
@@ -410,6 +410,7 @@ config SGI_IP32
...
@@ -410,6 +410,7 @@ config SGI_IP32
select BOOT_ELF32
select BOOT_ELF32
select DMA_NONCOHERENT
select DMA_NONCOHERENT
select HW_HAS_PCI
select HW_HAS_PCI
select IRQ_CPU
select R5000_CPU_SCACHE
select R5000_CPU_SCACHE
select RM7000_CPU_SCACHE
select RM7000_CPU_SCACHE
select SYS_HAS_CPU_R5000
select SYS_HAS_CPU_R5000
...
...
arch/mips/sgi-ip32/ip32-irq.c
View file @
dd67b155
...
@@ -20,6 +20,7 @@
...
@@ -20,6 +20,7 @@
#include <linux/random.h>
#include <linux/random.h>
#include <linux/sched.h>
#include <linux/sched.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <asm/mipsregs.h>
#include <asm/signal.h>
#include <asm/signal.h>
#include <asm/system.h>
#include <asm/system.h>
...
@@ -46,7 +47,8 @@ static void inline flush_mace_bus(void)
...
@@ -46,7 +47,8 @@ static void inline flush_mace_bus(void)
#define DBG(x...)
#define DBG(x...)
#endif
#endif
/* O2 irq map
/*
* O2 irq map
*
*
* IP0 -> software (ignored)
* IP0 -> software (ignored)
* IP1 -> software (ignored)
* IP1 -> software (ignored)
...
@@ -55,60 +57,60 @@ static void inline flush_mace_bus(void)
...
@@ -55,60 +57,60 @@ static void inline flush_mace_bus(void)
* IP4 -> (irq2) X unknown
* IP4 -> (irq2) X unknown
* IP5 -> (irq3) X unknown
* IP5 -> (irq3) X unknown
* IP6 -> (irq4) X unknown
* IP6 -> (irq4) X unknown
* IP7 -> (irq5)
0
CPU count/compare timer (system timer)
* IP7 -> (irq5)
7
CPU count/compare timer (system timer)
*
*
* crime: (C)
* crime: (C)
*
*
* CRIME_INT_STAT 31:0:
* CRIME_INT_STAT 31:0:
*
*
* 0 ->
1
Video in 1
* 0 ->
8
Video in 1
* 1 ->
2
Video in 2
* 1 ->
9
Video in 2
* 2 ->
3
Video out
* 2 ->
10
Video out
* 3 ->
4
Mace ethernet
* 3 ->
11
Mace ethernet
* 4 -> S SuperIO sub-interrupt
* 4 -> S SuperIO sub-interrupt
* 5 -> M Miscellaneous sub-interrupt
* 5 -> M Miscellaneous sub-interrupt
* 6 -> A Audio sub-interrupt
* 6 -> A Audio sub-interrupt
* 7 ->
8
PCI bridge errors
* 7 ->
15
PCI bridge errors
* 8 ->
9
PCI SCSI aic7xxx 0
* 8 ->
16
PCI SCSI aic7xxx 0
* 9 -> 1
0
PCI SCSI aic7xxx 1
* 9 -> 1
7
PCI SCSI aic7xxx 1
* 10 -> 1
1
PCI slot 0
* 10 -> 1
8
PCI slot 0
* 11 -> 1
2
unused (PCI slot 1)
* 11 -> 1
9
unused (PCI slot 1)
* 12 ->
13
unused (PCI slot 2)
* 12 ->
20
unused (PCI slot 2)
* 13 ->
14
unused (PCI shared 0)
* 13 ->
21
unused (PCI shared 0)
* 14 ->
15
unused (PCI shared 1)
* 14 ->
22
unused (PCI shared 1)
* 15 ->
16
unused (PCI shared 2)
* 15 ->
23
unused (PCI shared 2)
* 16 ->
17
GBE0 (E)
* 16 ->
24
GBE0 (E)
* 17 ->
18
GBE1 (E)
* 17 ->
25
GBE1 (E)
* 18 ->
19
GBE2 (E)
* 18 ->
26
GBE2 (E)
* 19 -> 2
0
GBE3 (E)
* 19 -> 2
7
GBE3 (E)
* 20 -> 2
1
CPU errors
* 20 -> 2
8
CPU errors
* 21 -> 2
2
Memory errors
* 21 -> 2
9
Memory errors
* 22 ->
23
RE empty edge (E)
* 22 ->
30
RE empty edge (E)
* 23 ->
24
RE full edge (E)
* 23 ->
31
RE full edge (E)
* 24 ->
25
RE idle edge (E)
* 24 ->
32
RE idle edge (E)
* 25 ->
26
RE empty level
* 25 ->
33
RE empty level
* 26 ->
27
RE full level
* 26 ->
34
RE full level
* 27 ->
28
RE idle level
* 27 ->
35
RE idle level
* 28 ->
29
unused (software 0) (E)
* 28 ->
36
unused (software 0) (E)
* 29 -> 3
0
unused (software 1) (E)
* 29 -> 3
7
unused (software 1) (E)
* 30 -> 3
1
unused (software 2) - crime 1.5 CPU SysCorError (E)
* 30 -> 3
8
unused (software 2) - crime 1.5 CPU SysCorError (E)
* 31 -> 3
2
VICE
* 31 -> 3
9
VICE
*
*
* S, M, A: Use the MACE ISA interrupt register
* S, M, A: Use the MACE ISA interrupt register
* MACE_ISA_INT_STAT 31:0
* MACE_ISA_INT_STAT 31:0
*
*
* 0-7 ->
33-40
Audio
* 0-7 ->
40-47
Audio
* 8 -> 4
1
RTC
* 8 -> 4
8
RTC
* 9 -> 4
2
Keyboard
* 9 -> 4
9
Keyboard
* 10 -> X Keyboard polled
* 10 -> X Keyboard polled
* 11 ->
44
Mouse
* 11 ->
51
Mouse
* 12 -> X Mouse polled
* 12 -> X Mouse polled
* 13-15 ->
46-48
Count/compare timers
* 13-15 ->
53-55
Count/compare timers
* 16-19 ->
49-52
Parallel (16 E)
* 16-19 ->
56-59
Parallel (16 E)
* 20-25 ->
53-58
Serial 1 (22 E)
* 20-25 ->
60-62
Serial 1 (22 E)
* 26-31 ->
59-64
Serial 2 (28 E)
* 26-31 ->
66-71
Serial 2 (28 E)
*
*
* Note that this means IRQs
5-7, 43, and 45
do not exist. This is a
* Note that this means IRQs
12-14, 50, and 52
do not exist. This is a
* different IRQ map than IRIX uses, but that's OK as Linux irq handling
* different IRQ map than IRIX uses, but that's OK as Linux irq handling
* is quite different anyway.
* is quite different anyway.
*/
*/
...
@@ -130,36 +132,6 @@ struct irqaction cpuerr_irq = {
...
@@ -130,36 +132,6 @@ struct irqaction cpuerr_irq = {
.
name
=
"CRIME CPU error"
,
.
name
=
"CRIME CPU error"
,
};
};
/*
* For interrupts wired from a single device to the CPU. Only the clock
* uses this it seems, which is IRQ 0 and IP7.
*/
static
void
enable_cpu_irq
(
unsigned
int
irq
)
{
set_c0_status
(
STATUSF_IP7
);
}
static
void
disable_cpu_irq
(
unsigned
int
irq
)
{
clear_c0_status
(
STATUSF_IP7
);
}
static
void
end_cpu_irq
(
unsigned
int
irq
)
{
if
(
!
(
irq_desc
[
irq
].
status
&
(
IRQ_DISABLED
|
IRQ_INPROGRESS
)))
enable_cpu_irq
(
irq
);
}
static
struct
irq_chip
ip32_cpu_interrupt
=
{
.
name
=
"IP32 CPU"
,
.
ack
=
disable_cpu_irq
,
.
mask
=
disable_cpu_irq
,
.
mask_ack
=
disable_cpu_irq
,
.
unmask
=
enable_cpu_irq
,
.
end
=
end_cpu_irq
,
};
/*
/*
* This is for pure CRIME interrupts - ie not MACE. The advantage?
* This is for pure CRIME interrupts - ie not MACE. The advantage?
* We get to split the register in half and do faster lookups.
* We get to split the register in half and do faster lookups.
...
@@ -422,15 +394,23 @@ static void ip32_irq0(void)
...
@@ -422,15 +394,23 @@ static void ip32_irq0(void)
uint64_t
crime_int
;
uint64_t
crime_int
;
int
irq
=
0
;
int
irq
=
0
;
/*
* Sanity check interrupt numbering enum.
* MACE got 32 interrupts and there are 32 MACE ISA interrupts daisy
* chained.
*/
BUILD_BUG_ON
(
CRIME_VICE_IRQ
-
MACE_VID_IN1_IRQ
!=
31
);
BUILD_BUG_ON
(
MACEISA_SERIAL2_RDMAOR_IRQ
-
MACEISA_AUDIO_SW_IRQ
!=
31
);
crime_int
=
crime
->
istat
&
crime_mask
;
crime_int
=
crime
->
istat
&
crime_mask
;
irq
=
__ffs
(
crime_int
);
irq
=
MACE_VID_IN1_IRQ
+
__ffs
(
crime_int
);
crime_int
=
1
<<
irq
;
crime_int
=
1
<<
irq
;
if
(
crime_int
&
CRIME_MACEISA_INT_MASK
)
{
if
(
crime_int
&
CRIME_MACEISA_INT_MASK
)
{
unsigned
long
mace_int
=
mace
->
perif
.
ctrl
.
istat
;
unsigned
long
mace_int
=
mace
->
perif
.
ctrl
.
istat
;
irq
=
__ffs
(
mace_int
&
maceisa_mask
)
+
32
;
irq
=
__ffs
(
mace_int
&
maceisa_mask
)
+
MACEISA_AUDIO_SW_IRQ
;
}
}
irq
++
;
DBG
(
"*irq %u*
\n
"
,
irq
);
DBG
(
"*irq %u*
\n
"
,
irq
);
do_IRQ
(
irq
);
do_IRQ
(
irq
);
}
}
...
@@ -457,7 +437,7 @@ static void ip32_irq4(void)
...
@@ -457,7 +437,7 @@ static void ip32_irq4(void)
static
void
ip32_irq5
(
void
)
static
void
ip32_irq5
(
void
)
{
{
do_IRQ
(
IP32_R4K_TIMER_IRQ
);
do_IRQ
(
MIPS_CPU_IRQ_BASE
+
7
);
}
}
asmlinkage
void
plat_irq_dispatch
(
void
)
asmlinkage
void
plat_irq_dispatch
(
void
)
...
@@ -490,21 +470,25 @@ void __init arch_init_irq(void)
...
@@ -490,21 +470,25 @@ void __init arch_init_irq(void)
mace
->
perif
.
ctrl
.
istat
=
0
;
mace
->
perif
.
ctrl
.
istat
=
0
;
mace
->
perif
.
ctrl
.
imask
=
0
;
mace
->
perif
.
ctrl
.
imask
=
0
;
for
(
irq
=
0
;
irq
<=
IP32_IRQ_MAX
;
irq
++
)
{
mips_cpu_irq_init
();
struct
irq_chip
*
controller
;
for
(
irq
=
MIPS_CPU_IRQ_BASE
+
8
;
irq
<=
IP32_IRQ_MAX
;
irq
++
)
{
struct
irq_chip
*
chip
;
if
(
irq
==
IP32_R4K_TIMER_IRQ
)
controller
=
&
ip32_cpu_interrupt
;
switch
(
irq
)
{
else
if
(
irq
<=
MACE_PCI_BRIDGE_IRQ
&&
irq
>=
MACE_VID_IN1_IRQ
)
case
MACE_VID_IN1_IRQ
...
MACE_PCI_BRIDGE_IRQ
:
controller
=
&
ip32_mace_interrupt
;
chip
=
&
ip32_mace_interrupt
;
else
if
(
irq
<=
MACEPCI_SHARED2_IRQ
&&
irq
>=
MACEPCI_SCSI0_IRQ
)
break
;
controller
=
&
ip32_macepci_interrupt
;
case
MACEPCI_SCSI0_IRQ
...
MACEPCI_SHARED2_IRQ
:
else
if
(
irq
<=
CRIME_VICE_IRQ
&&
irq
>=
CRIME_GBE0_IRQ
)
chip
=
&
ip32_macepci_interrupt
;
controller
=
&
ip32_crime_interrupt
;
break
;
else
case
CRIME_GBE0_IRQ
...
CRIME_VICE_IRQ
:
controller
=
&
ip32_maceisa_interrupt
;
chip
=
&
ip32_crime_interrupt
;
break
;
set_irq_chip
(
irq
,
controller
);
default:
chip
=
&
ip32_maceisa_interrupt
;
}
set_irq_chip
(
irq
,
chip
);
}
}
setup_irq
(
CRIME_MEMERR_IRQ
,
&
memerr_irq
);
setup_irq
(
CRIME_MEMERR_IRQ
,
&
memerr_irq
);
setup_irq
(
CRIME_CPUERR_IRQ
,
&
cpuerr_irq
);
setup_irq
(
CRIME_CPUERR_IRQ
,
&
cpuerr_irq
);
...
...
arch/mips/sgi-ip32/ip32-setup.c
View file @
dd67b155
...
@@ -83,7 +83,7 @@ void __init plat_time_init(void)
...
@@ -83,7 +83,7 @@ void __init plat_time_init(void)
void
__init
plat_timer_setup
(
struct
irqaction
*
irq
)
void
__init
plat_timer_setup
(
struct
irqaction
*
irq
)
{
{
irq
->
handler
=
no_action
;
irq
->
handler
=
no_action
;
setup_irq
(
IP32_R4K_TIMER_IRQ
,
irq
);
setup_irq
(
MIPS_CPU_IRQ_BASE
+
7
,
irq
);
}
}
void
__init
plat_mem_setup
(
void
)
void
__init
plat_mem_setup
(
void
)
...
...
include/asm-mips/ip32/ip32_ints.h
View file @
dd67b155
...
@@ -9,86 +9,104 @@
...
@@ -9,86 +9,104 @@
#ifndef __ASM_IP32_INTS_H
#ifndef __ASM_IP32_INTS_H
#define __ASM_IP32_INTS_H
#define __ASM_IP32_INTS_H
#include <asm/irq.h>
/*
/*
* This list reflects the assignment of interrupt numbers to
* This list reflects the assignment of interrupt numbers to
* interrupting events. Order is fairly irrelevant to handling
* interrupting events. Order is fairly irrelevant to handling
* priority. This differs from irix.
* priority. This differs from irix.
*/
*/
/* CPU */
enum
ip32_irq_no
{
#define IP32_R4K_TIMER_IRQ 0
/*
* CPU interrupts are 0 ... 7
*/
/* MACE */
/*
#define MACE_VID_IN1_IRQ 1
* MACE
#define MACE_VID_IN2_IRQ 2
*/
#define MACE_VID_OUT_IRQ 3
MACE_VID_IN1_IRQ
=
MIPS_CPU_IRQ_BASE
+
8
,
#define MACE_ETHERNET_IRQ 4
MACE_VID_IN2_IRQ
,
/* SUPERIO, MISC, and AUDIO are MACEISA */
MACE_VID_OUT_IRQ
,
#define MACE_PCI_BRIDGE_IRQ 8
MACE_ETHERNET_IRQ
,
/* SUPERIO, MISC, and AUDIO are MACEISA */
__MACE_SUPERIO
,
__MACE_MISC
,
__MACE_AUDIO
,
MACE_PCI_BRIDGE_IRQ
,
/* MACEPCI */
/*
#define MACEPCI_SCSI0_IRQ 9
* MACEPCI
#define MACEPCI_SCSI1_IRQ 10
*/
#define MACEPCI_SLOT0_IRQ 11
MACEPCI_SCSI0_IRQ
,
#define MACEPCI_SLOT1_IRQ 12
MACEPCI_SCSI1_IRQ
,
#define MACEPCI_SLOT2_IRQ 13
MACEPCI_SLOT0_IRQ
,
#define MACEPCI_SHARED0_IRQ 14
MACEPCI_SLOT1_IRQ
,
#define MACEPCI_SHARED1_IRQ 15
MACEPCI_SLOT2_IRQ
,
#define MACEPCI_SHARED2_IRQ 16
MACEPCI_SHARED0_IRQ
,
MACEPCI_SHARED1_IRQ
,
MACEPCI_SHARED2_IRQ
,
/* CRIME */
/*
#define CRIME_GBE0_IRQ 17
* CRIME
#define CRIME_GBE1_IRQ 18
*/
#define CRIME_GBE2_IRQ 19
CRIME_GBE0_IRQ
,
#define CRIME_GBE3_IRQ 20
CRIME_GBE1_IRQ
,
#define CRIME_CPUERR_IRQ 21
CRIME_GBE2_IRQ
,
#define CRIME_MEMERR_IRQ 22
CRIME_GBE3_IRQ
,
#define CRIME_RE_EMPTY_E_IRQ 23
CRIME_CPUERR_IRQ
,
#define CRIME_RE_FULL_E_IRQ 24
CRIME_MEMERR_IRQ
,
#define CRIME_RE_IDLE_E_IRQ 25
CRIME_RE_EMPTY_E_IRQ
,
#define CRIME_RE_EMPTY_L_IRQ 26
CRIME_RE_FULL_E_IRQ
,
#define CRIME_RE_FULL_L_IRQ 27
CRIME_RE_IDLE_E_IRQ
,
#define CRIME_RE_IDLE_L_IRQ 28
CRIME_RE_EMPTY_L_IRQ
,
#define CRIME_SOFT0_IRQ 29
CRIME_RE_FULL_L_IRQ
,
#define CRIME_SOFT1_IRQ 30
CRIME_RE_IDLE_L_IRQ
,
#define CRIME_SOFT2_IRQ 31
CRIME_SOFT0_IRQ
,
#define CRIME_SYSCORERR_IRQ CRIME_SOFT2_IRQ
CRIME_SOFT1_IRQ
,
#define CRIME_VICE_IRQ 32
CRIME_SOFT2_IRQ
,
CRIME_SYSCORERR_IRQ
=
CRIME_SOFT2_IRQ
,
CRIME_VICE_IRQ
,
/* MACEISA */
/*
#define MACEISA_AUDIO_SW_IRQ 33
* MACEISA
#define MACEISA_AUDIO_SC_IRQ 34
*/
#define MACEISA_AUDIO1_DMAT_IRQ 35
MACEISA_AUDIO_SW_IRQ
,
#define MACEISA_AUDIO1_OF_IRQ 36
MACEISA_AUDIO_SC_IRQ
,
#define MACEISA_AUDIO2_DMAT_IRQ 37
MACEISA_AUDIO1_DMAT_IRQ
,
#define MACEISA_AUDIO2_MERR_IRQ 38
MACEISA_AUDIO1_OF_IRQ
,
#define MACEISA_AUDIO3_DMAT_IRQ 39
MACEISA_AUDIO2_DMAT_IRQ
,
#define MACEISA_AUDIO3_MERR_IRQ 40
MACEISA_AUDIO2_MERR_IRQ
,
#define MACEISA_RTC_IRQ 41
MACEISA_AUDIO3_DMAT_IRQ
,
#define MACEISA_KEYB_IRQ 42
MACEISA_AUDIO3_MERR_IRQ
,
/* MACEISA_KEYB_POLL is not an IRQ */
MACEISA_RTC_IRQ
,
#define MACEISA_MOUSE_IRQ 44
MACEISA_KEYB_IRQ
,
/* MACEISA_MOUSE_POLL is not an IRQ */
/* MACEISA_KEYB_POLL is not an IRQ */
#define MACEISA_TIMER0_IRQ 46
__MACEISA_KEYB_POLL
,
#define MACEISA_TIMER1_IRQ 47
MACEISA_MOUSE_IRQ
,
#define MACEISA_TIMER2_IRQ 48
/* MACEISA_MOUSE_POLL is not an IRQ */
#define MACEISA_PARALLEL_IRQ 49
__MACEISA_MOUSE_POLL
,
#define MACEISA_PAR_CTXA_IRQ 50
MACEISA_TIMER0_IRQ
,
#define MACEISA_PAR_CTXB_IRQ 51
MACEISA_TIMER1_IRQ
,
#define MACEISA_PAR_MERR_IRQ 52
MACEISA_TIMER2_IRQ
,
#define MACEISA_SERIAL1_IRQ 53
MACEISA_PARALLEL_IRQ
,
#define MACEISA_SERIAL1_TDMAT_IRQ 54
MACEISA_PAR_CTXA_IRQ
,
#define MACEISA_SERIAL1_TDMAPR_IRQ 55
MACEISA_PAR_CTXB_IRQ
,
#define MACEISA_SERIAL1_TDMAME_IRQ 56
MACEISA_PAR_MERR_IRQ
,
#define MACEISA_SERIAL1_RDMAT_IRQ 57
MACEISA_SERIAL1_IRQ
,
#define MACEISA_SERIAL1_RDMAOR_IRQ 58
MACEISA_SERIAL1_TDMAT_IRQ
,
#define MACEISA_SERIAL2_IRQ 59
MACEISA_SERIAL1_TDMAPR_IRQ
,
#define MACEISA_SERIAL2_TDMAT_IRQ 60
MACEISA_SERIAL1_TDMAME_IRQ
,
#define MACEISA_SERIAL2_TDMAPR_IRQ 61
MACEISA_SERIAL1_RDMAT_IRQ
,
#define MACEISA_SERIAL2_TDMAME_IRQ 62
MACEISA_SERIAL1_RDMAOR_IRQ
,
#define MACEISA_SERIAL2_RDMAT_IRQ 63
MACEISA_SERIAL2_IRQ
,
#define MACEISA_SERIAL2_RDMAOR_IRQ 64
MACEISA_SERIAL2_TDMAT_IRQ
,
MACEISA_SERIAL2_TDMAPR_IRQ
,
MACEISA_SERIAL2_TDMAME_IRQ
,
MACEISA_SERIAL2_RDMAT_IRQ
,
MACEISA_SERIAL2_RDMAOR_IRQ
,
#define IP32_IRQ_MAX MACEISA_SERIAL2_RDMAOR_IRQ
IP32_IRQ_MAX
=
MACEISA_SERIAL2_RDMAOR_IRQ
};
#endif
/* __ASM_IP32_INTS_H */
#endif
/* __ASM_IP32_INTS_H */
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment