Commit dd94324b authored by Rajendra Nayak's avatar Rajendra Nayak Committed by Tero Kristo

ARM: dts: dra7xx-clocks: Fix the l3 and l4 clock rates

Without the patch:
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck # cat clk_rate
532000000
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div # cat clk_rate
532000000
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div/l4_root_clk_div # cat clk_rate
532000000

With the patch:
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck # cat clk_rate
532000000
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div # cat clk_rate
266000000
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div/l4_root_clk_div # cat clk_rate
133000000

The l3 clock derived from core DPLL is actually a divider clock,
with the default divider set to 2. l4 then derived from l3 is a fixed factor
clock, but the fixed divider is 2 and not 1. Which means the l3 clock is
half of core DPLLs h12x2 and l4 is half of l3 (as seen with this patch)
Signed-off-by: default avatarRajendra Nayak <rnayak@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
parent 7171511e
...@@ -673,10 +673,12 @@ hdmi_div_clk: hdmi_div_clk { ...@@ -673,10 +673,12 @@ hdmi_div_clk: hdmi_div_clk {
l3_iclk_div: l3_iclk_div { l3_iclk_div: l3_iclk_div {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-factor-clock"; compatible = "ti,divider-clock";
ti,max-div = <2>;
ti,bit-shift = <4>;
reg = <0x0100>;
clocks = <&dpll_core_h12x2_ck>; clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>; ti,index-power-of-two;
clock-div = <1>;
}; };
l4_root_clk_div: l4_root_clk_div { l4_root_clk_div: l4_root_clk_div {
...@@ -684,7 +686,7 @@ l4_root_clk_div: l4_root_clk_div { ...@@ -684,7 +686,7 @@ l4_root_clk_div: l4_root_clk_div {
compatible = "fixed-factor-clock"; compatible = "fixed-factor-clock";
clocks = <&l3_iclk_div>; clocks = <&l3_iclk_div>;
clock-mult = <1>; clock-mult = <1>;
clock-div = <1>; clock-div = <2>;
}; };
video1_clk2_div: video1_clk2_div { video1_clk2_div: video1_clk2_div {
......
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