Commit dda727ef authored by Paul Mackerras's avatar Paul Mackerras Committed by Ben Hutchings

powerpc: Don't try to fix up misaligned load-with-reservation instructions

commit 48fe9e94 upstream.

In the past, there was only one load-with-reservation instruction,
lwarx, and if a program attempted a lwarx on a misaligned address, it
would take an alignment interrupt and the kernel handler would emulate
it as though it was lwzx, which was not really correct, but benign since
it is loading the right amount of data, and the lwarx should be paired
with a stwcx. to the same address, which would also cause an alignment
interrupt which would result in a SIGBUS being delivered to the process.

We now have 5 different sizes of load-with-reservation instruction. Of
those, lharx and ldarx cause an immediate SIGBUS by luck since their
entries in aligninfo[] overlap instructions which were not fixed up, but
lqarx overlaps with lhz and will be emulated as such. lbarx can never
generate an alignment interrupt since it only operates on 1 byte.

To straighten this out and fix the lqarx case, this adds code to detect
the l[hwdq]arx instructions and return without fixing them up, resulting
in a SIGBUS being delivered to the process.
Signed-off-by: default avatarPaul Mackerras <paulus@ozlabs.org>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
[bwh: Backported to 3.2: open-code get_xop()]
Signed-off-by: default avatarBen Hutchings <ben@decadent.org.uk>
parent 02085b17
...@@ -764,14 +764,25 @@ int fix_alignment(struct pt_regs *regs) ...@@ -764,14 +764,25 @@ int fix_alignment(struct pt_regs *regs)
nb = aligninfo[instr].len; nb = aligninfo[instr].len;
flags = aligninfo[instr].flags; flags = aligninfo[instr].flags;
/* ldbrx/stdbrx overlap lfs/stfs in the DSISR unfortunately */ /*
if (IS_XFORM(instruction) && ((instruction >> 1) & 0x3ff) == 532) { * Handle some cases which give overlaps in the DSISR values.
nb = 8; */
flags = LD+SW; if (IS_XFORM(instruction)) {
} else if (IS_XFORM(instruction) && switch ((instruction >> 1) & 0x3ff) {
((instruction >> 1) & 0x3ff) == 660) { case 532: /* ldbrx */
nb = 8; nb = 8;
flags = ST+SW; flags = LD+SW;
break;
case 660: /* stdbrx */
nb = 8;
flags = ST+SW;
break;
case 20: /* lwarx */
case 84: /* ldarx */
case 116: /* lharx */
case 276: /* lqarx */
return 0; /* not emulated ever */
}
} }
/* Byteswap little endian loads and stores */ /* Byteswap little endian loads and stores */
......
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