Commit de7ecc4e authored by Piyush Mehta's avatar Piyush Mehta Committed by Greg Kroah-Hartman

usb: dwc3: xilinx: add reset-controller support

Add a reset-controller for supporting Xilinx versal platforms. To reset
the USB controller, get the reset ID from device-tree and using ID trigger
the reset, with the assert and deassert reset controller APIs for USB
controller initialization.
Signed-off-by: default avatarPiyush Mehta <piyush.mehta@amd.com>
Acked-by: default avatarThinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://lore.kernel.org/r/20231013125847.20334-1-piyush.mehta@amd.comSigned-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 46b6fc53
......@@ -32,9 +32,6 @@
#define XLNX_USB_TRAFFIC_ROUTE_CONFIG 0x005C
#define XLNX_USB_TRAFFIC_ROUTE_FPD 0x1
/* Versal USB Reset ID */
#define VERSAL_USB_RESET_ID 0xC104036
#define XLNX_USB_FPD_PIPE_CLK 0x7c
#define PIPE_CLK_DESELECT 1
#define PIPE_CLK_SELECT 0
......@@ -72,20 +69,23 @@ static void dwc3_xlnx_mask_phy_rst(struct dwc3_xlnx *priv_data, bool mask)
static int dwc3_xlnx_init_versal(struct dwc3_xlnx *priv_data)
{
struct device *dev = priv_data->dev;
struct reset_control *crst;
int ret;
crst = devm_reset_control_get_exclusive(dev, NULL);
if (IS_ERR(crst))
return dev_err_probe(dev, PTR_ERR(crst), "failed to get reset signal\n");
dwc3_xlnx_mask_phy_rst(priv_data, false);
/* Assert and De-assert reset */
ret = zynqmp_pm_reset_assert(VERSAL_USB_RESET_ID,
PM_RESET_ACTION_ASSERT);
ret = reset_control_assert(crst);
if (ret < 0) {
dev_err_probe(dev, ret, "failed to assert Reset\n");
return ret;
}
ret = zynqmp_pm_reset_assert(VERSAL_USB_RESET_ID,
PM_RESET_ACTION_RELEASE);
ret = reset_control_deassert(crst);
if (ret < 0) {
dev_err_probe(dev, ret, "failed to De-assert Reset\n");
return ret;
......
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