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Commit de8c72da authored by Vikas Chaudhary's avatar Vikas Chaudhary Committed by James Bottomley
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[SCSI] qla4xxx: Rename 82XX macros 

Signed-off-by: default avatarVikas Chaudhary <vikas.chaudhary@qlogic.com>
Reviewed-by: default avatarMike Christie <michaelc@cs.wisc.edu>
Signed-off-by: default avatarJames Bottomley <JBottomley@Parallels.com>
parent 5e9bcec7
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Showing with 139 additions and 139 deletions
drivers/scsi/qla4xxx/ql4_attr.c
View file @ de8c72da
......@@ -77,13 +77,13 @@ qla4_8xxx_sysfs_write_fw_dump(struct file *filep, struct kobject *kobj,
/* Reset HBA */
qla4_82xx_idc_lock(ha);
dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
if (dev_state == QLA82XX_DEV_READY) {
if (dev_state == QLA8XXX_DEV_READY) {
ql4_printk(KERN_INFO, ha,
"%s: Setting Need reset, reset_owner is 0x%x.\n",
__func__, ha->func_num);
qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
QLA82XX_DEV_NEED_RESET);
set_bit(AF_82XX_RST_OWNER, &ha->flags);
QLA8XXX_DEV_NEED_RESET);
set_bit(AF_8XXX_RST_OWNER, &ha->flags);
} else
ql4_printk(KERN_INFO, ha,
"%s: Reset not performed as device state is 0x%x\n",
......
drivers/scsi/qla4xxx/ql4_def.h
View file @ de8c72da
......@@ -497,7 +497,7 @@ struct scsi_qla_host {
#define AF_PCI_CHANNEL_IO_PERM_FAILURE 21 /* 0x00200000 */
#define AF_BUILD_DDB_LIST 22 /* 0x00400000 */
#define AF_82XX_FW_DUMPED 24 /* 0x01000000 */
#define AF_82XX_RST_OWNER 25 /* 0x02000000 */
#define AF_8XXX_RST_OWNER 25 /* 0x02000000 */
#define AF_82XX_DUMP_READING 26 /* 0x04000000 */
unsigned long dpc_flags;
......
drivers/scsi/qla4xxx/ql4_fw.h
View file @ de8c72da
......@@ -1195,9 +1195,9 @@ struct ql_iscsi_stats {
uint8_t reserved2[264]; /* 0x0308 - 0x040F */
};
#define QLA82XX_DBG_STATE_ARRAY_LEN 16
#define QLA82XX_DBG_CAP_SIZE_ARRAY_LEN 8
#define QLA82XX_DBG_RSVD_ARRAY_LEN 8
#define QLA8XXX_DBG_STATE_ARRAY_LEN 16
#define QLA8XXX_DBG_CAP_SIZE_ARRAY_LEN 8
#define QLA8XXX_DBG_RSVD_ARRAY_LEN 8
struct qla4_8xxx_minidump_template_hdr {
uint32_t entry_type;
......@@ -1214,8 +1214,8 @@ struct qla4_8xxx_minidump_template_hdr {
uint32_t driver_info_word3;
uint32_t driver_info_word4;
uint32_t saved_state_array[QLA82XX_DBG_STATE_ARRAY_LEN];
uint32_t capture_size_array[QLA82XX_DBG_CAP_SIZE_ARRAY_LEN];
uint32_t saved_state_array[QLA8XXX_DBG_STATE_ARRAY_LEN];
uint32_t capture_size_array[QLA8XXX_DBG_CAP_SIZE_ARRAY_LEN];
};
#endif /* _QLA4X_FW_H */
drivers/scsi/qla4xxx/ql4_mbx.c
View file @ de8c72da
......@@ -88,7 +88,7 @@ int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
qla4_82xx_idc_lock(ha);
dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
qla4_82xx_idc_unlock(ha);
if (dev_state == QLA82XX_DEV_FAILED) {
if (dev_state == QLA8XXX_DEV_FAILED) {
ql4_printk(KERN_WARNING, ha,
"scsi%ld: %s: H/W is in failed state, do not send any mailbox commands\n",
ha->host_no, __func__);
......
drivers/scsi/qla4xxx/ql4_nx.c
View file @ de8c72da
This diff is collapsed.
drivers/scsi/qla4xxx/ql4_nx.h
View file @ de8c72da
......@@ -490,8 +490,8 @@ enum {
* Base addresses of major components on-chip.
* ====================== BASE ADDRESSES ON-CHIP ======================
*/
#define QLA82XX_ADDR_DDR_NET (0x0000000000000000ULL)
#define QLA82XX_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
#define QLA8XXX_ADDR_DDR_NET (0x0000000000000000ULL)
#define QLA8XXX_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
/* Imbus address bit used to indicate a host address. This bit is
* eliminated by the pcie bar and bar select before presentation
......@@ -500,11 +500,11 @@ enum {
#define QLA82XX_P2_ADDR_PCIE (0x0000000800000000ULL)
#define QLA82XX_P3_ADDR_PCIE (0x0000008000000000ULL)
#define QLA82XX_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL)
#define QLA82XX_ADDR_OCM0 (0x0000000200000000ULL)
#define QLA82XX_ADDR_OCM0_MAX (0x00000002000fffffULL)
#define QLA82XX_ADDR_OCM1 (0x0000000200400000ULL)
#define QLA82XX_ADDR_OCM1_MAX (0x00000002004fffffULL)
#define QLA82XX_ADDR_QDR_NET (0x0000000300000000ULL)
#define QLA8XXX_ADDR_OCM0 (0x0000000200000000ULL)
#define QLA8XXX_ADDR_OCM0_MAX (0x00000002000fffffULL)
#define QLA8XXX_ADDR_OCM1 (0x0000000200400000ULL)
#define QLA8XXX_ADDR_OCM1_MAX (0x00000002004fffffULL)
#define QLA8XXX_ADDR_QDR_NET (0x0000000300000000ULL)
#define QLA82XX_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL)
#define QLA82XX_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL)
......@@ -572,13 +572,13 @@ enum {
#define QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c))
/* Every driver should use these Device State */
#define QLA82XX_DEV_COLD 1
#define QLA82XX_DEV_INITIALIZING 2
#define QLA82XX_DEV_READY 3
#define QLA82XX_DEV_NEED_RESET 4
#define QLA82XX_DEV_NEED_QUIESCENT 5
#define QLA82XX_DEV_FAILED 6
#define QLA82XX_DEV_QUIESCENT 7
#define QLA8XXX_DEV_COLD 1
#define QLA8XXX_DEV_INITIALIZING 2
#define QLA8XXX_DEV_READY 3
#define QLA8XXX_DEV_NEED_RESET 4
#define QLA8XXX_DEV_NEED_QUIESCENT 5
#define QLA8XXX_DEV_FAILED 6
#define QLA8XXX_DEV_QUIESCENT 7
#define MAX_STATES 8 /* Increment if new state added */
#define QLA82XX_IDC_VERSION 0x1
......@@ -795,41 +795,41 @@ struct crb_addr_pair {
/* Minidump related */
/* Entry Type Defines */
#define QLA82XX_RDNOP 0
#define QLA82XX_RDCRB 1
#define QLA82XX_RDMUX 2
#define QLA82XX_QUEUE 3
#define QLA82XX_BOARD 4
#define QLA82XX_RDOCM 6
#define QLA82XX_PREGS 7
#define QLA82XX_L1DTG 8
#define QLA82XX_L1ITG 9
#define QLA82XX_L1DAT 11
#define QLA82XX_L1INS 12
#define QLA82XX_L2DTG 21
#define QLA82XX_L2ITG 22
#define QLA82XX_L2DAT 23
#define QLA82XX_L2INS 24
#define QLA82XX_RDROM 71
#define QLA82XX_RDMEM 72
#define QLA82XX_CNTRL 98
#define QLA82XX_RDEND 255
#define QLA8XXX_RDNOP 0
#define QLA8XXX_RDCRB 1
#define QLA8XXX_RDMUX 2
#define QLA8XXX_QUEUE 3
#define QLA8XXX_BOARD 4
#define QLA8XXX_RDOCM 6
#define QLA8XXX_PREGS 7
#define QLA8XXX_L1DTG 8
#define QLA8XXX_L1ITG 9
#define QLA8XXX_L1DAT 11
#define QLA8XXX_L1INS 12
#define QLA8XXX_L2DTG 21
#define QLA8XXX_L2ITG 22
#define QLA8XXX_L2DAT 23
#define QLA8XXX_L2INS 24
#define QLA8XXX_RDROM 71
#define QLA8XXX_RDMEM 72
#define QLA8XXX_CNTRL 98
#define QLA8XXX_RDEND 255
/* Opcodes for Control Entries.
* These Flags are bit fields.
*/
#define QLA82XX_DBG_OPCODE_WR 0x01
#define QLA82XX_DBG_OPCODE_RW 0x02
#define QLA82XX_DBG_OPCODE_AND 0x04
#define QLA82XX_DBG_OPCODE_OR 0x08
#define QLA82XX_DBG_OPCODE_POLL 0x10
#define QLA82XX_DBG_OPCODE_RDSTATE 0x20
#define QLA82XX_DBG_OPCODE_WRSTATE 0x40
#define QLA82XX_DBG_OPCODE_MDSTATE 0x80
#define QLA8XXX_DBG_OPCODE_WR 0x01
#define QLA8XXX_DBG_OPCODE_RW 0x02
#define QLA8XXX_DBG_OPCODE_AND 0x04
#define QLA8XXX_DBG_OPCODE_OR 0x08
#define QLA8XXX_DBG_OPCODE_POLL 0x10
#define QLA8XXX_DBG_OPCODE_RDSTATE 0x20
#define QLA8XXX_DBG_OPCODE_WRSTATE 0x40
#define QLA8XXX_DBG_OPCODE_MDSTATE 0x80
/* Driver Flags */
#define QLA82XX_DBG_SKIPPED_FLAG 0x80 /* driver skipped this entry */
#define QLA82XX_DBG_SIZE_ERR_FLAG 0x40 /* Entry vs Capture size
#define QLA8XXX_DBG_SKIPPED_FLAG 0x80 /* driver skipped this entry */
#define QLA8XXX_DBG_SIZE_ERR_FLAG 0x40 /* Entry vs Capture size
* mismatch */
/* Driver_code is for driver to write some info about the entry
......
drivers/scsi/qla4xxx/ql4_os.c
View file @ de8c72da
......@@ -2525,7 +2525,7 @@ void qla4_8xxx_watchdog(struct scsi_qla_host *ha)
CRB_NIU_XG_PAUSE_CTL_P1);
set_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags);
qla4xxx_wake_dpc(ha);
} else if (dev_state == QLA82XX_DEV_NEED_RESET &&
} else if (dev_state == QLA8XXX_DEV_NEED_RESET &&
!test_bit(DPC_RESET_HA, &ha->dpc_flags)) {
if (!ql4xdontresethba) {
ql4_printk(KERN_INFO, ha, "%s: HW State: "
......@@ -2533,7 +2533,7 @@ void qla4_8xxx_watchdog(struct scsi_qla_host *ha)
set_bit(DPC_RESET_HA, &ha->dpc_flags);
qla4xxx_wake_dpc(ha);
}
} else if (dev_state == QLA82XX_DEV_NEED_QUIESCENT &&
} else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT &&
!test_bit(DPC_HA_NEED_QUIESCENT, &ha->dpc_flags)) {
ql4_printk(KERN_INFO, ha, "%s: HW State: NEED QUIES!\n",
__func__);
......@@ -3043,7 +3043,7 @@ static int qla4xxx_recover_adapter(struct scsi_qla_host *ha)
qla4_82xx_idc_lock(ha);
dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
qla4_82xx_idc_unlock(ha);
if (dev_state == QLA82XX_DEV_FAILED) {
if (dev_state == QLA8XXX_DEV_FAILED) {
ql4_printk(KERN_INFO, ha, "%s: don't retry "
"recover adapter. H/W is in Failed "
"state\n", __func__);
......@@ -3387,7 +3387,7 @@ static void qla4xxx_do_dpc(struct work_struct *work)
if (test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags)) {
qla4_82xx_idc_lock(ha);
qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
QLA82XX_DEV_FAILED);
QLA8XXX_DEV_FAILED);
qla4_82xx_idc_unlock(ha);
ql4_printk(KERN_INFO, ha, "HW State: FAILED\n");
qla4_8xxx_device_state_handler(ha);
......@@ -5164,7 +5164,7 @@ static int __devinit qla4xxx_probe_adapter(struct pci_dev *pdev,
qla4_82xx_idc_lock(ha);
dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
qla4_82xx_idc_unlock(ha);
if (dev_state == QLA82XX_DEV_FAILED) {
if (dev_state == QLA8XXX_DEV_FAILED) {
ql4_printk(KERN_WARNING, ha, "%s: don't retry "
"initialize adapter. H/W is in failed state\n",
__func__);
......@@ -5188,7 +5188,7 @@ static int __devinit qla4xxx_probe_adapter(struct pci_dev *pdev,
DEBUG2(printk(KERN_ERR "HW STATE: FAILED\n"));
qla4_82xx_idc_lock(ha);
qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
QLA82XX_DEV_FAILED);
QLA8XXX_DEV_FAILED);
qla4_82xx_idc_unlock(ha);
}
ret = -ENODEV;
......@@ -6035,7 +6035,7 @@ static uint32_t qla4_8xxx_error_recovery(struct scsi_qla_host *ha)
qla4_82xx_idc_lock(ha);
qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
QLA82XX_DEV_COLD);
QLA8XXX_DEV_COLD);
qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
QLA82XX_IDC_VERSION);
......@@ -6050,12 +6050,12 @@ static uint32_t qla4_8xxx_error_recovery(struct scsi_qla_host *ha)
"FAILED\n", ha->host_no, __func__);
qla4_8xxx_clear_drv_active(ha);
qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
QLA82XX_DEV_FAILED);
QLA8XXX_DEV_FAILED);
} else {
ql4_printk(KERN_INFO, ha, "scsi%ld: %s: HW State: "
"READY\n", ha->host_no, __func__);
qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
QLA82XX_DEV_READY);
QLA8XXX_DEV_READY);
/* Clear driver state register */
qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
qla4_8xxx_set_drv_active(ha);
......@@ -6076,7 +6076,7 @@ static uint32_t qla4_8xxx_error_recovery(struct scsi_qla_host *ha)
"the reset owner\n", ha->host_no, __func__,
ha->pdev->devfn);
if ((qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
QLA82XX_DEV_READY)) {
QLA8XXX_DEV_READY)) {
clear_bit(AF_FW_RECOVERY, &ha->flags);
rval = qla4xxx_initialize_adapter(ha, RESET_ADAPTER);
if (rval == QLA_SUCCESS) {
......
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