Commit dec39632 authored by Sowjanya Komatineni's avatar Sowjanya Komatineni Committed by Thierry Reding

clk: tegra: Add Tegra210 CSI TPG clock gate

Tegra210 CSI hardware internally uses PLLD for internal test pattern
generator logic.

PLLD_BASE register in CAR has a bit CSI_CLK_SOURCE to enable PLLD
out to CSI during TPG mode.

This patch adds this CSI TPG clock gate to Tegra210 clock driver
to allow Tegra video driver to ungate CSI TPG clock during TPG mode
and gate during non TPG mode.
Acked-by: default avatarStephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarSowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 42329854
...@@ -3076,6 +3076,13 @@ static __init void tegra210_periph_clk_init(struct device_node *np, ...@@ -3076,6 +3076,13 @@ static __init void tegra210_periph_clk_init(struct device_node *np,
periph_clk_enb_refcnt); periph_clk_enb_refcnt);
clks[TEGRA210_CLK_DSIB] = clk; clks[TEGRA210_CLK_DSIB] = clk;
/* csi_tpg */
clk = clk_register_gate(NULL, "csi_tpg", "pll_d",
CLK_SET_RATE_PARENT, clk_base + PLLD_BASE,
23, 0, &pll_d_lock);
clk_register_clkdev(clk, "csi_tpg", NULL);
clks[TEGRA210_CLK_CSI_TPG] = clk;
/* la */ /* la */
clk = tegra_clk_register_periph("la", la_parents, clk = tegra_clk_register_periph("la", la_parents,
ARRAY_SIZE(la_parents), &tegra210_la, clk_base, ARRAY_SIZE(la_parents), &tegra210_la, clk_base,
......
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