Commit df421a3a authored by Mark Brown's avatar Mark Brown

Merge series "ASoC: remove cppchecks warnings on lm49453 and da732x" from...

Merge series "ASoC: remove cppchecks warnings on lm49453 and da732x" from Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>:

There are the last two patches in the cleanups, this time I am not
sure what the code does and what the proper fix might be. Feedback
welcome.

Pierre-Louis Bossart (2):
  ASoC: lm49453: fix useless assignment before return
  ASoC: da732x: simplify code

 sound/soc/codecs/da732x.c  | 17 ++++++-----------
 sound/soc/codecs/da732x.h  | 12 ++++--------
 sound/soc/codecs/lm49453.c |  2 --
 3 files changed, 10 insertions(+), 21 deletions(-)

--
2.25.1
parents 75c324d5 945b0b58
......@@ -168,30 +168,25 @@ static const struct reg_default da732x_reg_cache[] = {
static inline int da732x_get_input_div(struct snd_soc_component *component, int sysclk)
{
int val;
int ret;
if (sysclk < DA732X_MCLK_10MHZ) {
val = DA732X_MCLK_RET_0_10MHZ;
ret = DA732X_MCLK_VAL_0_10MHZ;
val = DA732X_MCLK_VAL_0_10MHZ;
} else if ((sysclk >= DA732X_MCLK_10MHZ) &&
(sysclk < DA732X_MCLK_20MHZ)) {
val = DA732X_MCLK_RET_10_20MHZ;
ret = DA732X_MCLK_VAL_10_20MHZ;
val = DA732X_MCLK_VAL_10_20MHZ;
} else if ((sysclk >= DA732X_MCLK_20MHZ) &&
(sysclk < DA732X_MCLK_40MHZ)) {
val = DA732X_MCLK_RET_20_40MHZ;
ret = DA732X_MCLK_VAL_20_40MHZ;
val = DA732X_MCLK_VAL_20_40MHZ;
} else if ((sysclk >= DA732X_MCLK_40MHZ) &&
(sysclk <= DA732X_MCLK_54MHZ)) {
val = DA732X_MCLK_RET_40_54MHZ;
ret = DA732X_MCLK_VAL_40_54MHZ;
val = DA732X_MCLK_VAL_40_54MHZ;
} else {
return -EINVAL;
}
snd_soc_component_write(component, DA732X_REG_PLL_CTRL, val);
return ret;
return val;
}
static void da732x_set_charge_pump(struct snd_soc_component *component, int state)
......@@ -1158,7 +1153,7 @@ static int da732x_set_dai_pll(struct snd_soc_component *component, int pll_id,
if (indiv < 0)
return indiv;
fref = (da732x->sysclk / indiv);
fref = da732x->sysclk / BIT(indiv);
div_hi = freq_out / fref;
frac_div = (u64)(freq_out % fref) * 8192ULL;
do_div(frac_div, fref);
......
......@@ -48,14 +48,10 @@
#define DA732X_MCLK_20MHZ 20000000
#define DA732X_MCLK_40MHZ 40000000
#define DA732X_MCLK_54MHZ 54000000
#define DA732X_MCLK_RET_0_10MHZ 0
#define DA732X_MCLK_VAL_0_10MHZ 1
#define DA732X_MCLK_RET_10_20MHZ 1
#define DA732X_MCLK_VAL_10_20MHZ 2
#define DA732X_MCLK_RET_20_40MHZ 2
#define DA732X_MCLK_VAL_20_40MHZ 4
#define DA732X_MCLK_RET_40_54MHZ 3
#define DA732X_MCLK_VAL_40_54MHZ 8
#define DA732X_MCLK_VAL_0_10MHZ 0
#define DA732X_MCLK_VAL_10_20MHZ 1
#define DA732X_MCLK_VAL_20_40MHZ 2
#define DA732X_MCLK_VAL_40_54MHZ 3
#define DA732X_DAI_ID1 0
#define DA732X_DAI_ID2 1
#define DA732X_SRCCLK_PLL 0
......
......@@ -1206,8 +1206,6 @@ static int lm49453_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
break;
case 48000:
case 32576:
/* fll clk slection */
pll_clk = BIT(4);
return 0;
default:
return -EINVAL;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment