Commit df4a17a9 authored by Yangyang Li's avatar Yangyang Li Committed by David S. Miller

net: marvell: Fix the trailing format of some block comments

Use a trailing */ on a separate line for block comments.
Signed-off-by: default avatarYangyang Li <liyangyang20@huawei.com>
Signed-off-by: default avatarWeihang Li <liweihang@huawei.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent b52f6425
...@@ -700,7 +700,8 @@ static int skb_tx_csum(struct mv643xx_eth_private *mp, struct sk_buff *skb, ...@@ -700,7 +700,8 @@ static int skb_tx_csum(struct mv643xx_eth_private *mp, struct sk_buff *skb,
ip_hdr(skb)->ihl << TX_IHL_SHIFT; ip_hdr(skb)->ihl << TX_IHL_SHIFT;
/* TODO: Revisit this. With the usage of GEN_TCP_UDP_CHK_FULL /* TODO: Revisit this. With the usage of GEN_TCP_UDP_CHK_FULL
* it seems we don't need to pass the initial checksum. */ * it seems we don't need to pass the initial checksum.
*/
switch (ip_hdr(skb)->protocol) { switch (ip_hdr(skb)->protocol) {
case IPPROTO_UDP: case IPPROTO_UDP:
cmd |= UDP_FRAME; cmd |= UDP_FRAME;
...@@ -790,7 +791,8 @@ txq_put_hdr_tso(struct sk_buff *skb, struct tx_queue *txq, int length, ...@@ -790,7 +791,8 @@ txq_put_hdr_tso(struct sk_buff *skb, struct tx_queue *txq, int length,
WARN(1, "failed to prepare checksum!"); WARN(1, "failed to prepare checksum!");
/* Should we set this? Can't use the value from skb_tx_csum() /* Should we set this? Can't use the value from skb_tx_csum()
* as it's not the correct initial L4 checksum to use. */ * as it's not the correct initial L4 checksum to use.
*/
desc->l4i_chk = 0; desc->l4i_chk = 0;
desc->byte_cnt = hdr_len; desc->byte_cnt = hdr_len;
......
...@@ -3993,7 +3993,8 @@ static void mvneta_mac_config(struct phylink_config *config, unsigned int mode, ...@@ -3993,7 +3993,8 @@ static void mvneta_mac_config(struct phylink_config *config, unsigned int mode,
/* Armada 370 documentation says we can only change the port mode /* Armada 370 documentation says we can only change the port mode
* and in-band enable when the link is down, so force it down * and in-band enable when the link is down, so force it down
* while making these changes. We also do this for GMAC_CTRL2 */ * while making these changes. We also do this for GMAC_CTRL2
*/
if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X || if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X ||
(new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE || (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE ||
(new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) { (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) {
...@@ -4905,7 +4906,8 @@ static int mvneta_ethtool_set_eee(struct net_device *dev, ...@@ -4905,7 +4906,8 @@ static int mvneta_ethtool_set_eee(struct net_device *dev,
u32 lpi_ctl0; u32 lpi_ctl0;
/* The Armada 37x documents do not give limits for this other than /* The Armada 37x documents do not give limits for this other than
* it being an 8-bit register. */ * it being an 8-bit register.
*/
if (eee->tx_lpi_enabled && eee->tx_lpi_timer > 255) if (eee->tx_lpi_enabled && eee->tx_lpi_timer > 255)
return -EINVAL; return -EINVAL;
......
...@@ -55,7 +55,8 @@ ...@@ -55,7 +55,8 @@
#define RX_DEF_PENDING RX_MAX_PENDING #define RX_DEF_PENDING RX_MAX_PENDING
/* This is the worst case number of transmit list elements for a single skb: /* This is the worst case number of transmit list elements for a single skb:
VLAN:GSO + CKSUM + Data + skb_frags * DMA */ * VLAN:GSO + CKSUM + Data + skb_frags * DMA
*/
#define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1)) #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
#define TX_MIN_PENDING (MAX_SKB_TX_LE+1) #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
#define TX_MAX_PENDING 1024 #define TX_MAX_PENDING 1024
...@@ -1529,7 +1530,8 @@ static void sky2_rx_start(struct sky2_port *sky2) ...@@ -1529,7 +1530,8 @@ static void sky2_rx_start(struct sky2_port *sky2)
sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
/* These chips have no ram buffer? /* These chips have no ram buffer?
* MAC Rx RAM Read is controlled by hardware */ * MAC Rx RAM Read is controlled by hardware
*/
if (hw->chip_id == CHIP_ID_YUKON_EC_U && if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
hw->chip_rev > CHIP_REV_YU_EC_U_A0) hw->chip_rev > CHIP_REV_YU_EC_U_A0)
sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS); sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
...@@ -4684,7 +4686,8 @@ static __exit void sky2_debug_cleanup(void) ...@@ -4684,7 +4686,8 @@ static __exit void sky2_debug_cleanup(void)
#endif #endif
/* Two copies of network device operations to handle special case of /* Two copies of network device operations to handle special case of
not allowing netpoll on second port */ * not allowing netpoll on second port
*/
static const struct net_device_ops sky2_netdev_ops[2] = { static const struct net_device_ops sky2_netdev_ops[2] = {
{ {
.ndo_open = sky2_open, .ndo_open = sky2_open,
......
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