Commit e067096c authored by Arnd Bergmann's avatar Arnd Bergmann

Merge branch 'tegra/soc' into next/boards

Conflicts:
	arch/arm/mach-tegra/board-harmony-pcie.c

To fix an internal merge conflict between the tegra/soc and tegra/boards
branches.
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 1fc3eb81 e5570bbc
NVIDIA Tegra device tree bindings
-------------------------------------------
Boards with the tegra20 SoC shall have the following properties:
Required root node property:
compatible = "nvidia,tegra20";
Boards with the tegra30 SoC shall have the following properties:
Required root node property:
compatible = "nvidia,tegra30";
Tegra SOC USB controllers
The device node for a USB controller that is part of a Tegra
SOC is as described in the document "Open Firmware Recommended
Practice : Universal Serial Bus" with the following modifications
and additions :
Required properties :
- compatible : Should be "nvidia,tegra20-ehci" for USB controllers
used in host mode.
- phy_type : Should be one of "ulpi" or "utmi".
- nvidia,vbus-gpio : If present, specifies a gpio that needs to be
activated for the bus to be powered.
/dts-v1/;
/include/ "tegra30.dtsi"
/ {
model = "NVIDIA Tegra30 Cardhu evaluation board";
compatible = "nvidia,cardhu", "nvidia,tegra30";
memory {
reg = < 0x80000000 0x40000000 >;
};
serial@70006000 {
clock-frequency = < 408000000 >;
};
i2c@7000c000 {
clock-frequency = <100000>;
};
i2c@7000c400 {
clock-frequency = <100000>;
};
i2c@7000c500 {
clock-frequency = <100000>;
};
i2c@7000c700 {
clock-frequency = <100000>;
};
i2c@7000d000 {
clock-frequency = <100000>;
};
};
/dts-v1/; /dts-v1/;
/memreserve/ 0x1c000000 0x04000000;
/include/ "tegra20.dtsi" /include/ "tegra20.dtsi"
/ { / {
model = "NVIDIA Tegra2 Harmony evaluation board"; model = "NVIDIA Tegra2 Harmony evaluation board";
compatible = "nvidia,harmony", "nvidia,tegra20"; compatible = "nvidia,harmony", "nvidia,tegra20";
chosen {
bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk0p2 rw rootwait";
};
memory@0 { memory@0 {
reg = < 0x00000000 0x40000000 >; reg = < 0x00000000 0x40000000 >;
}; };
...@@ -52,16 +47,40 @@ sound { ...@@ -52,16 +47,40 @@ sound {
ext-mic-en-gpios = <&gpio 185 0>; ext-mic-en-gpios = <&gpio 185 0>;
}; };
serial@70006000 {
status = "disable";
};
serial@70006040 {
status = "disable";
};
serial@70006200 {
status = "disable";
};
serial@70006300 { serial@70006300 {
clock-frequency = < 216000000 >; clock-frequency = < 216000000 >;
}; };
serial@70006400 {
status = "disable";
};
sdhci@c8000000 {
status = "disable";
};
sdhci@c8000200 { sdhci@c8000200 {
cd-gpios = <&gpio 69 0>; /* gpio PI5 */ cd-gpios = <&gpio 69 0>; /* gpio PI5 */
wp-gpios = <&gpio 57 0>; /* gpio PH1 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */
power-gpios = <&gpio 155 0>; /* gpio PT3 */ power-gpios = <&gpio 155 0>; /* gpio PT3 */
}; };
sdhci@c8000400 {
status = "disable";
};
sdhci@c8000600 { sdhci@c8000600 {
cd-gpios = <&gpio 58 0>; /* gpio PH2 */ cd-gpios = <&gpio 58 0>; /* gpio PH2 */
wp-gpios = <&gpio 59 0>; /* gpio PH3 */ wp-gpios = <&gpio 59 0>; /* gpio PH3 */
......
/dts-v1/;
/include/ "tegra20.dtsi"
/ {
model = "Toshiba AC100 / Dynabook AZ";
compatible = "compal,paz00", "nvidia,tegra20";
memory@0 {
reg = <0x00000000 0x20000000>;
};
i2c@7000c000 {
clock-frequency = <400000>;
};
i2c@7000c400 {
clock-frequency = <400000>;
};
i2c@7000c500 {
status = "disable";
};
nvec@7000c500 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nvidia,nvec";
reg = <0x7000C500 0x100>;
interrupts = <0 92 0x04>;
clock-frequency = <80000>;
request-gpios = <&gpio 170 0>;
slave-addr = <138>;
};
i2c@7000d000 {
clock-frequency = <400000>;
};
serial@70006000 {
clock-frequency = <216000000>;
};
serial@70006040 {
status = "disable";
};
serial@70006200 {
status = "disable";
};
serial@70006300 {
clock-frequency = <216000000>;
};
serial@70006400 {
status = "disable";
};
sdhci@c8000000 {
cd-gpios = <&gpio 173 0>; /* gpio PV5 */
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
power-gpios = <&gpio 155 0>; /* gpio PT3 */
};
sdhci@c8000200 {
status = "disable";
};
sdhci@c8000400 {
status = "disable";
};
sdhci@c8000600 {
support-8bit;
};
};
/dts-v1/; /dts-v1/;
/memreserve/ 0x1c000000 0x04000000;
/include/ "tegra20.dtsi" /include/ "tegra20.dtsi"
/ { / {
model = "NVIDIA Seaboard"; model = "NVIDIA Seaboard";
compatible = "nvidia,seaboard", "nvidia,tegra20"; compatible = "nvidia,seaboard", "nvidia,tegra20";
chosen {
bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait";
};
memory { memory {
device_type = "memory"; device_type = "memory";
reg = < 0x00000000 0x40000000 >; reg = < 0x00000000 0x40000000 >;
}; };
i2c@7000c000 {
clock-frequency = <400000>;
};
i2c@7000c400 {
clock-frequency = <400000>;
};
i2c@7000c500 {
clock-frequency = <400000>;
};
i2c@7000d000 {
clock-frequency = <400000>;
};
serial@70006000 {
status = "disable";
};
serial@70006040 {
status = "disable";
};
serial@70006200 {
status = "disable";
};
serial@70006300 { serial@70006300 {
clock-frequency = < 216000000 >; clock-frequency = < 216000000 >;
}; };
serial@70006400 {
status = "disable";
};
sdhci@c8000000 {
status = "disable";
};
sdhci@c8000200 {
status = "disable";
};
sdhci@c8000400 { sdhci@c8000400 {
cd-gpios = <&gpio 69 0>; /* gpio PI5 */ cd-gpios = <&gpio 69 0>; /* gpio PI5 */
wp-gpios = <&gpio 57 0>; /* gpio PH1 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */
...@@ -29,4 +64,8 @@ sdhci@c8000400 { ...@@ -29,4 +64,8 @@ sdhci@c8000400 {
sdhci@c8000600 { sdhci@c8000600 {
support-8bit; support-8bit;
}; };
usb@c5000000 {
nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
};
}; };
/dts-v1/;
/include/ "tegra20.dtsi"
/ {
model = "Compulab TrimSlice board";
compatible = "compulab,trimslice", "nvidia,tegra20";
memory@0 {
reg = < 0x00000000 0x40000000 >;
};
i2c@7000c000 {
clock-frequency = <400000>;
};
i2c@7000c400 {
clock-frequency = <400000>;
};
i2c@7000c500 {
clock-frequency = <400000>;
};
i2c@7000d000 {
status = "disable";
};
serial@70006000 {
clock-frequency = < 216000000 >;
};
serial@70006040 {
status = "disable";
};
serial@70006200 {
status = "disable";
};
serial@70006300 {
status = "disable";
};
serial@70006400 {
status = "disable";
};
sdhci@c8000000 {
status = "disable";
};
sdhci@c8000200 {
status = "disable";
};
sdhci@c8000400 {
status = "disable";
};
sdhci@c8000600 {
cd-gpios = <&gpio 121 0>;
wp-gpios = <&gpio 122 0>;
};
};
/dts-v1/; /dts-v1/;
/memreserve/ 0x1c000000 0x04000000;
/include/ "tegra20.dtsi" /include/ "tegra20.dtsi"
/ { / {
model = "NVIDIA Tegra2 Ventana evaluation board"; model = "NVIDIA Tegra2 Ventana evaluation board";
compatible = "nvidia,ventana", "nvidia,tegra20"; compatible = "nvidia,ventana", "nvidia,tegra20";
chosen {
bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/ram rdinit=/sbin/init";
};
memory { memory {
reg = < 0x00000000 0x40000000 >; reg = < 0x00000000 0x40000000 >;
}; };
i2c@7000c000 {
clock-frequency = <400000>;
};
i2c@7000c400 {
clock-frequency = <400000>;
};
i2c@7000c500 {
clock-frequency = <400000>;
};
i2c@7000d000 {
clock-frequency = <400000>;
};
serial@70006000 {
status = "disable";
};
serial@70006040 {
status = "disable";
};
serial@70006200 {
status = "disable";
};
serial@70006300 { serial@70006300 {
clock-frequency = < 216000000 >; clock-frequency = < 216000000 >;
}; };
serial@70006400 {
status = "disable";
};
sdhci@c8000000 {
status = "disable";
};
sdhci@c8000200 {
status = "disable";
};
sdhci@c8000400 { sdhci@c8000400 {
cd-gpios = <&gpio 69 0>; /* gpio PI5 */ cd-gpios = <&gpio 69 0>; /* gpio PI5 */
wp-gpios = <&gpio 57 0>; /* gpio PH1 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */
......
...@@ -5,9 +5,9 @@ / { ...@@ -5,9 +5,9 @@ / {
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
intc: interrupt-controller@50041000 { intc: interrupt-controller@50041000 {
compatible = "nvidia,tegra20-gic"; compatible = "arm,cortex-a9-gic";
interrupt-controller; interrupt-controller;
#interrupt-cells = <1>; #interrupt-cells = <3>;
reg = < 0x50041000 0x1000 >, reg = < 0x50041000 0x1000 >,
< 0x50040100 0x0100 >; < 0x50040100 0x0100 >;
}; };
...@@ -17,7 +17,7 @@ i2c@7000c000 { ...@@ -17,7 +17,7 @@ i2c@7000c000 {
#size-cells = <0>; #size-cells = <0>;
compatible = "nvidia,tegra20-i2c"; compatible = "nvidia,tegra20-i2c";
reg = <0x7000C000 0x100>; reg = <0x7000C000 0x100>;
interrupts = < 70 >; interrupts = < 0 38 0x04 >;
}; };
i2c@7000c400 { i2c@7000c400 {
...@@ -25,7 +25,7 @@ i2c@7000c400 { ...@@ -25,7 +25,7 @@ i2c@7000c400 {
#size-cells = <0>; #size-cells = <0>;
compatible = "nvidia,tegra20-i2c"; compatible = "nvidia,tegra20-i2c";
reg = <0x7000C400 0x100>; reg = <0x7000C400 0x100>;
interrupts = < 116 >; interrupts = < 0 84 0x04 >;
}; };
i2c@7000c500 { i2c@7000c500 {
...@@ -33,7 +33,7 @@ i2c@7000c500 { ...@@ -33,7 +33,7 @@ i2c@7000c500 {
#size-cells = <0>; #size-cells = <0>;
compatible = "nvidia,tegra20-i2c"; compatible = "nvidia,tegra20-i2c";
reg = <0x7000C500 0x100>; reg = <0x7000C500 0x100>;
interrupts = < 124 >; interrupts = < 0 92 0x04 >;
}; };
i2c@7000d000 { i2c@7000d000 {
...@@ -41,30 +41,24 @@ i2c@7000d000 { ...@@ -41,30 +41,24 @@ i2c@7000d000 {
#size-cells = <0>; #size-cells = <0>;
compatible = "nvidia,tegra20-i2c"; compatible = "nvidia,tegra20-i2c";
reg = <0x7000D000 0x200>; reg = <0x7000D000 0x200>;
interrupts = < 85 >; interrupts = < 0 53 0x04 >;
}; };
i2s@70002800 { i2s@70002800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nvidia,tegra20-i2s"; compatible = "nvidia,tegra20-i2s";
reg = <0x70002800 0x200>; reg = <0x70002800 0x200>;
interrupts = < 45 >; interrupts = < 0 13 0x04 >;
dma-channel = < 2 >; dma-channel = < 2 >;
}; };
i2s@70002a00 { i2s@70002a00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nvidia,tegra20-i2s"; compatible = "nvidia,tegra20-i2s";
reg = <0x70002a00 0x200>; reg = <0x70002a00 0x200>;
interrupts = < 35 >; interrupts = < 0 3 0x04 >;
dma-channel = < 1 >; dma-channel = < 1 >;
}; };
das@70000c00 { das@70000c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nvidia,tegra20-das"; compatible = "nvidia,tegra20-das";
reg = <0x70000c00 0x80>; reg = <0x70000c00 0x80>;
}; };
...@@ -72,7 +66,13 @@ das@70000c00 { ...@@ -72,7 +66,13 @@ das@70000c00 {
gpio: gpio@6000d000 { gpio: gpio@6000d000 {
compatible = "nvidia,tegra20-gpio"; compatible = "nvidia,tegra20-gpio";
reg = < 0x6000d000 0x1000 >; reg = < 0x6000d000 0x1000 >;
interrupts = < 64 65 66 67 87 119 121 >; interrupts = < 0 32 0x04
0 33 0x04
0 34 0x04
0 35 0x04
0 55 0x04
0 87 0x04
0 89 0x04 >;
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-controller; gpio-controller;
}; };
...@@ -89,59 +89,80 @@ serial@70006000 { ...@@ -89,59 +89,80 @@ serial@70006000 {
compatible = "nvidia,tegra20-uart"; compatible = "nvidia,tegra20-uart";
reg = <0x70006000 0x40>; reg = <0x70006000 0x40>;
reg-shift = <2>; reg-shift = <2>;
interrupts = < 68 >; interrupts = < 0 36 0x04 >;
}; };
serial@70006040 { serial@70006040 {
compatible = "nvidia,tegra20-uart"; compatible = "nvidia,tegra20-uart";
reg = <0x70006040 0x40>; reg = <0x70006040 0x40>;
reg-shift = <2>; reg-shift = <2>;
interrupts = < 69 >; interrupts = < 0 37 0x04 >;
}; };
serial@70006200 { serial@70006200 {
compatible = "nvidia,tegra20-uart"; compatible = "nvidia,tegra20-uart";
reg = <0x70006200 0x100>; reg = <0x70006200 0x100>;
reg-shift = <2>; reg-shift = <2>;
interrupts = < 78 >; interrupts = < 0 46 0x04 >;
}; };
serial@70006300 { serial@70006300 {
compatible = "nvidia,tegra20-uart"; compatible = "nvidia,tegra20-uart";
reg = <0x70006300 0x100>; reg = <0x70006300 0x100>;
reg-shift = <2>; reg-shift = <2>;
interrupts = < 122 >; interrupts = < 0 90 0x04 >;
}; };
serial@70006400 { serial@70006400 {
compatible = "nvidia,tegra20-uart"; compatible = "nvidia,tegra20-uart";
reg = <0x70006400 0x100>; reg = <0x70006400 0x100>;
reg-shift = <2>; reg-shift = <2>;
interrupts = < 123 >; interrupts = < 0 91 0x04 >;
}; };
sdhci@c8000000 { sdhci@c8000000 {
compatible = "nvidia,tegra20-sdhci"; compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000000 0x200>; reg = <0xc8000000 0x200>;
interrupts = < 46 >; interrupts = < 0 14 0x04 >;
}; };
sdhci@c8000200 { sdhci@c8000200 {
compatible = "nvidia,tegra20-sdhci"; compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000200 0x200>; reg = <0xc8000200 0x200>;
interrupts = < 47 >; interrupts = < 0 15 0x04 >;
}; };
sdhci@c8000400 { sdhci@c8000400 {
compatible = "nvidia,tegra20-sdhci"; compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000400 0x200>; reg = <0xc8000400 0x200>;
interrupts = < 51 >; interrupts = < 0 19 0x04 >;
}; };
sdhci@c8000600 { sdhci@c8000600 {
compatible = "nvidia,tegra20-sdhci"; compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000600 0x200>; reg = <0xc8000600 0x200>;
interrupts = < 63 >; interrupts = < 0 31 0x04 >;
};
usb@c5000000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5000000 0x4000>;
interrupts = < 0 20 0x04 >;
phy_type = "utmi";
};
usb@c5004000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5004000 0x4000>;
interrupts = < 0 21 0x04 >;
phy_type = "ulpi";
};
usb@c5008000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5008000 0x4000>;
interrupts = < 0 97 0x04 >;
phy_type = "utmi";
}; };
}; };
/include/ "skeleton.dtsi"
/ {
compatible = "nvidia,tegra30";
interrupt-parent = <&intc>;
intc: interrupt-controller@50041000 {
compatible = "arm,cortex-a9-gic";
interrupt-controller;
#interrupt-cells = <3>;
reg = < 0x50041000 0x1000 >,
< 0x50040100 0x0100 >;
};
i2c@7000c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000C000 0x100>;
interrupts = < 0 38 0x04 >;
};
i2c@7000c400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000C400 0x100>;
interrupts = < 0 84 0x04 >;
};
i2c@7000c500 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000C500 0x100>;
interrupts = < 0 92 0x04 >;
};
i2c@7000c700 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000c700 0x100>;
interrupts = < 0 120 0x04 >;
};
i2c@7000d000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000D000 0x100>;
interrupts = < 0 53 0x04 >;
};
gpio: gpio@6000d000 {
compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
reg = < 0x6000d000 0x1000 >;
interrupts = < 0 32 0x04 0 33 0x04 0 34 0x04 0 35 0x04 0 55 0x04 0 87 0x04 0 89 0x04 >;
#gpio-cells = <2>;
gpio-controller;
};
serial@70006000 {
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006000 0x40>;
reg-shift = <2>;
interrupts = < 0 36 0x04 >;
};
serial@70006040 {
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006040 0x40>;
reg-shift = <2>;
interrupts = < 0 37 0x04 >;
};
serial@70006200 {
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006200 0x100>;
reg-shift = <2>;
interrupts = < 0 46 0x04 >;
};
serial@70006300 {
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006300 0x100>;
reg-shift = <2>;
interrupts = < 0 90 0x04 >;
};
serial@70006400 {
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006400 0x100>;
reg-shift = <2>;
interrupts = < 0 91 0x04 >;
};
sdhci@78000000 {
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
reg = <0x78000000 0x200>;
interrupts = < 0 14 0x04 >;
};
sdhci@78000200 {
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
reg = <0x78000200 0x200>;
interrupts = < 0 15 0x04 >;
};
sdhci@78000400 {
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
reg = <0x78000400 0x200>;
interrupts = < 0 19 0x04 >;
};
sdhci@78000600 {
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
reg = <0x78000600 0x200>;
interrupts = < 0 31 0x04 >;
};
pinmux: pinmux@70000000 {
compatible = "nvidia,tegra30-pinmux";
reg = < 0x70000868 0xd0 /* Pad control registers */
0x70003000 0x3e0 >; /* Mux registers */
};
};
...@@ -9,9 +9,8 @@ CONFIG_RESOURCE_COUNTERS=y ...@@ -9,9 +9,8 @@ CONFIG_RESOURCE_COUNTERS=y
CONFIG_CGROUP_SCHED=y CONFIG_CGROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y CONFIG_RT_GROUP_SCHED=y
CONFIG_BLK_DEV_INITRD=y CONFIG_BLK_DEV_INITRD=y
CONFIG_EMBEDDED=y
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_ELF_CORE is not set # CONFIG_ELF_CORE is not set
CONFIG_EMBEDDED=y
CONFIG_SLAB=y CONFIG_SLAB=y
CONFIG_MODULES=y CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_UNLOAD=y
...@@ -20,6 +19,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y ...@@ -20,6 +19,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set # CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_TEGRA=y CONFIG_ARCH_TEGRA=y
CONFIG_ARCH_TEGRA_2x_SOC=y
CONFIG_ARCH_TEGRA_3x_SOC=y
CONFIG_MACH_HARMONY=y CONFIG_MACH_HARMONY=y
CONFIG_MACH_KAEN=y CONFIG_MACH_KAEN=y
CONFIG_MACH_PAZ00=y CONFIG_MACH_PAZ00=y
...@@ -78,14 +79,12 @@ CONFIG_BLK_DEV_SD=y ...@@ -78,14 +79,12 @@ CONFIG_BLK_DEV_SD=y
# CONFIG_SCSI_LOWLEVEL is not set # CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y CONFIG_NETDEVICES=y
CONFIG_DUMMY=y CONFIG_DUMMY=y
CONFIG_NET_ETHERNET=y
CONFIG_R8169=y CONFIG_R8169=y
# CONFIG_NETDEV_10000 is not set
# CONFIG_WLAN is not set
CONFIG_USB_PEGASUS=y CONFIG_USB_PEGASUS=y
CONFIG_USB_USBNET=y CONFIG_USB_USBNET=y
CONFIG_USB_NET_SMSC75XX=y CONFIG_USB_NET_SMSC75XX=y
CONFIG_USB_NET_SMSC95XX=y CONFIG_USB_NET_SMSC95XX=y
# CONFIG_WLAN is not set
# CONFIG_INPUT is not set # CONFIG_INPUT is not set
# CONFIG_SERIO is not set # CONFIG_SERIO is not set
# CONFIG_VT is not set # CONFIG_VT is not set
......
...@@ -2,11 +2,8 @@ if ARCH_TEGRA ...@@ -2,11 +2,8 @@ if ARCH_TEGRA
comment "NVIDIA Tegra options" comment "NVIDIA Tegra options"
choice
prompt "Select Tegra processor family for target system"
config ARCH_TEGRA_2x_SOC config ARCH_TEGRA_2x_SOC
bool "Tegra 2 family" bool "Enable support for Tegra20 family"
select CPU_V7 select CPU_V7
select ARM_GIC select ARM_GIC
select ARCH_REQUIRE_GPIOLIB select ARCH_REQUIRE_GPIOLIB
...@@ -17,22 +14,36 @@ config ARCH_TEGRA_2x_SOC ...@@ -17,22 +14,36 @@ config ARCH_TEGRA_2x_SOC
Support for NVIDIA Tegra AP20 and T20 processors, based on the Support for NVIDIA Tegra AP20 and T20 processors, based on the
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
endchoice config ARCH_TEGRA_3x_SOC
bool "Enable support for Tegra30 family"
select CPU_V7
select ARM_GIC
select ARCH_REQUIRE_GPIOLIB
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select USB_ULPI if USB_SUPPORT
select USB_ULPI_VIEWPORT if USB_SUPPORT
select USE_OF
help
Support for NVIDIA Tegra T30 processor family, based on the
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
config TEGRA_PCI config TEGRA_PCI
bool "PCI Express support" bool "PCI Express support"
depends on ARCH_TEGRA_2x_SOC
select PCI select PCI
comment "Tegra board type" comment "Tegra board type"
config MACH_HARMONY config MACH_HARMONY
bool "Harmony board" bool "Harmony board"
depends on ARCH_TEGRA_2x_SOC
select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
help help
Support for nVidia Harmony development platform Support for nVidia Harmony development platform
config MACH_KAEN config MACH_KAEN
bool "Kaen board" bool "Kaen board"
depends on ARCH_TEGRA_2x_SOC
select MACH_SEABOARD select MACH_SEABOARD
select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
help help
...@@ -40,11 +51,13 @@ config MACH_KAEN ...@@ -40,11 +51,13 @@ config MACH_KAEN
config MACH_PAZ00 config MACH_PAZ00
bool "Paz00 board" bool "Paz00 board"
depends on ARCH_TEGRA_2x_SOC
help help
Support for the Toshiba AC100/Dynabook AZ netbook Support for the Toshiba AC100/Dynabook AZ netbook
config MACH_SEABOARD config MACH_SEABOARD
bool "Seaboard board" bool "Seaboard board"
depends on ARCH_TEGRA_2x_SOC
select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
help help
Support for nVidia Seaboard development platform. It will Support for nVidia Seaboard development platform. It will
...@@ -52,25 +65,29 @@ config MACH_SEABOARD ...@@ -52,25 +65,29 @@ config MACH_SEABOARD
have large similarities with the seaboard design. have large similarities with the seaboard design.
config MACH_TEGRA_DT config MACH_TEGRA_DT
bool "Generic Tegra board (FDT support)" bool "Generic Tegra20 board (FDT support)"
depends on ARCH_TEGRA_2x_SOC
select USE_OF select USE_OF
help help
Support for generic nVidia Tegra boards using Flattened Device Tree Support for generic NVIDIA Tegra20 boards using Flattened Device Tree
config MACH_TRIMSLICE config MACH_TRIMSLICE
bool "TrimSlice board" bool "TrimSlice board"
depends on ARCH_TEGRA_2x_SOC
select TEGRA_PCI select TEGRA_PCI
help help
Support for CompuLab TrimSlice platform Support for CompuLab TrimSlice platform
config MACH_WARIO config MACH_WARIO
bool "Wario board" bool "Wario board"
depends on ARCH_TEGRA_2x_SOC
select MACH_SEABOARD select MACH_SEABOARD
help help
Support for the Wario version of Seaboard Support for the Wario version of Seaboard
config MACH_VENTANA config MACH_VENTANA
bool "Ventana board" bool "Ventana board"
depends on ARCH_TEGRA_2x_SOC
select MACH_TEGRA_DT select MACH_TEGRA_DT
help help
Support for the nVidia Ventana development platform Support for the nVidia Ventana development platform
......
...@@ -6,12 +6,13 @@ obj-y += irq.o ...@@ -6,12 +6,13 @@ obj-y += irq.o
obj-y += clock.o obj-y += clock.o
obj-y += timer.o obj-y += timer.o
obj-y += pinmux.o obj-y += pinmux.o
obj-y += powergate.o
obj-y += fuse.o obj-y += fuse.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clock.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-t2-tables.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-tegra20-tables.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pinmux-tegra30-tables.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o
obj-$(CONFIG_SMP) += platsmp.o localtimer.o headsmp.o obj-$(CONFIG_SMP) += platsmp.o localtimer.o headsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o
...@@ -19,20 +20,22 @@ obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o ...@@ -19,20 +20,22 @@ obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o
obj-$(CONFIG_TEGRA_PCI) += pcie.o obj-$(CONFIG_TEGRA_PCI) += pcie.o
obj-$(CONFIG_USB_SUPPORT) += usb_phy.o obj-$(CONFIG_USB_SUPPORT) += usb_phy.o
obj-${CONFIG_MACH_HARMONY} += board-harmony.o obj-$(CONFIG_MACH_HARMONY) += board-harmony.o
obj-${CONFIG_MACH_HARMONY} += board-harmony-pinmux.o obj-$(CONFIG_MACH_HARMONY) += board-harmony-pinmux.o
obj-${CONFIG_MACH_HARMONY} += board-harmony-pcie.o obj-$(CONFIG_MACH_HARMONY) += board-harmony-pcie.o
obj-${CONFIG_MACH_HARMONY} += board-harmony-power.o obj-$(CONFIG_MACH_HARMONY) += board-harmony-power.o
obj-${CONFIG_MACH_PAZ00} += board-paz00.o obj-$(CONFIG_MACH_PAZ00) += board-paz00.o
obj-${CONFIG_MACH_PAZ00} += board-paz00-pinmux.o obj-$(CONFIG_MACH_PAZ00) += board-paz00-pinmux.o
obj-${CONFIG_MACH_SEABOARD} += board-seaboard.o obj-$(CONFIG_MACH_SEABOARD) += board-seaboard.o
obj-${CONFIG_MACH_SEABOARD} += board-seaboard-pinmux.o obj-$(CONFIG_MACH_SEABOARD) += board-seaboard-pinmux.o
obj-${CONFIG_MACH_TEGRA_DT} += board-dt.o obj-$(CONFIG_MACH_TEGRA_DT) += board-dt-tegra20.o
obj-${CONFIG_MACH_TEGRA_DT} += board-harmony-pinmux.o obj-$(CONFIG_MACH_TEGRA_DT) += board-harmony-pinmux.o
obj-${CONFIG_MACH_TEGRA_DT} += board-seaboard-pinmux.o obj-$(CONFIG_MACH_TEGRA_DT) += board-seaboard-pinmux.o
obj-$(CONFIG_MACH_TEGRA_DT) += board-paz00-pinmux.o
obj-$(CONFIG_MACH_TEGRA_DT) += board-trimslice-pinmux.o
obj-${CONFIG_MACH_TRIMSLICE} += board-trimslice.o obj-$(CONFIG_MACH_TRIMSLICE) += board-trimslice.o
obj-${CONFIG_MACH_TRIMSLICE} += board-trimslice-pinmux.o obj-$(CONFIG_MACH_TRIMSLICE) += board-trimslice-pinmux.o
...@@ -3,5 +3,8 @@ params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00000100 ...@@ -3,5 +3,8 @@ params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00000100
initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000 initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000
dtb-$(CONFIG_MACH_HARMONY) += tegra-harmony.dtb dtb-$(CONFIG_MACH_HARMONY) += tegra-harmony.dtb
dtb-$(CONFIG_MACH_PAZ00) += tegra-paz00.dtb
dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb
dtb-$(CONFIG_MACH_TRIMSLICE) += tegra-trimslice.dtb
dtb-$(CONFIG_MACH_VENTANA) += tegra-ventana.dtb dtb-$(CONFIG_MACH_VENTANA) += tegra-ventana.dtb
dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra-cardhu.dtb
...@@ -37,6 +37,7 @@ ...@@ -37,6 +37,7 @@
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
#include <asm/mach/time.h> #include <asm/mach/time.h>
#include <asm/setup.h> #include <asm/setup.h>
#include <asm/hardware/gic.h>
#include <mach/iomap.h> #include <mach/iomap.h>
#include <mach/irqs.h> #include <mach/irqs.h>
...@@ -47,7 +48,9 @@ ...@@ -47,7 +48,9 @@
#include "devices.h" #include "devices.h"
void harmony_pinmux_init(void); void harmony_pinmux_init(void);
void paz00_pinmux_init(void);
void seaboard_pinmux_init(void); void seaboard_pinmux_init(void);
void trimslice_pinmux_init(void);
void ventana_pinmux_init(void); void ventana_pinmux_init(void);
struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
...@@ -62,14 +65,28 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { ...@@ -62,14 +65,28 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C3_BASE, "tegra-i2c.2", NULL), OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C3_BASE, "tegra-i2c.2", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_DVC_BASE, "tegra-i2c.3", NULL), OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_DVC_BASE, "tegra-i2c.3", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra-i2s.0", NULL), OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra-i2s.0", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra-i2s.1", NULL), OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S2_BASE, "tegra-i2s.1", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra-das", NULL), OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra-das", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB_BASE, "tegra-ehci.0",
&tegra_ehci1_device.dev.platform_data),
OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB2_BASE, "tegra-ehci.1",
&tegra_ehci2_device.dev.platform_data),
OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2",
&tegra_ehci3_device.dev.platform_data),
{} {}
}; };
static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
/* name parent rate enabled */ /* name parent rate enabled */
{ "uartd", "pll_p", 216000000, true }, { "uartd", "pll_p", 216000000, true },
{ "usbd", "clk_m", 12000000, false },
{ "usb2", "clk_m", 12000000, false },
{ "usb3", "clk_m", 12000000, false },
{ "pll_a", "pll_p_out1", 56448000, true },
{ "pll_a_out0", "pll_a", 11289600, true },
{ "cdev1", NULL, 0, true },
{ "i2s1", "pll_a_out0", 11289600, false},
{ "i2s2", "pll_a_out0", 11289600, false},
{ NULL, NULL, 0, 0}, { NULL, NULL, 0, 0},
}; };
...@@ -78,30 +95,21 @@ static struct of_device_id tegra_dt_match_table[] __initdata = { ...@@ -78,30 +95,21 @@ static struct of_device_id tegra_dt_match_table[] __initdata = {
{} {}
}; };
static struct of_device_id tegra_dt_gic_match[] __initdata = {
{ .compatible = "nvidia,tegra20-gic", },
{}
};
static struct { static struct {
char *machine; char *machine;
void (*init)(void); void (*init)(void);
} pinmux_configs[] = { } pinmux_configs[] = {
{ "compulab,trimslice", trimslice_pinmux_init },
{ "nvidia,harmony", harmony_pinmux_init }, { "nvidia,harmony", harmony_pinmux_init },
{ "compal,paz00", paz00_pinmux_init },
{ "nvidia,seaboard", seaboard_pinmux_init }, { "nvidia,seaboard", seaboard_pinmux_init },
{ "nvidia,ventana", ventana_pinmux_init }, { "nvidia,ventana", ventana_pinmux_init },
}; };
static void __init tegra_dt_init(void) static void __init tegra_dt_init(void)
{ {
struct device_node *node;
int i; int i;
node = of_find_matching_node_by_address(NULL, tegra_dt_gic_match,
TEGRA_ARM_INT_DIST_BASE);
if (node)
irq_domain_add_simple(node, INT_GIC_BASE);
tegra_clk_init_from_table(tegra_dt_clk_init_table); tegra_clk_init_from_table(tegra_dt_clk_init_table);
for (i = 0; i < ARRAY_SIZE(pinmux_configs); i++) { for (i = 0; i < ARRAY_SIZE(pinmux_configs); i++) {
...@@ -122,19 +130,21 @@ static void __init tegra_dt_init(void) ...@@ -122,19 +130,21 @@ static void __init tegra_dt_init(void)
tegra20_auxdata_lookup, NULL); tegra20_auxdata_lookup, NULL);
} }
static const char * tegra_dt_board_compat[] = { static const char *tegra20_dt_board_compat[] = {
"compulab,trimslice",
"nvidia,harmony", "nvidia,harmony",
"compal,paz00",
"nvidia,seaboard", "nvidia,seaboard",
"nvidia,ventana", "nvidia,ventana",
NULL NULL
}; };
DT_MACHINE_START(TEGRA_DT, "nVidia Tegra (Flattened Device Tree)") DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)")
.map_io = tegra_map_common_io, .map_io = tegra_map_common_io,
.init_early = tegra_init_early, .init_early = tegra20_init_early,
.init_irq = tegra_init_irq, .init_irq = tegra_dt_init_irq,
.handle_irq = gic_handle_irq, .handle_irq = gic_handle_irq,
.timer = &tegra_timer, .timer = &tegra_timer,
.init_machine = tegra_dt_init, .init_machine = tegra_dt_init,
.dt_compat = tegra_dt_board_compat, .dt_compat = tegra20_dt_board_compat,
MACHINE_END MACHINE_END
/*
* arch/arm/mach-tegra/board-dt-tegra30.c
*
* NVIDIA Tegra30 device tree board support
*
* Copyright (C) 2011 NVIDIA Corporation
*
* Derived from:
*
* arch/arm/mach-tegra/board-dt-tegra20.c
*
* Copyright (C) 2010 Secret Lab Technologies, Ltd.
* Copyright (C) 2010 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_fdt.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>
#include "board.h"
static struct of_device_id tegra_dt_match_table[] __initdata = {
{ .compatible = "simple-bus", },
{}
};
static void __init tegra30_dt_init(void)
{
of_platform_populate(NULL, tegra_dt_match_table,
NULL, NULL);
}
static const char *tegra30_dt_board_compat[] = {
"nvidia,cardhu",
NULL
};
DT_MACHINE_START(TEGRA30_DT, "NVIDIA Tegra30 (Flattened Device Tree)")
.map_io = tegra_map_common_io,
.init_early = tegra30_init_early,
.init_irq = tegra_dt_init_irq,
.handle_irq = gic_handle_irq,
.timer = &tegra_timer,
.init_machine = tegra30_dt_init,
.restart = tegra_assert_system_reset,
.dt_compat = tegra30_dt_board_compat,
MACHINE_END
...@@ -19,6 +19,7 @@ ...@@ -19,6 +19,7 @@
#include <linux/of.h> #include <linux/of.h>
#include <mach/pinmux.h> #include <mach/pinmux.h>
#include <mach/pinmux-tegra20.h>
#include "gpio-names.h" #include "gpio-names.h"
#include "board-harmony.h" #include "board-harmony.h"
......
...@@ -186,7 +186,7 @@ MACHINE_START(HARMONY, "harmony") ...@@ -186,7 +186,7 @@ MACHINE_START(HARMONY, "harmony")
.atag_offset = 0x100, .atag_offset = 0x100,
.fixup = tegra_harmony_fixup, .fixup = tegra_harmony_fixup,
.map_io = tegra_map_common_io, .map_io = tegra_map_common_io,
.init_early = tegra_init_early, .init_early = tegra20_init_early,
.init_irq = tegra_init_irq, .init_irq = tegra_init_irq,
.handle_irq = gic_handle_irq, .handle_irq = gic_handle_irq,
.timer = &tegra_timer, .timer = &tegra_timer,
......
...@@ -19,6 +19,7 @@ ...@@ -19,6 +19,7 @@
#include <linux/of.h> #include <linux/of.h>
#include <mach/pinmux.h> #include <mach/pinmux.h>
#include <mach/pinmux-tegra20.h>
#include "gpio-names.h" #include "gpio-names.h"
#include "board-paz00.h" #include "board-paz00.h"
......
...@@ -216,7 +216,7 @@ MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ") ...@@ -216,7 +216,7 @@ MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ")
.atag_offset = 0x100, .atag_offset = 0x100,
.fixup = tegra_paz00_fixup, .fixup = tegra_paz00_fixup,
.map_io = tegra_map_common_io, .map_io = tegra_map_common_io,
.init_early = tegra_init_early, .init_early = tegra20_init_early,
.init_irq = tegra_init_irq, .init_irq = tegra_init_irq,
.handle_irq = gic_handle_irq, .handle_irq = gic_handle_irq,
.timer = &tegra_timer, .timer = &tegra_timer,
......
...@@ -19,7 +19,7 @@ ...@@ -19,7 +19,7 @@
#include <linux/of.h> #include <linux/of.h>
#include <mach/pinmux.h> #include <mach/pinmux.h>
#include <mach/pinmux-t2.h> #include <mach/pinmux-tegra20.h>
#include "gpio-names.h" #include "gpio-names.h"
#include "board-pinmux.h" #include "board-pinmux.h"
......
...@@ -283,7 +283,7 @@ static void __init tegra_wario_init(void) ...@@ -283,7 +283,7 @@ static void __init tegra_wario_init(void)
MACHINE_START(SEABOARD, "seaboard") MACHINE_START(SEABOARD, "seaboard")
.atag_offset = 0x100, .atag_offset = 0x100,
.map_io = tegra_map_common_io, .map_io = tegra_map_common_io,
.init_early = tegra_init_early, .init_early = tegra20_init_early,
.init_irq = tegra_init_irq, .init_irq = tegra_init_irq,
.handle_irq = gic_handle_irq, .handle_irq = gic_handle_irq,
.timer = &tegra_timer, .timer = &tegra_timer,
...@@ -293,7 +293,7 @@ MACHINE_END ...@@ -293,7 +293,7 @@ MACHINE_END
MACHINE_START(KAEN, "kaen") MACHINE_START(KAEN, "kaen")
.atag_offset = 0x100, .atag_offset = 0x100,
.map_io = tegra_map_common_io, .map_io = tegra_map_common_io,
.init_early = tegra_init_early, .init_early = tegra20_init_early,
.init_irq = tegra_init_irq, .init_irq = tegra_init_irq,
.handle_irq = gic_handle_irq, .handle_irq = gic_handle_irq,
.timer = &tegra_timer, .timer = &tegra_timer,
...@@ -303,7 +303,7 @@ MACHINE_END ...@@ -303,7 +303,7 @@ MACHINE_END
MACHINE_START(WARIO, "wario") MACHINE_START(WARIO, "wario")
.atag_offset = 0x100, .atag_offset = 0x100,
.map_io = tegra_map_common_io, .map_io = tegra_map_common_io,
.init_early = tegra_init_early, .init_early = tegra20_init_early,
.init_irq = tegra_init_irq, .init_irq = tegra_init_irq,
.handle_irq = gic_handle_irq, .handle_irq = gic_handle_irq,
.timer = &tegra_timer, .timer = &tegra_timer,
......
...@@ -19,6 +19,7 @@ ...@@ -19,6 +19,7 @@
#include <linux/of.h> #include <linux/of.h>
#include <mach/pinmux.h> #include <mach/pinmux.h>
#include <mach/pinmux-tegra20.h>
#include "gpio-names.h" #include "gpio-names.h"
#include "board-pinmux.h" #include "board-pinmux.h"
......
...@@ -175,7 +175,7 @@ MACHINE_START(TRIMSLICE, "trimslice") ...@@ -175,7 +175,7 @@ MACHINE_START(TRIMSLICE, "trimslice")
.atag_offset = 0x100, .atag_offset = 0x100,
.fixup = tegra_trimslice_fixup, .fixup = tegra_trimslice_fixup,
.map_io = tegra_map_common_io, .map_io = tegra_map_common_io,
.init_early = tegra_init_early, .init_early = tegra20_init_early,
.init_irq = tegra_init_irq, .init_irq = tegra_init_irq,
.handle_irq = gic_handle_irq, .handle_irq = gic_handle_irq,
.timer = &tegra_timer, .timer = &tegra_timer,
......
...@@ -25,10 +25,11 @@ ...@@ -25,10 +25,11 @@
void tegra_assert_system_reset(char mode, const char *cmd); void tegra_assert_system_reset(char mode, const char *cmd);
void __init tegra_init_early(void); void __init tegra20_init_early(void);
void __init tegra30_init_early(void);
void __init tegra_map_common_io(void); void __init tegra_map_common_io(void);
void __init tegra_init_irq(void); void __init tegra_init_irq(void);
void __init tegra_init_clock(void); void __init tegra_dt_init_irq(void);
int __init tegra_pcie_init(bool init_port0, bool init_port1); int __init tegra_pcie_init(bool init_port0, bool init_port1);
extern struct sys_timer tegra_timer; extern struct sys_timer tegra_timer;
......
...@@ -387,35 +387,18 @@ EXPORT_SYMBOL(tegra_clk_init_from_table); ...@@ -387,35 +387,18 @@ EXPORT_SYMBOL(tegra_clk_init_from_table);
void tegra_periph_reset_deassert(struct clk *c) void tegra_periph_reset_deassert(struct clk *c)
{ {
tegra2_periph_reset_deassert(c); BUG_ON(!c->ops->reset);
c->ops->reset(c, false);
} }
EXPORT_SYMBOL(tegra_periph_reset_deassert); EXPORT_SYMBOL(tegra_periph_reset_deassert);
void tegra_periph_reset_assert(struct clk *c) void tegra_periph_reset_assert(struct clk *c)
{ {
tegra2_periph_reset_assert(c); BUG_ON(!c->ops->reset);
c->ops->reset(c, true);
} }
EXPORT_SYMBOL(tegra_periph_reset_assert); EXPORT_SYMBOL(tegra_periph_reset_assert);
void __init tegra_init_clock(void)
{
tegra2_init_clocks();
}
/*
* The SDMMC controllers have extra bits in the clock source register that
* adjust the delay between the clock and data to compenstate for delays
* on the PCB.
*/
void tegra_sdmmc_tap_delay(struct clk *c, int delay)
{
unsigned long flags;
spin_lock_irqsave(&c->spinlock, flags);
tegra2_sdmmc_tap_delay(c, delay);
spin_unlock_irqrestore(&c->spinlock, flags);
}
#ifdef CONFIG_DEBUG_FS #ifdef CONFIG_DEBUG_FS
static int __clk_lock_all_spinlocks(void) static int __clk_lock_all_spinlocks(void)
......
...@@ -146,15 +146,11 @@ struct tegra_clk_init_table { ...@@ -146,15 +146,11 @@ struct tegra_clk_init_table {
}; };
void tegra2_init_clocks(void); void tegra2_init_clocks(void);
void tegra2_periph_reset_deassert(struct clk *c);
void tegra2_periph_reset_assert(struct clk *c);
void clk_init(struct clk *clk); void clk_init(struct clk *clk);
struct clk *tegra_get_clock_by_name(const char *name); struct clk *tegra_get_clock_by_name(const char *name);
unsigned long clk_measure_input_freq(void);
int clk_reparent(struct clk *c, struct clk *parent); int clk_reparent(struct clk *c, struct clk *parent);
void tegra_clk_init_from_table(struct tegra_clk_init_table *table); void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
unsigned long clk_get_rate_locked(struct clk *c); unsigned long clk_get_rate_locked(struct clk *c);
int clk_set_rate_locked(struct clk *c, unsigned long rate); int clk_set_rate_locked(struct clk *c, unsigned long rate);
void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
#endif #endif
/* /*
* arch/arm/mach-tegra/board-harmony.c * arch/arm/mach-tegra/common.c
* *
* Copyright (C) 2010 Google, Inc. * Copyright (C) 2010 Google, Inc.
* *
...@@ -21,8 +21,10 @@ ...@@ -21,8 +21,10 @@
#include <linux/io.h> #include <linux/io.h>
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/of_irq.h>
#include <asm/hardware/cache-l2x0.h> #include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
#include <mach/iomap.h> #include <mach/iomap.h>
#include <mach/system.h> #include <mach/system.h>
...@@ -33,18 +35,31 @@ ...@@ -33,18 +35,31 @@
void (*arch_reset)(char mode, const char *cmd) = tegra_assert_system_reset; void (*arch_reset)(char mode, const char *cmd) = tegra_assert_system_reset;
#ifdef CONFIG_OF
static const struct of_device_id tegra_dt_irq_match[] __initconst = {
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
{ }
};
void __init tegra_dt_init_irq(void)
{
tegra_init_irq();
of_irq_init(tegra_dt_irq_match);
}
#endif
void tegra_assert_system_reset(char mode, const char *cmd) void tegra_assert_system_reset(char mode, const char *cmd)
{ {
void __iomem *reset = IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x04); void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
u32 reg; u32 reg;
/* use *_related to avoid spinlock since caches are off */
reg = readl_relaxed(reset); reg = readl_relaxed(reset);
reg |= 0x04; reg |= 0x10;
writel_relaxed(reg, reset); writel_relaxed(reg, reset);
} }
static __initdata struct tegra_clk_init_table common_clk_init_table[] = { #ifdef CONFIG_ARCH_TEGRA_2x_SOC
static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
/* name parent rate enabled */ /* name parent rate enabled */
{ "clk_m", NULL, 0, true }, { "clk_m", NULL, 0, true },
{ "pll_p", "clk_m", 216000000, true }, { "pll_p", "clk_m", 216000000, true },
...@@ -60,24 +75,38 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = { ...@@ -60,24 +75,38 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
{ "cpu", NULL, 0, true }, { "cpu", NULL, 0, true },
{ NULL, NULL, 0, 0}, { NULL, NULL, 0, 0},
}; };
#endif
static void __init tegra_init_cache(void) static void __init tegra_init_cache(u32 tag_latency, u32 data_latency)
{ {
#ifdef CONFIG_CACHE_L2X0 #ifdef CONFIG_CACHE_L2X0
void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
u32 aux_ctrl, cache_type;
writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
writel_relaxed(0x331, p + L2X0_TAG_LATENCY_CTRL); cache_type = readl(p + L2X0_CACHE_TYPE);
writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL); aux_ctrl = (cache_type & 0x700) << (17-8);
aux_ctrl |= 0x6C000001;
l2x0_init(p, 0x6C080001, 0x8200c3fe); l2x0_init(p, aux_ctrl, 0x8200c3fe);
#endif #endif
} }
void __init tegra_init_early(void) #ifdef CONFIG_ARCH_TEGRA_2x_SOC
void __init tegra20_init_early(void)
{ {
tegra_init_fuse(); tegra_init_fuse();
tegra_init_clock(); tegra2_init_clocks();
tegra_clk_init_from_table(common_clk_init_table); tegra_clk_init_from_table(tegra20_clk_init_table);
tegra_init_cache(); tegra_init_cache(0x331, 0x441);
}
#endif
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
void __init tegra30_init_early(void)
{
tegra_init_cache(0x441, 0x551);
} }
#endif
...@@ -26,6 +26,6 @@ void tegra_periph_reset_deassert(struct clk *c); ...@@ -26,6 +26,6 @@ void tegra_periph_reset_deassert(struct clk *c);
void tegra_periph_reset_assert(struct clk *c); void tegra_periph_reset_assert(struct clk *c);
unsigned long clk_get_rate_all_locked(struct clk *c); unsigned long clk_get_rate_all_locked(struct clk *c);
void tegra_sdmmc_tap_delay(struct clk *c, int delay); void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
#endif #endif
...@@ -25,7 +25,6 @@ ...@@ -25,7 +25,6 @@
#define IRQ_LOCALTIMER 29 #define IRQ_LOCALTIMER 29
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
/* Primary Interrupt Controller */ /* Primary Interrupt Controller */
#define INT_PRI_BASE (INT_GIC_BASE + 32) #define INT_PRI_BASE (INT_GIC_BASE + 32)
#define INT_TMR1 (INT_PRI_BASE + 0) #define INT_TMR1 (INT_PRI_BASE + 0)
...@@ -178,6 +177,5 @@ ...@@ -178,6 +177,5 @@
#define NR_BOARD_IRQS 32 #define NR_BOARD_IRQS 32
#define NR_IRQS (INT_BOARD_BASE + NR_BOARD_IRQS) #define NR_IRQS (INT_BOARD_BASE + NR_BOARD_IRQS)
#endif
#endif #endif
/* /*
* linux/arch/arm/mach-tegra/include/mach/pinmux-t2.h * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
* *
* Copyright (C) 2010 Google, Inc. * Copyright (C) 2010 Google, Inc.
* *
...@@ -14,8 +14,8 @@ ...@@ -14,8 +14,8 @@
* *
*/ */
#ifndef __MACH_TEGRA_PINMUX_T2_H #ifndef __MACH_TEGRA_PINMUX_TEGRA20_H
#define __MACH_TEGRA_PINMUX_T2_H #define __MACH_TEGRA_PINMUX_TEGRA20_H
enum tegra_pingroup { enum tegra_pingroup {
TEGRA_PINGROUP_ATA = 0, TEGRA_PINGROUP_ATA = 0,
......
/*
* linux/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
*
* Copyright (C) 2010 Google, Inc.
* Copyright (C) 2010,2011 Nvidia, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __MACH_TEGRA_PINMUX_TEGRA30_H
#define __MACH_TEGRA_PINMUX_TEGRA30_H
enum tegra_pingroup {
TEGRA_PINGROUP_ULPI_DATA0 = 0,
TEGRA_PINGROUP_ULPI_DATA1,
TEGRA_PINGROUP_ULPI_DATA2,
TEGRA_PINGROUP_ULPI_DATA3,
TEGRA_PINGROUP_ULPI_DATA4,
TEGRA_PINGROUP_ULPI_DATA5,
TEGRA_PINGROUP_ULPI_DATA6,
TEGRA_PINGROUP_ULPI_DATA7,
TEGRA_PINGROUP_ULPI_CLK,
TEGRA_PINGROUP_ULPI_DIR,
TEGRA_PINGROUP_ULPI_NXT,
TEGRA_PINGROUP_ULPI_STP,
TEGRA_PINGROUP_DAP3_FS,
TEGRA_PINGROUP_DAP3_DIN,
TEGRA_PINGROUP_DAP3_DOUT,
TEGRA_PINGROUP_DAP3_SCLK,
TEGRA_PINGROUP_GPIO_PV0,
TEGRA_PINGROUP_GPIO_PV1,
TEGRA_PINGROUP_SDMMC1_CLK,
TEGRA_PINGROUP_SDMMC1_CMD,
TEGRA_PINGROUP_SDMMC1_DAT3,
TEGRA_PINGROUP_SDMMC1_DAT2,
TEGRA_PINGROUP_SDMMC1_DAT1,
TEGRA_PINGROUP_SDMMC1_DAT0,
TEGRA_PINGROUP_GPIO_PV2,
TEGRA_PINGROUP_GPIO_PV3,
TEGRA_PINGROUP_CLK2_OUT,
TEGRA_PINGROUP_CLK2_REQ,
TEGRA_PINGROUP_LCD_PWR1,
TEGRA_PINGROUP_LCD_PWR2,
TEGRA_PINGROUP_LCD_SDIN,
TEGRA_PINGROUP_LCD_SDOUT,
TEGRA_PINGROUP_LCD_WR_N,
TEGRA_PINGROUP_LCD_CS0_N,
TEGRA_PINGROUP_LCD_DC0,
TEGRA_PINGROUP_LCD_SCK,
TEGRA_PINGROUP_LCD_PWR0,
TEGRA_PINGROUP_LCD_PCLK,
TEGRA_PINGROUP_LCD_DE,
TEGRA_PINGROUP_LCD_HSYNC,
TEGRA_PINGROUP_LCD_VSYNC,
TEGRA_PINGROUP_LCD_D0,
TEGRA_PINGROUP_LCD_D1,
TEGRA_PINGROUP_LCD_D2,
TEGRA_PINGROUP_LCD_D3,
TEGRA_PINGROUP_LCD_D4,
TEGRA_PINGROUP_LCD_D5,
TEGRA_PINGROUP_LCD_D6,
TEGRA_PINGROUP_LCD_D7,
TEGRA_PINGROUP_LCD_D8,
TEGRA_PINGROUP_LCD_D9,
TEGRA_PINGROUP_LCD_D10,
TEGRA_PINGROUP_LCD_D11,
TEGRA_PINGROUP_LCD_D12,
TEGRA_PINGROUP_LCD_D13,
TEGRA_PINGROUP_LCD_D14,
TEGRA_PINGROUP_LCD_D15,
TEGRA_PINGROUP_LCD_D16,
TEGRA_PINGROUP_LCD_D17,
TEGRA_PINGROUP_LCD_D18,
TEGRA_PINGROUP_LCD_D19,
TEGRA_PINGROUP_LCD_D20,
TEGRA_PINGROUP_LCD_D21,
TEGRA_PINGROUP_LCD_D22,
TEGRA_PINGROUP_LCD_D23,
TEGRA_PINGROUP_LCD_CS1_N,
TEGRA_PINGROUP_LCD_M1,
TEGRA_PINGROUP_LCD_DC1,
TEGRA_PINGROUP_HDMI_INT,
TEGRA_PINGROUP_DDC_SCL,
TEGRA_PINGROUP_DDC_SDA,
TEGRA_PINGROUP_CRT_HSYNC,
TEGRA_PINGROUP_CRT_VSYNC,
TEGRA_PINGROUP_VI_D0,
TEGRA_PINGROUP_VI_D1,
TEGRA_PINGROUP_VI_D2,
TEGRA_PINGROUP_VI_D3,
TEGRA_PINGROUP_VI_D4,
TEGRA_PINGROUP_VI_D5,
TEGRA_PINGROUP_VI_D6,
TEGRA_PINGROUP_VI_D7,
TEGRA_PINGROUP_VI_D8,
TEGRA_PINGROUP_VI_D9,
TEGRA_PINGROUP_VI_D10,
TEGRA_PINGROUP_VI_D11,
TEGRA_PINGROUP_VI_PCLK,
TEGRA_PINGROUP_VI_MCLK,
TEGRA_PINGROUP_VI_VSYNC,
TEGRA_PINGROUP_VI_HSYNC,
TEGRA_PINGROUP_UART2_RXD,
TEGRA_PINGROUP_UART2_TXD,
TEGRA_PINGROUP_UART2_RTS_N,
TEGRA_PINGROUP_UART2_CTS_N,
TEGRA_PINGROUP_UART3_TXD,
TEGRA_PINGROUP_UART3_RXD,
TEGRA_PINGROUP_UART3_CTS_N,
TEGRA_PINGROUP_UART3_RTS_N,
TEGRA_PINGROUP_GPIO_PU0,
TEGRA_PINGROUP_GPIO_PU1,
TEGRA_PINGROUP_GPIO_PU2,
TEGRA_PINGROUP_GPIO_PU3,
TEGRA_PINGROUP_GPIO_PU4,
TEGRA_PINGROUP_GPIO_PU5,
TEGRA_PINGROUP_GPIO_PU6,
TEGRA_PINGROUP_GEN1_I2C_SDA,
TEGRA_PINGROUP_GEN1_I2C_SCL,
TEGRA_PINGROUP_DAP4_FS,
TEGRA_PINGROUP_DAP4_DIN,
TEGRA_PINGROUP_DAP4_DOUT,
TEGRA_PINGROUP_DAP4_SCLK,
TEGRA_PINGROUP_CLK3_OUT,
TEGRA_PINGROUP_CLK3_REQ,
TEGRA_PINGROUP_GMI_WP_N,
TEGRA_PINGROUP_GMI_IORDY,
TEGRA_PINGROUP_GMI_WAIT,
TEGRA_PINGROUP_GMI_ADV_N,
TEGRA_PINGROUP_GMI_CLK,
TEGRA_PINGROUP_GMI_CS0_N,
TEGRA_PINGROUP_GMI_CS1_N,
TEGRA_PINGROUP_GMI_CS2_N,
TEGRA_PINGROUP_GMI_CS3_N,
TEGRA_PINGROUP_GMI_CS4_N,
TEGRA_PINGROUP_GMI_CS6_N,
TEGRA_PINGROUP_GMI_CS7_N,
TEGRA_PINGROUP_GMI_AD0,
TEGRA_PINGROUP_GMI_AD1,
TEGRA_PINGROUP_GMI_AD2,
TEGRA_PINGROUP_GMI_AD3,
TEGRA_PINGROUP_GMI_AD4,
TEGRA_PINGROUP_GMI_AD5,
TEGRA_PINGROUP_GMI_AD6,
TEGRA_PINGROUP_GMI_AD7,
TEGRA_PINGROUP_GMI_AD8,
TEGRA_PINGROUP_GMI_AD9,
TEGRA_PINGROUP_GMI_AD10,
TEGRA_PINGROUP_GMI_AD11,
TEGRA_PINGROUP_GMI_AD12,
TEGRA_PINGROUP_GMI_AD13,
TEGRA_PINGROUP_GMI_AD14,
TEGRA_PINGROUP_GMI_AD15,
TEGRA_PINGROUP_GMI_A16,
TEGRA_PINGROUP_GMI_A17,
TEGRA_PINGROUP_GMI_A18,
TEGRA_PINGROUP_GMI_A19,
TEGRA_PINGROUP_GMI_WR_N,
TEGRA_PINGROUP_GMI_OE_N,
TEGRA_PINGROUP_GMI_DQS,
TEGRA_PINGROUP_GMI_RST_N,
TEGRA_PINGROUP_GEN2_I2C_SCL,
TEGRA_PINGROUP_GEN2_I2C_SDA,
TEGRA_PINGROUP_SDMMC4_CLK,
TEGRA_PINGROUP_SDMMC4_CMD,
TEGRA_PINGROUP_SDMMC4_DAT0,
TEGRA_PINGROUP_SDMMC4_DAT1,
TEGRA_PINGROUP_SDMMC4_DAT2,
TEGRA_PINGROUP_SDMMC4_DAT3,
TEGRA_PINGROUP_SDMMC4_DAT4,
TEGRA_PINGROUP_SDMMC4_DAT5,
TEGRA_PINGROUP_SDMMC4_DAT6,
TEGRA_PINGROUP_SDMMC4_DAT7,
TEGRA_PINGROUP_SDMMC4_RST_N,
TEGRA_PINGROUP_CAM_MCLK,
TEGRA_PINGROUP_GPIO_PCC1,
TEGRA_PINGROUP_GPIO_PBB0,
TEGRA_PINGROUP_CAM_I2C_SCL,
TEGRA_PINGROUP_CAM_I2C_SDA,
TEGRA_PINGROUP_GPIO_PBB3,
TEGRA_PINGROUP_GPIO_PBB4,
TEGRA_PINGROUP_GPIO_PBB5,
TEGRA_PINGROUP_GPIO_PBB6,
TEGRA_PINGROUP_GPIO_PBB7,
TEGRA_PINGROUP_GPIO_PCC2,
TEGRA_PINGROUP_JTAG_RTCK,
TEGRA_PINGROUP_PWR_I2C_SCL,
TEGRA_PINGROUP_PWR_I2C_SDA,
TEGRA_PINGROUP_KB_ROW0,
TEGRA_PINGROUP_KB_ROW1,
TEGRA_PINGROUP_KB_ROW2,
TEGRA_PINGROUP_KB_ROW3,
TEGRA_PINGROUP_KB_ROW4,
TEGRA_PINGROUP_KB_ROW5,
TEGRA_PINGROUP_KB_ROW6,
TEGRA_PINGROUP_KB_ROW7,
TEGRA_PINGROUP_KB_ROW8,
TEGRA_PINGROUP_KB_ROW9,
TEGRA_PINGROUP_KB_ROW10,
TEGRA_PINGROUP_KB_ROW11,
TEGRA_PINGROUP_KB_ROW12,
TEGRA_PINGROUP_KB_ROW13,
TEGRA_PINGROUP_KB_ROW14,
TEGRA_PINGROUP_KB_ROW15,
TEGRA_PINGROUP_KB_COL0,
TEGRA_PINGROUP_KB_COL1,
TEGRA_PINGROUP_KB_COL2,
TEGRA_PINGROUP_KB_COL3,
TEGRA_PINGROUP_KB_COL4,
TEGRA_PINGROUP_KB_COL5,
TEGRA_PINGROUP_KB_COL6,
TEGRA_PINGROUP_KB_COL7,
TEGRA_PINGROUP_CLK_32K_OUT,
TEGRA_PINGROUP_SYS_CLK_REQ,
TEGRA_PINGROUP_CORE_PWR_REQ,
TEGRA_PINGROUP_CPU_PWR_REQ,
TEGRA_PINGROUP_PWR_INT_N,
TEGRA_PINGROUP_CLK_32K_IN,
TEGRA_PINGROUP_OWR,
TEGRA_PINGROUP_DAP1_FS,
TEGRA_PINGROUP_DAP1_DIN,
TEGRA_PINGROUP_DAP1_DOUT,
TEGRA_PINGROUP_DAP1_SCLK,
TEGRA_PINGROUP_CLK1_REQ,
TEGRA_PINGROUP_CLK1_OUT,
TEGRA_PINGROUP_SPDIF_IN,
TEGRA_PINGROUP_SPDIF_OUT,
TEGRA_PINGROUP_DAP2_FS,
TEGRA_PINGROUP_DAP2_DIN,
TEGRA_PINGROUP_DAP2_DOUT,
TEGRA_PINGROUP_DAP2_SCLK,
TEGRA_PINGROUP_SPI2_MOSI,
TEGRA_PINGROUP_SPI2_MISO,
TEGRA_PINGROUP_SPI2_CS0_N,
TEGRA_PINGROUP_SPI2_SCK,
TEGRA_PINGROUP_SPI1_MOSI,
TEGRA_PINGROUP_SPI1_SCK,
TEGRA_PINGROUP_SPI1_CS0_N,
TEGRA_PINGROUP_SPI1_MISO,
TEGRA_PINGROUP_SPI2_CS1_N,
TEGRA_PINGROUP_SPI2_CS2_N,
TEGRA_PINGROUP_SDMMC3_CLK,
TEGRA_PINGROUP_SDMMC3_CMD,
TEGRA_PINGROUP_SDMMC3_DAT0,
TEGRA_PINGROUP_SDMMC3_DAT1,
TEGRA_PINGROUP_SDMMC3_DAT2,
TEGRA_PINGROUP_SDMMC3_DAT3,
TEGRA_PINGROUP_SDMMC3_DAT4,
TEGRA_PINGROUP_SDMMC3_DAT5,
TEGRA_PINGROUP_SDMMC3_DAT6,
TEGRA_PINGROUP_SDMMC3_DAT7,
TEGRA_PINGROUP_PEX_L0_PRSNT_N,
TEGRA_PINGROUP_PEX_L0_RST_N,
TEGRA_PINGROUP_PEX_L0_CLKREQ_N,
TEGRA_PINGROUP_PEX_WAKE_N,
TEGRA_PINGROUP_PEX_L1_PRSNT_N,
TEGRA_PINGROUP_PEX_L1_RST_N,
TEGRA_PINGROUP_PEX_L1_CLKREQ_N,
TEGRA_PINGROUP_PEX_L2_PRSNT_N,
TEGRA_PINGROUP_PEX_L2_RST_N,
TEGRA_PINGROUP_PEX_L2_CLKREQ_N,
TEGRA_PINGROUP_HDMI_CEC,
TEGRA_MAX_PINGROUP,
};
enum tegra_drive_pingroup {
TEGRA_DRIVE_PINGROUP_AO1 = 0,
TEGRA_DRIVE_PINGROUP_AO2,
TEGRA_DRIVE_PINGROUP_AT1,
TEGRA_DRIVE_PINGROUP_AT2,
TEGRA_DRIVE_PINGROUP_AT3,
TEGRA_DRIVE_PINGROUP_AT4,
TEGRA_DRIVE_PINGROUP_AT5,
TEGRA_DRIVE_PINGROUP_CDEV1,
TEGRA_DRIVE_PINGROUP_CDEV2,
TEGRA_DRIVE_PINGROUP_CSUS,
TEGRA_DRIVE_PINGROUP_DAP1,
TEGRA_DRIVE_PINGROUP_DAP2,
TEGRA_DRIVE_PINGROUP_DAP3,
TEGRA_DRIVE_PINGROUP_DAP4,
TEGRA_DRIVE_PINGROUP_DBG,
TEGRA_DRIVE_PINGROUP_LCD1,
TEGRA_DRIVE_PINGROUP_LCD2,
TEGRA_DRIVE_PINGROUP_SDIO2,
TEGRA_DRIVE_PINGROUP_SDIO3,
TEGRA_DRIVE_PINGROUP_SPI,
TEGRA_DRIVE_PINGROUP_UAA,
TEGRA_DRIVE_PINGROUP_UAB,
TEGRA_DRIVE_PINGROUP_UART2,
TEGRA_DRIVE_PINGROUP_UART3,
TEGRA_DRIVE_PINGROUP_VI1,
TEGRA_DRIVE_PINGROUP_SDIO1,
TEGRA_DRIVE_PINGROUP_CRT,
TEGRA_DRIVE_PINGROUP_DDC,
TEGRA_DRIVE_PINGROUP_GMA,
TEGRA_DRIVE_PINGROUP_GMB,
TEGRA_DRIVE_PINGROUP_GMC,
TEGRA_DRIVE_PINGROUP_GMD,
TEGRA_DRIVE_PINGROUP_GME,
TEGRA_DRIVE_PINGROUP_GMF,
TEGRA_DRIVE_PINGROUP_GMG,
TEGRA_DRIVE_PINGROUP_GMH,
TEGRA_DRIVE_PINGROUP_OWR,
TEGRA_DRIVE_PINGROUP_UAD,
TEGRA_DRIVE_PINGROUP_GPV,
TEGRA_DRIVE_PINGROUP_DEV3,
TEGRA_DRIVE_PINGROUP_CEC,
TEGRA_MAX_DRIVE_PINGROUP,
};
#endif
...@@ -2,6 +2,7 @@ ...@@ -2,6 +2,7 @@
* linux/arch/arm/mach-tegra/include/mach/pinmux.h * linux/arch/arm/mach-tegra/include/mach/pinmux.h
* *
* Copyright (C) 2010 Google, Inc. * Copyright (C) 2010 Google, Inc.
* Copyright (C) 2010,2011 Nvidia, Inc.
* *
* This software is licensed under the terms of the GNU General Public * This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and * License version 2, as published by the Free Software Foundation, and
...@@ -17,18 +18,13 @@ ...@@ -17,18 +18,13 @@
#ifndef __MACH_TEGRA_PINMUX_H #ifndef __MACH_TEGRA_PINMUX_H
#define __MACH_TEGRA_PINMUX_H #define __MACH_TEGRA_PINMUX_H
#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
#include "pinmux-t2.h"
#else
#error "Undefined Tegra architecture"
#endif
enum tegra_mux_func { enum tegra_mux_func {
TEGRA_MUX_RSVD = 0x8000, TEGRA_MUX_RSVD = 0x8000,
TEGRA_MUX_RSVD1 = 0x8000, TEGRA_MUX_RSVD1 = 0x8000,
TEGRA_MUX_RSVD2 = 0x8001, TEGRA_MUX_RSVD2 = 0x8001,
TEGRA_MUX_RSVD3 = 0x8002, TEGRA_MUX_RSVD3 = 0x8002,
TEGRA_MUX_RSVD4 = 0x8003, TEGRA_MUX_RSVD4 = 0x8003,
TEGRA_MUX_INVALID = 0x4000,
TEGRA_MUX_NONE = -1, TEGRA_MUX_NONE = -1,
TEGRA_MUX_AHB_CLK, TEGRA_MUX_AHB_CLK,
TEGRA_MUX_APB_CLK, TEGRA_MUX_APB_CLK,
...@@ -90,6 +86,49 @@ enum tegra_mux_func { ...@@ -90,6 +86,49 @@ enum tegra_mux_func {
TEGRA_MUX_VI, TEGRA_MUX_VI,
TEGRA_MUX_VI_SENSOR_CLK, TEGRA_MUX_VI_SENSOR_CLK,
TEGRA_MUX_XIO, TEGRA_MUX_XIO,
TEGRA_MUX_BLINK,
TEGRA_MUX_CEC,
TEGRA_MUX_CLK12,
TEGRA_MUX_DAP,
TEGRA_MUX_DAPSDMMC2,
TEGRA_MUX_DDR,
TEGRA_MUX_DEV3,
TEGRA_MUX_DTV,
TEGRA_MUX_VI_ALT1,
TEGRA_MUX_VI_ALT2,
TEGRA_MUX_VI_ALT3,
TEGRA_MUX_EMC_DLL,
TEGRA_MUX_EXTPERIPH1,
TEGRA_MUX_EXTPERIPH2,
TEGRA_MUX_EXTPERIPH3,
TEGRA_MUX_GMI_ALT,
TEGRA_MUX_HDA,
TEGRA_MUX_HSI,
TEGRA_MUX_I2C4,
TEGRA_MUX_I2C5,
TEGRA_MUX_I2CPWR,
TEGRA_MUX_I2S0,
TEGRA_MUX_I2S1,
TEGRA_MUX_I2S2,
TEGRA_MUX_I2S3,
TEGRA_MUX_I2S4,
TEGRA_MUX_NAND_ALT,
TEGRA_MUX_POPSDIO4,
TEGRA_MUX_POPSDMMC4,
TEGRA_MUX_PWM0,
TEGRA_MUX_PWM1,
TEGRA_MUX_PWM2,
TEGRA_MUX_PWM3,
TEGRA_MUX_SATA,
TEGRA_MUX_SPI5,
TEGRA_MUX_SPI6,
TEGRA_MUX_SYSCLK,
TEGRA_MUX_VGP1,
TEGRA_MUX_VGP2,
TEGRA_MUX_VGP3,
TEGRA_MUX_VGP4,
TEGRA_MUX_VGP5,
TEGRA_MUX_VGP6,
TEGRA_MUX_SAFE, TEGRA_MUX_SAFE,
TEGRA_MAX_MUX, TEGRA_MAX_MUX,
}; };
...@@ -105,6 +144,11 @@ enum tegra_tristate { ...@@ -105,6 +144,11 @@ enum tegra_tristate {
TEGRA_TRI_TRISTATE = 1, TEGRA_TRI_TRISTATE = 1,
}; };
enum tegra_pin_io {
TEGRA_PIN_OUTPUT = 0,
TEGRA_PIN_INPUT = 1,
};
enum tegra_vddio { enum tegra_vddio {
TEGRA_VDDIO_BB = 0, TEGRA_VDDIO_BB = 0,
TEGRA_VDDIO_LCD, TEGRA_VDDIO_LCD,
...@@ -115,10 +159,16 @@ enum tegra_vddio { ...@@ -115,10 +159,16 @@ enum tegra_vddio {
TEGRA_VDDIO_SYS, TEGRA_VDDIO_SYS,
TEGRA_VDDIO_AUDIO, TEGRA_VDDIO_AUDIO,
TEGRA_VDDIO_SD, TEGRA_VDDIO_SD,
TEGRA_VDDIO_CAM,
TEGRA_VDDIO_GMI,
TEGRA_VDDIO_PEXCTL,
TEGRA_VDDIO_SDMMC1,
TEGRA_VDDIO_SDMMC3,
TEGRA_VDDIO_SDMMC4,
}; };
struct tegra_pingroup_config { struct tegra_pingroup_config {
enum tegra_pingroup pingroup; int pingroup;
enum tegra_mux_func func; enum tegra_mux_func func;
enum tegra_pullupdown pupd; enum tegra_pullupdown pupd;
enum tegra_tristate tristate; enum tegra_tristate tristate;
...@@ -187,7 +237,7 @@ enum tegra_schmitt { ...@@ -187,7 +237,7 @@ enum tegra_schmitt {
}; };
struct tegra_drive_pingroup_config { struct tegra_drive_pingroup_config {
enum tegra_drive_pingroup pingroup; int pingroup;
enum tegra_hsm hsm; enum tegra_hsm hsm;
enum tegra_schmitt schmitt; enum tegra_schmitt schmitt;
enum tegra_drive drive; enum tegra_drive drive;
...@@ -208,6 +258,7 @@ struct tegra_pingroup_desc { ...@@ -208,6 +258,7 @@ struct tegra_pingroup_desc {
int funcs[4]; int funcs[4];
int func_safe; int func_safe;
int vddio; int vddio;
enum tegra_pin_io io_default;
s16 tri_bank; /* Register bank the tri_reg exists within */ s16 tri_bank; /* Register bank the tri_reg exists within */
s16 mux_bank; /* Register bank the mux_reg exists within */ s16 mux_bank; /* Register bank the mux_reg exists within */
s16 pupd_bank; /* Register bank the pupd_reg exists within */ s16 pupd_bank; /* Register bank the pupd_reg exists within */
...@@ -217,15 +268,23 @@ struct tegra_pingroup_desc { ...@@ -217,15 +268,23 @@ struct tegra_pingroup_desc {
s8 tri_bit; /* offset into the TRISTATE_REG_* register bit */ s8 tri_bit; /* offset into the TRISTATE_REG_* register bit */
s8 mux_bit; /* offset into the PIN_MUX_CTL_* register bit */ s8 mux_bit; /* offset into the PIN_MUX_CTL_* register bit */
s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */ s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */
s8 lock_bit; /* offset of the LOCK bit into mux register bit */
s8 od_bit; /* offset of the OD bit into mux register bit */
s8 ioreset_bit; /* offset of the IO_RESET bit into mux register bit */
}; };
extern const struct tegra_pingroup_desc tegra_soc_pingroups[]; typedef void (*pinmux_init) (const struct tegra_pingroup_desc **pg,
extern const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[]; int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
int *pgdrive_max);
int tegra_pinmux_set_tristate(enum tegra_pingroup pg, void tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
enum tegra_tristate tristate); const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
enum tegra_pullupdown pupd); void tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate);
int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd);
void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, void tegra_pinmux_config_table(const struct tegra_pingroup_config *config,
int len); int len);
...@@ -241,4 +300,3 @@ void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *conf ...@@ -241,4 +300,3 @@ void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *conf
void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config, void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
int len, enum tegra_pullupdown pupd); int len, enum tegra_pullupdown pupd);
#endif #endif
...@@ -21,6 +21,7 @@ ...@@ -21,6 +21,7 @@
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/irq.h> #include <linux/irq.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/of.h>
#include <asm/hardware/gic.h> #include <asm/hardware/gic.h>
...@@ -129,6 +130,11 @@ void __init tegra_init_irq(void) ...@@ -129,6 +130,11 @@ void __init tegra_init_irq(void)
gic_arch_extn.irq_unmask = tegra_unmask; gic_arch_extn.irq_unmask = tegra_unmask;
gic_arch_extn.irq_retrigger = tegra_retrigger; gic_arch_extn.irq_retrigger = tegra_retrigger;
gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), /*
IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); * Check if there is a devicetree present, since the GIC will be
* initialized elsewhere under DT.
*/
if (!of_have_populated_dt())
gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
} }
/* /*
* linux/arch/arm/mach-tegra/pinmux-t2-tables.c * linux/arch/arm/mach-tegra/pinmux-tegra20-tables.c
* *
* Common pinmux configurations for Tegra 2 SoCs * Common pinmux configurations for Tegra20 SoCs
* *
* Copyright (C) 2010 NVIDIA Corporation * Copyright (C) 2010 NVIDIA Corporation
* *
...@@ -29,6 +29,7 @@ ...@@ -29,6 +29,7 @@
#include <mach/iomap.h> #include <mach/iomap.h>
#include <mach/pinmux.h> #include <mach/pinmux.h>
#include <mach/pinmux-tegra20.h>
#include <mach/suspend.h> #include <mach/suspend.h>
#define TRISTATE_REG_A 0x14 #define TRISTATE_REG_A 0x14
...@@ -43,7 +44,7 @@ ...@@ -43,7 +44,7 @@
.reg = ((r) - PINGROUP_REG_A) \ .reg = ((r) - PINGROUP_REG_A) \
} }
const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = { static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
DRIVE_PINGROUP(AO1, 0x868), DRIVE_PINGROUP(AO1, 0x868),
DRIVE_PINGROUP(AO2, 0x86c), DRIVE_PINGROUP(AO2, 0x86c),
DRIVE_PINGROUP(AT1, 0x870), DRIVE_PINGROUP(AT1, 0x870),
...@@ -105,9 +106,13 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE ...@@ -105,9 +106,13 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE
.pupd_bank = 2, \ .pupd_bank = 2, \
.pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \ .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
.pupd_bit = pupd_b, \ .pupd_bit = pupd_b, \
.lock_bit = -1, \
.od_bit = -1, \
.ioreset_bit = -1, \
.io_default = -1, \
} }
const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = { static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
PINGROUP(ATA, NAND, IDE, NAND, GMI, RSVD, IDE, 0x14, 0, 0x80, 24, 0xA0, 0), PINGROUP(ATA, NAND, IDE, NAND, GMI, RSVD, IDE, 0x14, 0, 0x80, 24, 0xA0, 0),
PINGROUP(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 1, 0x80, 16, 0xA0, 2), PINGROUP(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 1, 0x80, 16, 0xA0, 2),
PINGROUP(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 2, 0x80, 22, 0xA0, 4), PINGROUP(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 2, 0x80, 22, 0xA0, 4),
...@@ -226,3 +231,14 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = { ...@@ -226,3 +231,14 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
PINGROUP(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 30), PINGROUP(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 30),
PINGROUP(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 28), PINGROUP(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 28),
}; };
void __devinit tegra20_pinmux_init(const struct tegra_pingroup_desc **pg,
int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
int *pgdrive_max)
{
*pg = tegra_soc_pingroups;
*pg_max = TEGRA_MAX_PINGROUP;
*pgdrive = tegra_soc_drive_pingroups;
*pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
}
This diff is collapsed.
This diff is collapsed.
...@@ -174,7 +174,7 @@ static int tegra_periph_clk_enable_refcount[3 * 32]; ...@@ -174,7 +174,7 @@ static int tegra_periph_clk_enable_refcount[3 * 32];
#define pmc_readl(reg) \ #define pmc_readl(reg) \
__raw_readl(reg_pmc_base + (reg)) __raw_readl(reg_pmc_base + (reg))
unsigned long clk_measure_input_freq(void) static unsigned long clk_measure_input_freq(void)
{ {
u32 clock_autodetect; u32 clock_autodetect;
clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET); clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
...@@ -278,18 +278,6 @@ static struct clk_ops tegra_clk_m_ops = { ...@@ -278,18 +278,6 @@ static struct clk_ops tegra_clk_m_ops = {
.disable = tegra2_clk_m_disable, .disable = tegra2_clk_m_disable,
}; };
void tegra2_periph_reset_assert(struct clk *c)
{
BUG_ON(!c->ops->reset);
c->ops->reset(c, true);
}
void tegra2_periph_reset_deassert(struct clk *c)
{
BUG_ON(!c->ops->reset);
c->ops->reset(c, false);
}
/* super clock functions */ /* super clock functions */
/* "super clocks" on tegra have two-stage muxes and a clock skipping /* "super clocks" on tegra have two-stage muxes and a clock skipping
* super divider. We will ignore the clock skipping divider, since we * super divider. We will ignore the clock skipping divider, since we
...@@ -1132,6 +1120,9 @@ static struct clk_ops tegra_periph_clk_ops = { ...@@ -1132,6 +1120,9 @@ static struct clk_ops tegra_periph_clk_ops = {
void tegra2_sdmmc_tap_delay(struct clk *c, int delay) void tegra2_sdmmc_tap_delay(struct clk *c, int delay)
{ {
u32 reg; u32 reg;
unsigned long flags;
spin_lock_irqsave(&c->spinlock, flags);
delay = clamp(delay, 0, 15); delay = clamp(delay, 0, 15);
reg = clk_readl(c->reg); reg = clk_readl(c->reg);
...@@ -1139,6 +1130,8 @@ void tegra2_sdmmc_tap_delay(struct clk *c, int delay) ...@@ -1139,6 +1130,8 @@ void tegra2_sdmmc_tap_delay(struct clk *c, int delay)
reg |= SDMMC_CLK_INT_FB_SEL; reg |= SDMMC_CLK_INT_FB_SEL;
reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT; reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT;
clk_writel(reg, c->reg); clk_writel(reg, c->reg);
spin_unlock_irqrestore(&c->spinlock, flags);
} }
/* External memory controller clock ops */ /* External memory controller clock ops */
......
...@@ -182,20 +182,28 @@ static struct irqaction tegra_timer_irq = { ...@@ -182,20 +182,28 @@ static struct irqaction tegra_timer_irq = {
static void __init tegra_init_timer(void) static void __init tegra_init_timer(void)
{ {
struct clk *clk; struct clk *clk;
unsigned long rate = clk_measure_input_freq(); unsigned long rate;
int ret; int ret;
clk = clk_get_sys("timer", NULL); clk = clk_get_sys("timer", NULL);
BUG_ON(IS_ERR(clk)); if (IS_ERR(clk)) {
clk_enable(clk); pr_warn("Unable to get timer clock."
" Assuming 12Mhz input clock.\n");
rate = 12000000;
} else {
clk_enable(clk);
rate = clk_get_rate(clk);
}
/* /*
* rtc registers are used by read_persistent_clock, keep the rtc clock * rtc registers are used by read_persistent_clock, keep the rtc clock
* enabled * enabled
*/ */
clk = clk_get_sys("rtc-tegra", NULL); clk = clk_get_sys("rtc-tegra", NULL);
BUG_ON(IS_ERR(clk)); if (IS_ERR(clk))
clk_enable(clk); pr_warn("Unable to get rtc-tegra clock\n");
else
clk_enable(clk);
#ifdef CONFIG_HAVE_ARM_TWD #ifdef CONFIG_HAVE_ARM_TWD
twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600); twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600);
......
...@@ -21,7 +21,12 @@ ...@@ -21,7 +21,12 @@
#include <linux/platform_data/tegra_usb.h> #include <linux/platform_data/tegra_usb.h>
#include <linux/irq.h> #include <linux/irq.h>
#include <linux/usb/otg.h> #include <linux/usb/otg.h>
#include <linux/gpio.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <mach/usb_phy.h> #include <mach/usb_phy.h>
#include <mach/iomap.h>
#define TEGRA_USB_DMA_ALIGN 32 #define TEGRA_USB_DMA_ALIGN 32
...@@ -574,6 +579,35 @@ static const struct hc_driver tegra_ehci_hc_driver = { ...@@ -574,6 +579,35 @@ static const struct hc_driver tegra_ehci_hc_driver = {
.port_handed_over = ehci_port_handed_over, .port_handed_over = ehci_port_handed_over,
}; };
static int setup_vbus_gpio(struct platform_device *pdev)
{
int err = 0;
int gpio;
if (!pdev->dev.of_node)
return 0;
gpio = of_get_named_gpio(pdev->dev.of_node, "nvidia,vbus-gpio", 0);
if (!gpio_is_valid(gpio))
return 0;
err = gpio_request(gpio, "vbus_gpio");
if (err) {
dev_err(&pdev->dev, "can't request vbus gpio %d", gpio);
return err;
}
err = gpio_direction_output(gpio, 1);
if (err) {
dev_err(&pdev->dev, "can't enable vbus\n");
return err;
}
gpio_set_value(gpio, 1);
return err;
}
static u64 tegra_ehci_dma_mask = DMA_BIT_MASK(32);
static int tegra_ehci_probe(struct platform_device *pdev) static int tegra_ehci_probe(struct platform_device *pdev)
{ {
struct resource *res; struct resource *res;
...@@ -590,6 +624,15 @@ static int tegra_ehci_probe(struct platform_device *pdev) ...@@ -590,6 +624,15 @@ static int tegra_ehci_probe(struct platform_device *pdev)
return -EINVAL; return -EINVAL;
} }
/* Right now device-tree probed devices don't get dma_mask set.
* Since shared usb code relies on it, set it here for now.
* Once we have dma capability bindings this can go away.
*/
if (!pdev->dev.dma_mask)
pdev->dev.dma_mask = &tegra_ehci_dma_mask;
setup_vbus_gpio(pdev);
tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL); tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL);
if (!tegra) if (!tegra)
return -ENOMEM; return -ENOMEM;
...@@ -640,6 +683,28 @@ static int tegra_ehci_probe(struct platform_device *pdev) ...@@ -640,6 +683,28 @@ static int tegra_ehci_probe(struct platform_device *pdev)
goto fail_io; goto fail_io;
} }
/* This is pretty ugly and needs to be fixed when we do only
* device-tree probing. Old code relies on the platform_device
* numbering that we lack for device-tree-instantiated devices.
*/
if (instance < 0) {
switch (res->start) {
case TEGRA_USB_BASE:
instance = 0;
break;
case TEGRA_USB2_BASE:
instance = 1;
break;
case TEGRA_USB3_BASE:
instance = 2;
break;
default:
err = -ENODEV;
dev_err(&pdev->dev, "unknown usb instance\n");
goto fail_phy;
}
}
tegra->phy = tegra_usb_phy_open(instance, hcd->regs, pdata->phy_config, tegra->phy = tegra_usb_phy_open(instance, hcd->regs, pdata->phy_config,
TEGRA_USB_PHY_MODE_HOST); TEGRA_USB_PHY_MODE_HOST);
if (IS_ERR(tegra->phy)) { if (IS_ERR(tegra->phy)) {
...@@ -773,6 +838,11 @@ static void tegra_ehci_hcd_shutdown(struct platform_device *pdev) ...@@ -773,6 +838,11 @@ static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
hcd->driver->shutdown(hcd); hcd->driver->shutdown(hcd);
} }
static struct of_device_id tegra_ehci_of_match[] __devinitdata = {
{ .compatible = "nvidia,tegra20-ehci", },
{ },
};
static struct platform_driver tegra_ehci_driver = { static struct platform_driver tegra_ehci_driver = {
.probe = tegra_ehci_probe, .probe = tegra_ehci_probe,
.remove = tegra_ehci_remove, .remove = tegra_ehci_remove,
...@@ -783,5 +853,6 @@ static struct platform_driver tegra_ehci_driver = { ...@@ -783,5 +853,6 @@ static struct platform_driver tegra_ehci_driver = {
.shutdown = tegra_ehci_hcd_shutdown, .shutdown = tegra_ehci_hcd_shutdown,
.driver = { .driver = {
.name = "tegra-ehci", .name = "tegra-ehci",
.of_match_table = tegra_ehci_of_match,
} }
}; };
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