Commit e1231dd6 authored by Aleksandar Markovic's avatar Aleksandar Markovic Committed by Ralf Baechle

MIPS: math-emu: CLASS.D: Zero bits 32-63 of the result

Fix content of CLASS.D output bits 32-63 to match hardware behavior.

Prior to this patch, bits 32-63 of CLASS.D output were not
initialized, causing different 32-63 bits content of CLASS.D, based on
circumstances. However, the hardware consistently returns all these
bits zeroed. The documentation is not clear whether these bits should
be zero or unpredictable. Since technically "all zero" case still can
be viewed as belonging to "unpredictable" class of results, it is
better to zero bits 32-63.
Signed-off-by: default avatarMiodrag Dinic <miodrag.dinic@imgtec.com>
Signed-off-by: default avatarGoran Ferenc <goran.ferenc@imgtec.com>
Signed-off-by: default avatarAleksandar Markovic <aleksandar.markovic@imgtec.com>
Cc: Douglas Leung <douglas.leung@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Maciej W. Rozycki <macro@imgtec.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Petar Jovanovic <petar.jovanovic@imgtec.com>
Cc: Raghu Gandham <raghu.gandham@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/17142/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 3ec404d8
...@@ -2144,8 +2144,8 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, ...@@ -2144,8 +2144,8 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
return SIGILL; return SIGILL;
DPFROMREG(fs, MIPSInst_FS(ir)); DPFROMREG(fs, MIPSInst_FS(ir));
rv.w = ieee754dp_2008class(fs); rv.l = ieee754dp_2008class(fs);
rfmt = w_fmt; rfmt = l_fmt;
break; break;
} }
......
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