Commit e2c0b51f authored by Marc Zyngier's avatar Marc Zyngier Committed by Oliver Upton

arm64: Allow the definition of UNKNOWN system register fields

The CCSIDR_EL1 register contains an UNKNOWN field (which replaces
fields that were actually defined in previous revisions of the
architecture).

Define an 'Unkn' field type modeled after the Res0/Res1 types
to allow such description. This allows the generation of

  #define CCSIDR_EL1_UNKN     (UL(0) | GENMASK_ULL(31, 28))

which may have its use one day. Hopefully the architecture doesn't
add too many of those in the future.
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Signed-off-by: default avatarAkihiko Odaki <akihiko.odaki@gmail.com>
Reviewed-by: default avatarMark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230112023852.42012-2-akihiko.odaki@daynix.comSigned-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
parent b7bfaa76
...@@ -98,6 +98,7 @@ END { ...@@ -98,6 +98,7 @@ END {
res0 = "UL(0)" res0 = "UL(0)"
res1 = "UL(0)" res1 = "UL(0)"
unkn = "UL(0)"
next_bit = 63 next_bit = 63
...@@ -112,11 +113,13 @@ END { ...@@ -112,11 +113,13 @@ END {
define(reg "_RES0", "(" res0 ")") define(reg "_RES0", "(" res0 ")")
define(reg "_RES1", "(" res1 ")") define(reg "_RES1", "(" res1 ")")
define(reg "_UNKN", "(" unkn ")")
print "" print ""
reg = null reg = null
res0 = null res0 = null
res1 = null res1 = null
unkn = null
next next
} }
...@@ -134,6 +137,7 @@ END { ...@@ -134,6 +137,7 @@ END {
res0 = "UL(0)" res0 = "UL(0)"
res1 = "UL(0)" res1 = "UL(0)"
unkn = "UL(0)"
define("REG_" reg, "S" op0 "_" op1 "_C" crn "_C" crm "_" op2) define("REG_" reg, "S" op0 "_" op1 "_C" crn "_C" crm "_" op2)
define("SYS_" reg, "sys_reg(" op0 ", " op1 ", " crn ", " crm ", " op2 ")") define("SYS_" reg, "sys_reg(" op0 ", " op1 ", " crn ", " crm ", " op2 ")")
...@@ -161,7 +165,9 @@ END { ...@@ -161,7 +165,9 @@ END {
define(reg "_RES0", "(" res0 ")") define(reg "_RES0", "(" res0 ")")
if (res1 != null) if (res1 != null)
define(reg "_RES1", "(" res1 ")") define(reg "_RES1", "(" res1 ")")
if (res0 != null || res1 != null) if (unkn != null)
define(reg "_UNKN", "(" unkn ")")
if (res0 != null || res1 != null || unkn != null)
print "" print ""
reg = null reg = null
...@@ -172,6 +178,7 @@ END { ...@@ -172,6 +178,7 @@ END {
op2 = null op2 = null
res0 = null res0 = null
res1 = null res1 = null
unkn = null
next next
} }
...@@ -190,6 +197,7 @@ END { ...@@ -190,6 +197,7 @@ END {
next_bit = 0 next_bit = 0
res0 = null res0 = null
res1 = null res1 = null
unkn = null
next next
} }
...@@ -215,6 +223,16 @@ END { ...@@ -215,6 +223,16 @@ END {
next next
} }
/^Unkn/ && (block == "Sysreg" || block == "SysregFields") {
expect_fields(2)
parse_bitdef(reg, "UNKN", $2)
field = "UNKN_" msb "_" lsb
unkn = unkn " | GENMASK_ULL(" msb ", " lsb ")"
next
}
/^Field/ && (block == "Sysreg" || block == "SysregFields") { /^Field/ && (block == "Sysreg" || block == "SysregFields") {
expect_fields(3) expect_fields(3)
field = $3 field = $3
......
...@@ -15,6 +15,8 @@ ...@@ -15,6 +15,8 @@
# Res1 <msb>[:<lsb>] # Res1 <msb>[:<lsb>]
# Unkn <msb>[:<lsb>]
# Field <msb>[:<lsb>] <name> # Field <msb>[:<lsb>] <name>
# Enum <msb>[:<lsb>] <name> # Enum <msb>[:<lsb>] <name>
......
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